Abstract: A memory system includes: a memory device including a plurality of memory blocks for storing data; a controller memory including a read data area for storing first data, which is read from a victim memory block among the plurality of memory blocks, and a write data area for storing second data, which is to be written into a target memory block among the plurality of memory blocks; and a controller suitable for reading the first data from the read data area, storing the first data into a host memory, and, when the first data stored in the host memory satisfies a predetermined condition, reading the first data from the host memory and storing the first data into the write data area.

Abstract: An apparatus comprises a processor to perform tile-based rendering to build a command buffer without knowledge whether the contents of a cache will be discarded, and a memory to store the command buffer. The processor is to determine a discard state of the cache prior to executing the command buffer, execute the command buffer, and discard or keep the contents of the cache according to the discard state. The command buffer can sample discard control from memory immediately before the processor executes the command buffer. The discard control in memory can be updated after the command buffer is queued and before the processor executes the command buffer.

Abstract: Backup storage is configured to automatically take one or more snapshots of a protected device. After a plurality of snapshots of the protected device have been automatically taken by the backup storage, the backup storage is communicated with in order to catalog metadata associated with the plurality of snapshots.

Abstract: A method for reducing reactivation time of services that includes examining page faults that occur during processing of a service after the service has been inactive to provide a plurality of prefetch groups, and formulating a prefetch decision tree from page fault data in the prefetch groups. Pages from an initial page table for the service following a reactivated service request are then compared with the prefetched pages in the resident memory in accordance with the prefetch decision tree. Pages in the page table that are not included in said prefetched pages are paged in. A process to provide to provide the service is executed using the page table. Executing the process substantially avoids page faults.

Abstract: A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.

Abstract: Devices, systems and methods are disclosed for quickly readying a device when charging a dead battery. For example, a device may enter a hibernation mode when the battery becomes critically low and may resume normal operation from the hibernation mode when an external power source is connected to the device. While the battery is critically low but the device is connected to the external power source, the device may generate a visible indication, such as a watermark, and apply the watermark to content to allow a user to control the device while indicating to the user that the battery is critically low and should not be removed from the external power source. Thus, the device may reduce user-perceived latency from when the external power source is connected to when the device resumes system interactivity (e.g., being responsive to user input).

Abstract: The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

Abstract: A method for a cache miss estimation includes; generating a variable range of a possible value of loop variables relevant to a specific array; generating first expression of number of times indicating the number of times the specific position of a specific loop is executed; generating second expression of number of times indicating the number of times the data of the access target is stored in the cache; generating third expression of number of times indicating the number of times the data of the access target is removed from the cache; generating fourth expression of number of times, from a generated conflict miss cause common expression, indicating the number of times the data of the access target is stored in the cache; and estimating a number of cache miss based on the difference between the first and the second expressions and the difference between the third and the forth expressions.

Abstract: Embodiments of the present system and method provide cache replacement in a victim exclusive cache using a snoop filter where replacement information is not lost during a re-reference back to the CPU. Replacement information is stored in a snoop filter, meaning that historical access data may be fully preserved and allows for more flexibility in the LLC re-insertion points, without additional bits stored in a L2 cache. The present system and method further include snoop filter replacement technique. The present system and method passes replacement information between a snoop filter and a victim exclusive cache (e.g., LLC) when transactions move cachelines to and from a master CPU. This maintains and advances existing replacement information for a cacheline that is removed from the victim exclusive cache on a read, as well as intelligently replaces and ages cachelines in the snoop filter.

Abstract: A processor includes a cache memory and a cache controller. The cache controller fetches first data from a first location of an information handling system, stores the first data to a first cache line of a plurality of cache lines, determines first proximity information for the first data based upon the first location, stores the first proximity information in a first proximity tag associated with the first cache line, and evicts the first cache line from the cache based upon the first proximity tag.

Abstract: Data processing systems and methods, according to various embodiments, perform privacy assessments and monitor new versions of computer code for updated features and conditions that relate to compliance with privacy standards. The systems and methods may obtain a copy of computer code (e.g., a software application or code associated with a website) that collects and/or uses personal data, and then automatically analyze the computer code to identify one or more privacy-related attributes that may impact compliance with applicable privacy standards. The system may be adapted to monitor one or more locations (e.g., an online software application marketplace, and/or a specified website) to determine whether the application or website has changed. The system may, after analyzing the computer code, display the privacy-related attributes, collect information regarding the attributes, and automatically notify one or more designated individuals (e.g.

Abstract: In a transactional memory environment, a computer-implemented method includes a first processor initiating a first transaction and encountering an abort condition. Responsive to the abort condition, an abort other request is communicated between the first processor and one or more additional processors. The one or more additional processors receive the abort other request, and, responsive to the abort other request, the one or more additional processors selectively abort a current second transaction based on the abort other request and an abort other condition. Optionally, the transactional memory environment supports a transaction category scheme, whereby each transaction has associated therewith a category identifier. In such embodiments, the abort other request includes an abort category identifier, and the abort other condition includes aborting the current second transaction if the abort category identifier matches the category identifier for the current second transaction.

Abstract: A data retransmission method provided according to an embodiment includes that: retransmitted data transmitted to User Equipment (UE) by a base station on a second carrier is received, the retransmitted data being data failed to be transmitted previously on a first carrier; and the received retransmitted data is merged with initially transmitted data received previously on the first carrier and corresponding to the retransmitted data. The embodiment may ensure timely retransmission after a data transmission failure, reduce a data retransmission delay and also reduce a packet loss phenomenon caused by a relatively long retransmission waiting time. Moreover, the UE may merge the received retransmitted data with the initially transmitted data, so that data transmission continuity is ensured, and network performance is improved.

Abstract: A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

Abstract: In one embodiment, a computer-implemented method executable by a server system to store data in a data cache and refresh the data based on a dynamic schedule is provided. The method includes: receiving, by a processor, data from a first resource; storing, by the processor, the data in a data cache; determining, by the processor, a type of the data, and an access frequency of the data; determining, by the processor, a dynamic schedule based on the type of the data, and the access frequency of the data; and refreshing the data cache with new data from the first resource based on the dynamic schedule.

Abstract: A content serving data processing system is configured for trending topic cache eviction management. The system includes a computing system communicatively coupled to different sources of content objects over a computer communications network. The system also includes a cache storing different cached content objects retrieved from the different content sources. The system yet further includes a cache eviction module. The module includes program code enabled to manage cache eviction of the content objects in the cache by marking selected ones of the content objects as invalid in accordance with a specified cache eviction strategy, detect a trending topic amongst the retrieved content objects, and override the marking of one of the selected ones of the content objects as invalid and keeping the one of the selected ones of the content objects in the cache when the one of the selected ones of the content objects relates to the trending topic.

Abstract: Methods and apparatus for managing data content among in-network caches of a communication network are provided. In some embodiments, multiple registers are maintained for indexing cached data content. Different data content is indexed in different registers based on parameters such as popularity or content freshness. Customized popularity estimators can be applied to each register, and data content may be indexed by different registers as parameters change. Less popular content can be removed from caches as required. In some embodiments, caches can be grouped into clusters, and deletion of data content from a cache may be modified or inhibited if the cluster still requires a copy of that data content. Data content can be moved between caches of a cluster based on popularity.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.

Abstract: The present disclosure discloses cache-based data transmission methods and apparatuses. The method is implemented as follows. An apparatus where a caching node is located reports a caching capability to a network side, and the caching node is configured to cache data. The network side sends a cache indicating parameter to the apparatus where the caching node is located, and maintains a data list. Wherein, the cache indicating parameter is configured to control the caching node to cache the data which has the property of high repetition probability and/or high cache utilization, and the data list is a list of the data cached in the caching node. When the caching node has cached data requested by a UE, the UE obtains the requested data from the caching node.

Abstract: A technique involves, from an incoming flow of data that includes a first stream from a first source and another stream from another source, placing data of the first stream into first storage segments and data of the other stream into other storage segments that are different from the first storage segments. The technique further involves, while some of the data of the first stream becomes invalidated over time and while a garbage collection service consolidates remaining valid data of the first stream together within the first segments, tracking the number of times the remaining valid data of the first stream is consolidated together within the first segments by the garbage collection service. The technique further involves comingling (i) remaining valid data of the first stream which has been consolidated together a predefined number of times within the first segments with (ii) the data of the other stream.

Abstract: Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.

Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.

Abstract: Caching data in a redundant array of independent disks (RAID) storage system including receiving an operation instruction targeting a location in an attached memory of the RAID storage system, wherein the attached memory temporarily stores data for storage on RAID storage devices, and wherein the operation instruction is one selected from a group consisting of a read instruction and a write instruction; redirecting, based on a content of the operation instruction, the operation instruction from the attached memory to the embedded memory on the RAID storage system; and servicing the operation instruction by accessing a portion of the embedded memory corresponding to the location in the attached memory of the RAID storage system.

Abstract: A memory controller, a memory system and a method of operating the memory controller are disclosed. A memory controller includes a CPU selecting a memory bank, a memory storing a first extended address associated with the selected memory bank, and a memory management unit (MMU) cloning the first extended address and storing the cloned first extended address as a second extended address. The MMU includes snoop logic that stores a first address corresponding to the first extended address, receives a second address from the CPU, compares the first address with the second address, and provides an update signal in response to the comparison of the first address and second address. The MMU also includes a cloning register that updates the second extended address with input data received from the CPU in response to the update signal. The memory and MMU are both directly connected to the CPU via a low latency interface.

Abstract: Caching data in a redundant array of independent disks (RAID) storage system including receiving an operation instruction targeting a location in an attached memory of the RAID storage system, wherein the attached memory temporarily stores data for storage on RAID storage devices, and wherein the operation instruction is one selected from a group consisting of a read instruction and a write instruction; redirecting, based on a content of the operation instruction, the operation instruction from the attached memory to the embedded memory on the RAID storage system; and servicing the operation instruction by accessing a portion of the embedded memory corresponding to the location in the attached memory of the RAID storage system.

Abstract: Aspects of branch prediction are suppressed for branch instructions executing in transactions, of a transactional memory environment, that are re-executions of previously aborted transactions.

Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.

Abstract: Systems and methods are described to reserve cache space of points of presence (“POPs”) within a content delivery network (“CDN”). A provider may submit a request to the CDN to reserve cache space on one or more POPs for data objects designated by that provider. Thereafter, the CDN may implement a provider-specific cache on the POPs of the CDN, which is distinct from a shared cache space on the POPs. The provider may further select a custom cache eviction policy for the provider-specific cache, which causes the POPs to manage data objects within the provider-specific cache according to the custom cache eviction policy, independently of a cache eviction policy applied to the shared cache.

Abstract: In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

Abstract: For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by defining and maintaining object dependency lists for each one of the cached objects for identifying objects upon which the cached objects are dependent. Maintaining cache consistency for 2 types of cache eviction policies is supported by maintaining an object dependency lists for each one of the cached objects for identifying objects dependent upon the cached object. Each of the objects in an object dependency list is updated when the object is updated.

Abstract: Embodiments are provided for enabling a dynamic management of a multi-tenant distributed database. According to certain aspects, a management module supports an interface that enables a customer to configure one or more consistency models for a service to be supported by the distributed database. The management module may determine computing resources within the distributed database that are needed to support the service according to the configured consistency model(s), and may instantiate the computing resources for testing and development of the service by the customer.

Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.

Abstract: A system comprises a processor, a memory fabric, and a fabric bridge coupled to the memory fabric and the processor. The fabric bridge may receive, from the processor a first eviction request comprising first eviction data, transmit, to the processor, a message indicating the fabric bridge has accepted the first eviction request, transmit a first write comprising the first eviction data to the fabric, receive, from the processor, a second eviction request comprising second eviction data, and transmit a second write comprising the second eviction data to the fabric. Responsive to transmitting the second write request, the fabric bridge may transmit, to the processor, a message indicating the fabric bridge accepted the second eviction request, determine that the first write and the second write have persisted, and transmit, to the processor, a notification to the processor responsive to determining that the first write and the second write have persisted.

Abstract: Systems and methods are directed to selectively bypassing allocation of cache lines in a cache. A bypass predictor table is provided with reuse counters to track reuse characteristics of cache lines, based on memory regions to which the cache lines belong in memory. A contender reuse counter provides an indication of a likelihood of reuse of a contender cache line in the cache pursuant to a miss in the cache for the contender cache line, and a victim reuse counter provides an indication of a likelihood of reuse for a victim cache line that will be evicted if the contender cache line is allocated in the cache. A decision whether to allocate the contender cache line in the cache or bypass allocation of the contender cache line in the cache is based on the contender reuse counter value and the victim reuse counter value.

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

Abstract: A computer has processors each including computation cores; memories, and an IO device, and includes NUMA nodes. The computer holds pattern management information to manage patterns and comprises a control module to determine a pattern to be applied to the computer. The pattern management information includes policy information including a policy on placement of a transfer-use memory area in the NUMA nodes, a policy on the placement of driver management information in the NUMA nodes, and a policy on allocation of computation cores that execute data transfer in the NUMA nodes, for each of the plurality of patterns. The control module applies each of the patterns to the computer based on the pattern management information, to measure IO performance in each of the patterns, and determine a pattern being highest in IO performance as a pattern to be applied to the computer.

Abstract: A means for assigning database objects to a backup storage group proceeds by collecting information related to a plurality of backup devices. The information collected includes speed of recovery, time to backup, and a recovery rank for each device. A backup pool is defined, using a database configuration parameter, to contain one or more of the plurality of backup devices. A determination is made to store a backup of a data object in a first device of the plurality of backup devices based on the collected information and a priority rank associated with the data object.

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

Abstract: When a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract: A method, a device, and a non-transitory storage medium provide for receiving registration information during a registration with a network, wherein the registration information includes a user identifier of a user registering with another network device of the network and an identifier of the other network device; determining whether registration information pertaining to a previous registration by the user with the network is stored; determining that the registration information pertaining to the previous registration is not stored; storing the received registration information based on determining that the registration information pertaining to the previous registration is not stored; selecting which application server of the network to transmit the received registration information; transmitting the received registration information to the application server based on the selecting; and using the received registration information to provide a service by the application server.

Abstract: Systems, devices, and methods for streaming or otherwise delivering media content over a network are provided. One exemplary method of streaming media content over a network using a RS-DVR system involves receiving, at the RS-DVR system, a request for a portion of the media content from a media player on a client device via the network, receiving, at the RS-DVR system, the portion of the media content from an origin server on the network, buffering the portion of the media content at the RS-DVR system, and transmitting the portion of the media content to the media player on the client device. The portion of media content may be transmitted using a modified transport layer protocol, and in some embodiments, marked as non-cacheable.

Abstract: Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request.

Abstract: A method, device, and non-transitory computer readable medium that manages replacement in a distributed cache environment includes determining a cache value of a new item associated with one of a plurality of I/O cache resources. A cache value of a least valuable other item in the plurality of I/O cache resources is obtained. A determination is made when the cache value of the new item is greater than the cache value of the least valuable other item in the plurality of I/O cache resources. The least valuable other item is replaced with the new item when the determination indicates the cache value of the new item is greater than the cache value of the least valuable other item.

Abstract: Hierarchical dynamic scheduling is disclosed. A plurality of physical nodes is included in a computer system. Each node includes a plurality of processors. Each processor includes a plurality of hyperthreads. An abstraction of the nodes, processors, and hyperthreads forms a hierarchy. Upon receiving an indication that a hyperthread should be assigned, a dynamic search of the hierarchy is performed, beginning at the leaf level, for a process to assign to the hyperthread.

Abstract: Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request.

Abstract: In one embodiment, transceiver circuitry includes a first-in-first-out (FIFO) circuit and a control logic circuit. The FIFO circuit receives data signals based on a first clock frequency and outputs stored data signals based on a second clock frequency. The stored data signals are transmitted out of the FIFO circuit only in response to a difference between a value of a write pointer of the FIFO circuit and a value of a read pointer of the FIFO circuit exceeding an empty threshold limit of the FIFO circuit. The control logic circuit may be utilized to adjust the empty threshold limit of the FIFO circuit.

Abstract: Data processing systems and methods, according to various embodiments, perform privacy assessments and monitor new versions of computer code for updated features and conditions that relate to compliance with privacy standards. The systems and methods may obtain a copy of computer code (e.g., a software application or code associated with a website) that collects and/or uses personal data, and then automatically analyze the computer code to identify one or more privacy-related attributes that may impact compliance with applicable privacy standards. The system may be adapted to monitor one or more locations (e.g., an online software application marketplace, and/or a specified website) to determine whether the application or website has changed. The system may, after analyzing the computer code, display the privacy-related attributes, collect information regarding the attributes, and automatically notify one or more designated individuals (e.g.

Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.