Abstract: Aspects include a computing devices, systems, and methods for hardware acceleration for inline caches in dynamic languages. An inline cache may be initialized for an instance of a dynamic software operation. A call of an initialized instance of the dynamic software operation may be executed by an inline cache hardware accelerator. The inline cache may be checked to determine that its data is current. When the data is current, the initialized instance of the dynamic software operation may be executed using the related inline cache data. When the data is not current, a new inline cache may be initialized for the instance of the dynamic software operation, including the not current data of a previously initialized instance of the dynamic software operation. The inline cache hardware accelerator may include an inline cache memory, a coprocessor, and/or a functional until one an inline cache pipeline connected to a processor pipeline.

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

Abstract: Techniques for universal cache management are described. In an example embodiment, a plurality of caches are allocated, in volatile memory of a computing device, to a plurality of data-processing instances, where each one of the plurality of caches is exclusively allocated to a separate one of the plurality of data-processing instances. A common cache is allocated in the volatile memory of the computing device, where the common cache is shared by the plurality of data-processing instances. Each instance of the plurality of data-processing instances is configured to: identify a data block in the particular cache allocated to that instance, where the data block has not been changed since the data block was last persistently written to one or more storage devices; cause the data block to be stored in the common cache; and remove the data block from the particular cache. Data blocks in the common cache are maintained without being persistently written to the one or more storage devices.

Abstract: For a cache in which a plurality of frequently accessed data segments are temporarily stored, reference count information of the plurality of data segments, in conjunction with least recently used (LRU) information, is used to determine a length of time to retain the plurality of data segments in the cache according to a predetermined weight, where notwithstanding the LRU information, those of the plurality of data segments having a higher reference counts are retained longer than those having lower reference counts.

Abstract: For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

Abstract: Systems and methods for performing an adaptive sustain write are disclosed. In one implementation, a controller of a non-volatile memory that is coupled with a host system monitors a rate at which the host system sends user data to the non-volatile memory system for storage and determines that the rate at which the host system sends user data to the non-volatile memory system for storage exceeds a threshold. The controller stores a first portion of the user data in one or more user capacity memory blocks of the non-volatile memory system. Additionally, the controller stores a second portion of the user data in one or more over-provisioning memory blocks of the non-volatile memory system after determining that the rate at which the host system sends data to the non-volatile memory system for storage exceeds the threshold.

Abstract: A data cache server may process requests from a data cache client to put, get, and delete data items into or from the data cache server. Each data item may be based on data in a data store. In response to each request to put a data item into the data cache server, the data cache server may determine whether any of the data in the data store on which the data item is based has or may have changed; put the data item into the data cache memory if none of the data in the data store on which the data item is based has been determined to have or maybe to have changed, and not put the data item into the data cache memory if data in the data store on which the data item is based has been determined to have or maybe to have changed.

Abstract: A method, computer program product, and computing system for storing a plurality of frontend data chunks within a cache system. The plurality of frontend data chunks correspond to a plurality of backend data chunks stored within a data array. A device weight is determined for each of the plurality of backend data chunks. The device weight is indicative of the type of storage device upon which each of the plurality of backend data chunks is stored within the data array. A deletion score is assigned to each of the plurality of frontend data chunks. Each deletion score is based, at least in part, upon the device weight determined for its corresponding backend data chunk.

Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.

Abstract: Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine.

Abstract: Stored data consistency is maintained at source and destination sites upon a failure when migrating a plurality of related virtual machines from the source site to the destination site. Consistency is maintained across a first site and a second site upon a failure during independent migrations of a plurality of virtual machines in a consistency group from the first site to the second site wherein at least a first virtual machine is executing at the first site and wherein at least a second virtual machine is executing at the second site, by performing a consistent snapshot at the first site of one or more storage volumes employed by the virtual machines in the consistency group; and performing a consistent snapshot at the second site of one or more storage volumes employed by the virtual machines in the consistency group.

Abstract: Circuitry for dynamically ordering the execution of multiple threads in parallel is presented. The circuitry may include a control circuit that controls the execution of multiple subsets of threads using multiple processing units in parallel. Each of the plurality of processing units may be associated with an adjustable order thread issuer that may receive a subset of threads and an order in which to execute the subset of threads from the control circuit. The adjustable order thread issuer may manage the processing unit by providing each thread from the subset of threads for execution to the processing unit in the specified order. The adjustable order thread issuer may adjust the order in which threads are issued in an effort to optimize shared resource usage and thus improve the performance of a multithreaded application.

Abstract: For browser cache cleanup, to consider for eviction a data item stored in a cache of a browser application in a device, a probability that the data item will be needed again during a period after the eviction is computed. A type is determined of a network that will be available at the device during the period. A cost is computed of obtaining the data item over a network of the type, from a location of the device during the period. Using the probability and the cost, a weight of the data item is computed. The weight is associated with the data item as a part of associating a set of weights with a set of data items in the cache. The data item is selected for eviction from the cache because the weight is a lowest weight in the set of weights.

Abstract: Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

Abstract: Systems and methods for cache load balancing by reclaimable block migration are described. In some embodiments, a computer system may include a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the computer system to: maintain a first list of reclaimable blocks that reside in a first caching device and a first advertised age for the oldest reclaimable block of the first list; maintain a second list of reclaimable blocks that reside in a second caching device and a second advertised age for the oldest reclaimable block of the second list; determine that the second advertised age is older than the first advertised age; and cause the oldest reclaimable block on the first list to be migrated from the first caching device to the second caching device.

Abstract: Various systems and methods for adjusting threshold access frequency based on cache pressure are disclosed. The threshold access frequency is adjusted based on a block of data in a storage volume that has an access frequency matching or exceeding the threshold access frequency. The threshold access frequency is used to determine whether the block of data should be inserted into the cache from the storage volume.

Abstract: A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.

Abstract: In an embodiment, a computing device may include a memory device that may be rendered unusable after a certain number of operations are performed on the memory device. The computing device may incorporate one or more techniques for protecting the memory device. Processing logic contained in the computing device may be configured to implement the techniques. The techniques may include, for example, acquiring a request to write or erase information stored in a memory device contained in a first computing device, saving the request for execution after a user visible event has been generated on the first computing device, generating the user visible event on the first computing device, and executing the saved request after the user visible event has been generated. In addition, the techniques may include reporting the request. The request may be reported to, for example, an anti-malware agent.

Abstract: Techniques provided herein allow for management of data. In various embodiments, systems and methods prune and retain data being managed by a data management system, where the managed data can include log data aggregated from one or more servers for analysis purposes. According to some embodiments, pruning can be triggered according to one or more constraints, such as the age of managed data (e.g., retain only 30 days of managed data) or the memory space required to store the managed data (e.g., retain only 100 GB worth of managed data). The constraints that trigger data pruning can be based on a data retention policy. When triggered, pruning can be performed on a fraction of the managed data stored based on the data retention policy (e.g., 3 days of full managed data, 27 days of pruned managed data). The pruning may be performed by sampling, at a desired rate, the managed data.

Abstract: An apparatus, system, and method are disclosed for coordinating storage requests in a multi-processor/multi-thread environment. An append/invalidate module generates a first append data storage command from a first storage request and a second append data storage command from a second storage request. The storage requests overwrite existing data with first and second data including where the first and second data have at least a portion of overlapping data. The second storage request is received after the first storage request. The append/invalidate module updates an index by marking data being overwritten as invalid. A restructure module updates the index based on the first data and updates the index based on the second data. The updated index is organized to indicate that the second data is more current than the first data regardless of processing order. The modules prevent access to the index until the modules have completed updating the index.

Abstract: Certain embodiments herein relate to using tagless access buffers (TABs) to optimize energy efficiency in various computing systems. Candidate memory references in an L1 data cache may be identified and stored in the TAB. Various techniques may be implemented for identifying the candidate references and allocating the references into the TAB. Groups of memory references may also be allocate to a single TAB entry or may be allocated to an extra TAB entry (such that two lines in the TAB may be used to store L1 data cache lines), for example, when a strided access pattern spans two consecutive L1 data cache lines. Certain other embodiments are related to data filter cache and multi-issue tagless hit instruction cache (TH-IC) techniques.

Abstract: In a computer, a logical partition for calculation in which an OS and an application operate and a logical partition for storage for providing a storage function are constructed. In the logical partition for calculation, a device corresponding to a storage device is provided, while the logical partition for storage provides a volume. A memory space that can be shared by the both logical partitions is prepared, and management information describing a sorting destination or a sorting method of an I/O request issued by an application is provided in the memory. If the logical partition for calculation receives an I/O request from the application, the partition refers to the management information and sorts the I/O request to the storage device or the logical partition for storage. The logical partition for storage processes the received I/O request by the storage function and transmits the result to the storage device.

Abstract: The present application is directed towards ASDR table contract renewal. In some embodiments, a core may cache an ASDR table entry received from an owner core such that when the entry is needed again the core does not need to re-request the entry from the owner core. As storing a cached copy of the entry allows the non-owner core to use an ASDR table entry without requesting the entry from the owner core, the owner core may be unaware of an ASDR table entry's use by a non-owner core. To ensure the owner core keeps the ASDR table entry alive, which the non-owner core has cached, the non-owner core may perform contract renewal for each of its recently used cached entries. The contract renewal method may include sending a message to the owner core that indicates which cached ASDR table entries the non-owner core has recently used or accessed. Responsive to receiving the message the owner core may reset a timeout period associated with the ASDR table entry.

Abstract: A method for handling input/output (I/O) in a data storage system comprising a RAID subsystem storing data according to a RAID level utilizing a parity scheme, where RAID stripes have been configured across a plurality of data storage devices. The method may include monitoring write requests to the RAID subsystem, identifying write requests destined for the same RAID stripe, and bundling the identified write requests for substantially simultaneous execution at the corresponding RAID stripe. Monitoring write requests to the RAID subsystem may include delaying at least some of the write requests to the RAID subsystem so as to build-up a queue of write requests. In some embodiments, identifying write requests and bundling the identified write requests may include identifying and bundling a number of write requests as required to perform a full stripe write to the corresponding RAID stripe.

Abstract: There is provide a memory controller, which substitutes a substitution page for an error page in a block including a plurality of pages in a non-volatile memory and secures a substitution block to substitute a page in the secured substitution block for the error page when the substitution page is insufficient in a block to which the error page belongs, the substitution page being assigned to the block to which the error page belongs, the substitution block being different from the block to which the error page belongs.

Abstract: Provided is a system and method for providing removable data storage elements as a cloud based storage system. More specifically, the method achieves this for at least one embodiment by receiving at least one generally random stream of data objects, each data object having at least one identifiable element. The method directs the selection of at least a first identifiable element. The method then orders the stream of data objects against the first identifiable element and disposes the data objects upon at least one of the removable data storage elements in accordance with the ordered stream of data objects. A system for performing the method is also disclosed.

Abstract: An approach to managing software components in a datacenter having virtualized components includes maintaining a suitable data construct for representing the virtualized elements. In embodiments, virtualized elements include knowledge relating to instantiations of virtual machines. Management of software components includes traversing a data representation of the datacenter, and assessing the compatibility of the software component with components in the datacenter that relate to the target of the software component.

Abstract: A method and apparatus for evicting cache lines from a cache memory includes receiving a request from one of a plurality of processors. The cache memory is configured to store a plurality of cache lines, and a given cache line includes an identifier indicating a processor that performed a most recent access of the given cache line. The method further includes selecting a cache line for eviction from a group of least recently used cache lines, where each cache line of the group of least recently used cache lines occupy a priority position less that a predetermined value, and then evicting the selected cache line.

Abstract: According to the present disclosure, there is disclosed an image display device and a memory management method thereof. According to an embodiment of the present disclosure, when a plurality of web pages are loaded and thus the memory space is insufficient, the loaded web pages may be implemented to be unloaded based on unloading priorities assigned by user preference, thereby minimizing data loss and securing insufficient memory space. Furthermore, when approaching an excess of memory capacity as a plurality of web pages are executed, it may be notified to the user in advance and the assigned unloading priorities may be provided to allow the user's selective unloading, thereby providing the user's convenience and enhancing the use efficiency of a web browser.

Abstract: A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.

Abstract: A method, computer program product, and computing system for associating a tracking file with a multi-portion data file located on a data array. The tracking file is configured to monitor the status of each portion of the multi-portion data file. At least one portion of the multi-portion data file is modified via a virtual machine executed on a first physical machine. The tracking file is updated to reflect the modification of the at least one portion of the multi-portion data file.

Abstract: According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

Abstract: Embodiments of the present invention may provide a system and method for providing real time analytics and reporting across networked applications. The real time analytics and reporting across networked applications may be provided by extending the reporting metadata and the corresponding design- and runtime-tools. Based on a cross NWAs MDAV-Definition, the corresponding metadata (subview and subquery definitions) may be generated and assigned to the corresponding NWA-Layer (NWA software component). At deployment and configuration time, the relevant views may be activated depending availability of underlying data. At runtime, an MDAV executer (e.g., a MDAV runtime engine) may run a distributed and optimized provisioning of reporting and analytics data. The data provisioning scheme may depend on selection parameters, filters, join conditions between parts in different NWAs, analytical functions defined in the report, and the locality of the data (local or remote).

Abstract: A system and method for a media processor separates the functions of topology creation and maintenance from the functions of processing data through a topology. The system includes a control layer including a topology generating element to generate a topology describing a set of input multimedia streams, one or more sources for the input multimedia streams, a sequence of operations to perform on the multimedia data, and a set of output multimedia streams, and a media processor to govern the passing of the multimedia data as described in the topology and govern the performance of the sequence of multimedia operations on the multimedia data to create the set of output multimedia streams. The core layer includes the input media streams, the sources for the input multimedia streams, one or more transforms to operate on the multimedia data, stream sinks, and media sinks to provide the set of output multimedia streams.

Abstract: A processing method has been claimed for reducing the average wait time of requests in a queue in a system environment where garbage collection may occur. In the method, a computer system treats as a unit each request in a queue and a completion time of garbage collection that may occur at the time of processing the request, and processes requests preferentially and systematically in ascending order of the processing times of the units including the garbage collection times, thereby, reducing the average wait time of the requests. While, the computer system managing the queue knows the remaining amount of heap just before processing a certain request, the computer system statistically calculates in advance the amounts of heap to be consumed on a request type basis and holds the values.

Abstract: A system, method, and computer-readable medium that facilitate efficient use of cache memory in a massively parallel processing system are provided. A residency time of a data block to be stored in cache memory or a disk drive is estimated. A metric is calculated for the data block as a function of the residency time. The metric may further be calculated as a function of the data block size. One or more data blocks stored in cache memory are evaluated by comparing a respective metric of the one or more data blocks with the metric of the data block to be stored. A determination is then made to either store the data block on the disk drive or flush the one or more data blocks from the cache memory and store the data block in the cache memory. In this manner, the cache memory may be more efficiently utilized by storing smaller data blocks with lesser residency times by flushing larger data blocks with significant residency times from the cache memory.

Abstract: In some aspects, finer grained parallelism is achieved by segmenting programmatic workloads into smaller discretized portions, where a first element can be indicative both of a configuration or program to be executed, and a first data set to be used in such execution, while a second element can be indicative of a second data element or group. The discretized portions can cause program execute on distributed processors. Approaches to selecting processors, and allocating local memory associated with those processors are disclosed. In one example, discretized portions that share a program have an anti-affinity to cause dispersion, for initial execution assignment. Flags, such as programmer and compiler generated flags can be used in determining such allocations. Workloads can be grouped according to compatibility of memory usage requirements.

Abstract: A file system to controls access to a tape library that selectively loads and unloads a plurality of cartridges from a plurality of slots to a drive for transmitting to the file system archived data retrieved from a particular cartridge. The file system includes a cache and receives a request from a requestor to access the tape library, estimates a first data transfer rate from an anticipated tape library operation completion duration and from a capacity of cached data to be transmitted from the cache to the requestor, initiates access to the tape library, and adapts the first data transfer rate to a second data transfer rate to transmit the capacity of the cached data to the requestor throughout the anticipated tape library operation completion duration.

Abstract: Systems and methods for improved caching with data recovery are disclosed. A write input/output (I/O) request is received from an application to write to a storage area network (SAN) LUN that is cached by a first intelligent storage adapter (ISA) using a cache LUN and mirrored by a second ISA using a mirror LUN. Write through caching is enabled, when either the first ISA or the second ISA has failed. The write I/O request is proceed by a surviving ISA from among the first ISA and the second ISA, where the surviving ISA sends the write I/O to the SAN LUN. Data is copied from a local storage device of the surviving ISA to a recovery LUN; and periodically data is also flushed from the local storage of the surviving ISA to the SAN LUN.

Abstract: Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.

Abstract: Methods, systems, and computer program products for providing reverse copy-on-write for improved cache utilization are disclosed. Examples generally relate to both physical and virtualized computer systems. A computer-implemented method may include detecting when a first task is to write to a memory page that is shared with a second task, creating a copy of the memory page for use by the second task, and modifying a memory mapping to associate the second task with the copy of the memory page. In a virtualized computer system, a hypervisor may detect when a first virtual machine is to write to a memory page shared with a second virtual machine, create a copy of the memory page for the second virtual machine, and adjust a memory mapping to associate the second virtual machine with the copy of the memory page.

Abstract: A processing method has been claimed for reducing the average wait time of requests in a queue in a system environment where garbage collection may occur. In the method, a computer system treats as a unit each request in a queue and a completion time of garbage collection that may occur at the time of processing the request, and processes requests preferentially and systematically in ascending order of the processing times of the units including the garbage collection times, thereby, reducing the average wait time of the requests. While, the computer system managing the queue knows the remaining amount of heap just before processing a certain request, the computer system statistically calculates in advance the amounts of heap to be consumed on a request type basis and holds the values.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Abstract: A distributed data warehouse system maintains data blocks on behalf of clients, and stores primary and secondary copies of data blocks on different disks or nodes in a cluster. The data warehouse system may back up data blocks in a key-value backup storage system. In response to a query targeting a data block previously stored in the cluster, the data warehouse system may determine whether a consistent, uncorrupted copy of the data block is available in the cluster (e.g., by applying a consistency check). If not (e.g., if a disk or node failed), the data warehouse system may automatically initiate an operation to restore the data block from the backup storage system, using a unique identifier of the data block to access a backup copy. The target data may be returned in a query response prior to restoring primary and secondary copies of the data block in the cluster.

Abstract: A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

Abstract: A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Abstract: A secure demand paging system (1020) includes a processor (1030) operable for executing instructions, an internal memory (1034) for a first page in a first virtual machine context, an external memory (1024) for a second page in a second virtual machine context, and a security circuit (1038) coupled to the processor (1030) and to the internal memory (1034) for maintaining the first page secure in the internal memory (1034).

Abstract: A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area.