Abstract: In one embodiment, a prefetching method implemented in a microprocessor, the prefetching method comprising: issuing all prefetches remaining for a memory block as L3 prefetches based on a set of conditions; and issuing L2 prefetches for cache lines corresponding to the L3 prefetches upon reaching the end of the memory block.

Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.

Abstract: In a typical data plane application, there is a packet dispatcher which receives packets from the underlying subsystem for distribution among various threads/processes for further processing. These threads/processes may run on various processing elements (PEs) and pass through multiple stages of processing. As new generation system-on-a-chip (SoC) architectures have multiple heterogeneous clusters with corresponding PEs, packet processing may traverse through multiple PEs in different clusters. Since latencies/performance for different clusters/PEs may be different, packet processing on the SoC may take a variable amount of time, which may lead to unpredictable latencies. The present disclosure provides embodiments to solve the problem of packet processing on heterogeneous clusters/PEs by providing a fast path enabler to the applications for SoC architecture awareness.

Abstract: Systems and methods for pre-fetching data based on memory usage patterns. An example method comprises: receiving a first memory access request identifying a first memory block; receiving a second memory access request identifying a second memory block; update a memory access tracking data structure by incrementing a sequence counter corresponding to a memory access sequence that references the first memory block and the second memory block; receive a third memory access request identifying a third memory block; identifying, based on the memory access tracking data structure, a sequence counter having a maximal value among sequence counters associated with memory access sequences that reference the third memory block; and pre-fetching a fourth memory block corresponding to the identified sequence counter.

Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Abstract: A device includes: a first interface circuit configured to communicate with a host processor; a second interface circuit configured to communicate with a memory comprising a plurality of storage regions; a cache memory including a plurality of cache lines configured to temporarily store data; and a controller configured to receive an integrated command from the host processor, the integrated command comprising memory operation information and cache management information, configured to control the memory based on a first command that is instructed according to the memory operation information, and configured to control at least one of the plurality of cache lines based on the cache management information.

Abstract: An apparatus comprises prefetch circuitry, and a cache having a plurality of entries to store data for access by processing circuitry and blocks of metadata for reference by the prefetch circuitry. The prefetch circuitry can detect one or more access sequences in dependence on training inputs derived from demand accesses processed by the cache in response to memory access operations performed by the processing circuitry. On detecting a given access sequence, this causes an associated given block of metadata providing information indicative of the given access sequence to be stored in a selected entry of the cache. Eviction control circuitry, responsive to a victimisation event, performs an operation to select a victim entry in the cache, the victim entry being selected from one or more candidate victim entries.

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple fabric interfaces in clients and a fabric. A packet transmitter in the fabric interface includes multiple queues, each for storing packets of a respective type, and a corresponding address history cache for each queue. Queue arbiters in the packet transmitter select candidate packets for issue and determine when address history caches on both sides of the link store the upper portion of the address. The packet transmitter sends a source identifier and a pointer for the request in the packet on the link, rather than the entire request address, which reduces the size of the packet. The queue arbiters support out-of-order issue from the queues. The queue arbiters detect conflicts with out-of-order issue and adjust the outbound packets and fields stored in the queue entries to avoid data corruption.

Abstract: Methods, systems, and computer-readable media for dynamic prefetching for database queries are disclosed. A query of a database is started according to a first prefetch policy. Before completing the query, the first prefetch policy is changed to a second prefetch policy. A portion of the query is performed according to the second prefetch policy.

Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises memory and a processor. The memory comprises a DRAM cache, a cache dedicated to the processor and one or more intermediate caches between the dedicated cache and the DRAM cache. The processor is configured to issue prefetch requests to prefetch data, issue data access requests to fetch the data and when one or more previously issued prefetch requests are determined to be inaccurate, issue a prefetch request to prefetch a tag, corresponding to the memory address of requested data in the DRAM cache. A tag look-up is performed at the DRAM cache without performing tag look-ups at the dedicated cache or the intermediate caches. The tag is prefetched from the DRAM cache without prefetching the requested data.

Abstract: An apparatus and method for managing packet transfer between a memory fabric having a physical layer interface higher data rate than a data rate of a physical layer interface of another device, receives incoming packets from the memory fabric physical layer interface wherein at least some of the packets include different instruction types. The apparatus and method determine a packet type of the incoming packet received from the memory fabric physical layer interface and when the determined incoming packet type is of a type containing an atomic request, the method and apparatus prioritizes transfer of the incoming packet with the atomic request over other packet types of incoming packets, to memory access logic that accesses local memory within an apparatus.

Abstract: Hardware-assisted Dynamic Random Access Memory (DRAM) row merging, including: identifying, by a memory controller, in a DRAM module, a plurality of rows storing identical data; storing, in a mapping table, data mapping one or more rows of the plurality of rows to another row; and excluding the one or more rows from a refresh the DRAM module.

Abstract: Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.

Abstract: A graph can be generated based on an access pattern associated with blocks of a memory device that have been accessed by a host system, wherein the graph comprises nodes representing at least a subset of the blocks that have been accessed by the host system and edges that are based on the access pattern, wherein each edge is associated with a respective probability value between a respective pair of nodes. A number of edges having respective probability values that satisfy a probability value threshold criterion can be determined. It can be determined whether the number of edges satisfies a decayed edge value condition. In response to determining that the number of edges does not satisfy the decayed edge value condition, the graph can be removed.

Abstract: Methods, systems, apparatus, and articles of manufacture to reduce memory latency when fetching pixel kernels are disclosed. An example apparatus includes first interface circuitry to receive a first request from a hardware accelerator at a first time including first coordinates of a first pixel disposed in a first image block, second interface circuitry to receive a second request including second coordinates from the hardware accelerator at a second time after the first time, and kernel retriever circuitry to, in response to the second request, determine whether the first image block is in cache storage based on a mapping of the second coordinates to a block tag, and, in response to determining that the first image block is in the cache storage, access, in parallel, two or more memory devices associated with the cache storage to transfer a plurality of image blocks including the first image block to the hardware accelerator.

Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.

Abstract: A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.

Abstract: Methods, systems, and devices for an enhanced instruction caching scheme are described. A memory controller may include a first closely-coupled memory component that is associated with storing data and control information and a second closely-coupled memory component that is associated with storing control information. The memory controller may be configured to retrieve data from the first memory closely-coupled component and control information from a second closely-coupled memory component. Control information may be stored in the first closely-coupled memory component, and a memory controller may access the control information stored in the first closely-coupled memory component by transferring, from the first closely-coupled memory component, the control information into the second closely-coupled memory component.

Abstract: Systems and methods described herein can take advantage of the caching abilities of the browser and the idle time of the user to prefetch tag libraries of one or more tags for execution in a subsequent content page. For example, these systems and methods can provide the ability to prefetch and not execute a tag library on a content page before it is required so the tag library is cached in the browser. When the browser hits the page that uses the tag library, the tag library can be quickly retrieved from memory and executed.

Abstract: A method for stream-processing biomedical data includes receiving, by a file system on a computing device, a first request for access to at least a first portion of a file stored on a remotely located storage device. The method includes receiving, by the file system, a second request for access to at least a second portion of the file. The method includes determining, by a pre-fetching component executing on the computing device, whether the first request and the second request are associated with a sequential read operation. The method includes automatically retrieving, by the pre-fetching component, a third portion of the requested file, before receiving a third request for access to least the third portion of the file, based on a determination that the first request and the second request are associated with the sequential read operation.

Abstract: A branch predictor of a processor includes one or more prediction structures, including a predicted branch address and predicted branch direction, that identify predicted branches. To reduce power consumption, the branch predictor selects one or more of the prediction structures that are not expected to provide useful branch prediction information and filters the selected structures such that the filtered structures are not used for branch prediction. The branch predictor thereby reduces the amount of power used for branch prediction without substantially reducing the accuracy of the predicted branches.

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

Abstract: An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and prefetch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of prefetch requests in dependence on reception of the trigger.

Abstract: In a server device, a memory is configured to store a folder corresponding to each of a plurality of users. User permissions are set for the folder to indicate whether access to the folder is allowed. A client device is configured to perform transmitting print data to the server device. The print data is associated with identification information for identifying a user. A set of program instructions causes the server device to perform: in response to receiving the print data from the client device, storing the print data in the folder corresponding to the user identified by the identification information associated with the print data. A printer is configured to perform: receiving an input of the identification information; identifying the folder corresponding to the user identified by the identification information; acquiring the print data stored in the folder; and printing an image based on the print data.

Abstract: A single instruction multiple thread (SIMT) processor includes execution circuitry, prefetch circuitry and prefetch strategy selection circuitry. The prefetch strategy selection circuitry serves to detect one or more characteristics of a stream of program instructions that are being executed to identify whether or not a given data access instruction within a program will be executed a plurality of times. The prefetch strategy to use is selected from a plurality of selectable prefetch strategies in dependence upon the detection of such detected characteristics.

Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Abstract: In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices coupled to the interface component. The interface component may be to cause a memory device of the plurality of memory devices to perform an operation in response to a command from the controller.

Abstract: An apparatus comprises processing circuitry to issue demand memory access requests to access data stored in a memory system. Stride pattern detection circuitry detects whether a sequence of demand target addresses specified by the demand memory access requests includes two or more constant stride sequences of addresses interleaved within the sequence of demand target addresses. Each constant stride sequence comprises addresses separated by intervals of a constant stride value. Prefetch control circuitry controls issuing of prefetch load requests to prefetch data from the memory system. The prefetch load requests specify prefetch target addresses predicted based on the constant stride sequences detected by the stride pattern detection circuitry.

Abstract: Techniques include receiving a backup request for backing up data on a production VVOL, to which is assigned physical space from storage devices in a first storage tier. When the production VVOL and a snapshot VVOL exist, and a write request is received to a data block on the production VVOL that is shared between the production VVOL and the snapshot VVOL, then the techniques include capturing a snapshot of the production VVOL by redirecting the write request to newly allocated space on the production VVOL, writing new data to the newly allocated space, and storing metadata referring to the original block(s) on the production VVOL. Based on an IO workload threshold, the techniques include copying, in a background process, the original version of the modified block from the production VVOL to a snapshot VVOL, to which is assigned physical storage space from storage devices in a second storage tier.

Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

Abstract: A verifiable computing system is presented. A worker computing device of the verifiable computing system receives a primary program and a verification logic that are generated based on a target function. The worker computing device includes a main processor and a coprocessor. The main processor is configured to execute the primary program and the coprocessor is configured to implement the verification logic. Telemetry is collected from the main processor executing the primary program and provided to the coprocessor. The coprocessor implementing the verification logic uses the telemetry to generate a proof. The proof is provided to a verifying computing device for determining whether the primary program is tampered with.

Abstract: There is provided a data processing apparatus and method for storing a plurality of prediction cache entries in a prediction cache with associativity greater than one comprising a plurality of prediction cache ways, each of the plurality of prediction entries defining an association between a prediction cache lookup address and target information; and storing a plurality of stream entries, each stream entry corresponding to a sequence of prediction cache lookup addresses and comprising: a stream identifier defined by two or more sequential prediction cache lookup addresses of the sequence, and a plurality of sequential way predictions, each way prediction of the plurality of sequential way predictions defining, for a given position in the sequence of prediction cache lookup addresses, a prediction cache way to be looked up in the prediction cache to identify a prediction entry associated with the prediction cache lookup address at the given position in the sequence.

Abstract: Memory prefetching in a processor comprises: identifying, in response to memory access instructions, a pattern of addresses; in response to a first memory access request corresponding to a sub-pattern of the pattern of addresses, prefetching a first address that is offset from the sub-pattern of addresses by a first lookahead value, wherein the first address is part of the pattern; measuring a memory access latency; determining, based on the memory access latency, a second lookahead value, wherein the second lookahead value is different from the first lookahead value; and in response to a second memory access request corresponding to the sub-pattern of the pattern of addresses, prefetching a second address, wherein the second address is part of the pattern, and wherein the second address is offset from the sub-pattern of addresses by the second lookahead value.

Abstract: Described is a computing system and method for differential cache block sizing for computing systems. The method for differential cache block sizing includes determining, upon a cache miss at a cache, a number of available cache blocks given a payload length of the main memory and a cache block size for the last level cache, generating a main memory request including at least one indicator for a missed cache block and any available cache blocks, sending the main memory request to the main memory to obtain data associated with the missed cache block and each of the any available cache blocks, storing the data received for the missed cache block in the cache; and storing the data received for each of the any available cache blocks in the cache depending on a cache replacement algorithm.

Abstract: A computer-implemented method includes fetching a fetch-packet containing a first hyper-block from a first address of a memory. The fetch-packet contains a bitwise distance from an entry point of the first hyper-block to a predicted exit point. The method further includes executing a first branch instruction of the first hyper-block. The first branch instruction corresponds to a first exit point. The first branch instruction includes an address corresponding to an entry point of a second hyper-block. The method also includes storing, responsive to executing the first branch instruction, a bitwise distance from the entry point of the first hyper-block to the first exit point. The method further includes moving a program counter from the first exit point of the first hyper-block to the entry point of the second hyper-block.

Abstract: A storage system has a volatile memory, a non-volatile memory, and a controller. The controller of the storage system can implement various mechanisms for improving random read performance. These mechanisms include improved read prediction cache management, using a pattern length for read prediction, and a time-based enhancement for read prediction. Each of these mechanisms can be used alone on in combination with some or all of the other mechanisms.

Abstract: A method for managing a readahead cache in a memory subsystem based on one or more active streams of read commands is described. The method includes receiving a read command that requests data from a memory component and determining whether the read command is part of an active stream of read commands based on a comparison of a set of addresses of the read command with one or more of (1) a command history table, which stores a set of command entries that each correspond to a received read command that has not been associated with an active stream, or (2) an active stream table, which stores a set of stream entries that each corresponds to active streams of read commands. The method further includes modifying a stream entry in the set of stream entries in response to determining that the read command is part of an active stream.

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

Abstract: A computer system for dynamic enforcement of store atomicity includes multiple processor cores, local cache memory for each processor core, a shared memory, a separate store buffer for each processor core for executed stores that are not yet performed and a coherence mechanism. A first processor core load on a first processor core receives a value at a first time from a first processor core store in the store buffer and prevents any other first processor core load younger than the first processor core load in program order from committing until a second time when the first processor core store is performed. Between the first time and the second time any load younger in program load than the first processor core load and having an address matched by coherence invalidation or an address matched by an eviction is squashed.

Abstract: A method of optimising a service rate of a buffer in a computer system having memory stores of first and second type is described. The method selectively services the buffer by routing data to each of the memory store of the first type and the second type based on read/write capacity of the memory store of the first type.

Abstract: Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Abstract: Indices or data structures used by an enterprise search system are stored across heterogenous storage devices. One or more characteristics associated with a data structure and one or more characteristics associated with a search query operator supported by the data structure are considered when determining which storage device should store each data structure.

Abstract: To reduce latency and bandwidth consumption in systems, systems and methods are provided for grouping multiple cache line request messages in a related and speculative manner. That is, multiple cache lines are likely to have the same state and ownership characteristics, and therefore, requests for multiple cache lines can be grouped. Information received in response can be directed to the requesting processor socket, and those speculatively received (not actually requested, but likely to be requested) can be maintained in queue or other memory until a request is received for that information, or until discarded to free up tracking space for new requests.

Abstract: A computer system includes a first computer and a second computer. The second computer includes, a minimum analysis dataset in which a data item serving as an analysis target and a repetition unit are defined in advance for each analysis target and an agent. The agent receives an analysis target data fetching designation including the minimum analysis dataset, a repetition range of repeating acquisition of data, and a repetition unit. The agent generates a first process that acquires data from the first computer and a first instance that executes processing within the first process on the basis of the repetition range and the repetition unit and activate the first instance to acquire the accumulated data from the first computer. When the processing of the first instance is completed, the agent generates a second process that executes analysis processing and a second instance that executes processing within the second process.

Abstract: In a cache stash relay, first data, from a producer device, is stashed in a shared cache of a data processing system. The first data is associated with first data addresses in a shared memory of the data processing system. An address pattern of the first data addresses is identified. When a request for second data, associated with a second data address, is received from a processing unit of the data processing system, any data associated with data addresses in the identified address pattern are relayed from the shared cache to a local cache of the processing unit if the second data address is in the identified address pattern. The relaying may include pushing the data from the shared cache to the local cache or a pre-fetcher of the processing unit pulling the data from the shared cache to the local cache in response to a message.

Abstract: A computer-implemented method manages I/O queues in a multi-tier storage system. The method includes identifying a set of subsystems in a multi-tier storage system, and each subsystem in the set of subsystems are communicatively connected to the storage system via a non-volatile memory express (NVMe) protocol and correlated to a tier of the multi-tier storage system. The method includes, determining a workload of each extent, wherein each extent of the set of extents are stored on one subsystem and the extents are accessed by an application. The method further includes, mapping, based on the workload of each extent, each extent to a core of the plurality of cores, wherein the mapping is configured to such that each core is balanced. The method includes, establishing, based on the mapping, an IOQ for each extent, wherein the IOQ is processed by the core to which it is mapped.

Abstract: Systems 100, 1000, methods, and machine-interpretable programming or other instruction products for the management of data transmission by multiple networked computing resources 106, 1106. In particular, the disclosure relates to the synchronization of related requests for transmitting data using distributed network resources.

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.

Abstract: Disclosed is a computer implemented method and system to dynamically adjust prefetch depth, the method comprising, identifying a first prefetch stream, wherein the first prefetch stream is identified in a prefetch request queue (PRQ), and wherein the first prefetch stream includes a first prefetch depth. The method also comprises determining a number of inflight prefetches, and comparing, a number of prefetch machines against the number of inflight prefetches, wherein each of the prefetch machines is configured to monitor one prefetch request. The method further includes adjusting, in response to the comparing, the first prefetch depth of the first prefetch stream.

Abstract: An adaptive-feedback-based read-look-ahead management system and method are provided. In one embodiment, a method for stream management is presented that is performed in a storage system. The method comprises performing a read look ahead operation for each of a plurality of streams; determining a success rate of the read look ahead operation of each of the plurality of streams; and allocating more of the memory for a stream that has a success rate above a threshold than for a stream that has a success rate below the threshold. Other embodiments are provided.