Look-ahead Patents (Class 711/137)
  • Patent number: 11146656
    Abstract: In some embodiments, an electronic device is disclosed for intelligently prefetching data via a computer network. The electronic device can include a device housing, a user interface, a memory device, and a hardware processor. The hardware processor can: communicate via a communication network; determine that the hardware processor is expected to be unable to communicate via the communication network; responsive to determining that the hardware processor is expected to be unable to communicate via the communication network, determine prefetch data to request prior to the hardware processor being unable to communicate via the communication network; request the prefetch data; receive and store the prefetch data prior to the hardware processor being unable to communicate via the communication network; and subsequent to the hardware processor being unable to communicate via the communication network, process the prefetch data with an application responsive to processing a first user input with the application.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 12, 2021
    Assignee: Tealium Inc.
    Inventors: Craig P. Rouse, Harry Cassell, Christopher B. Slovak
  • Patent number: 11144574
    Abstract: A temporal DB that stores data having been stored in a DB of a mainframe is provided in a DB dedicated device 20. During a DB update, when an application on a mainframe issues an update SQL, a DBMS updates the DB and stores an update log, and an update-log capturing unit periodically reads out the update log. In the DB dedicated device 20, an update-log applying unit updates the temporal DB based on the update log. During DB reference, when the application on the mainframe issues an inquiry SQL with inquiry target time attached, the DBMS transfers the inquiry SQL to the inquiry processing unit. In the DB dedicated device, the inquiry processing unit inquires the temporal DB about data for the inquiry target time and returns an inquiry result to the DBMS.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ritsuko Boh, Noriaki Kohno
  • Patent number: 11138116
    Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 5, 2021
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, Dmitri Kitariev, David J. Riddoch, Derek Roberts, Neil Turton
  • Patent number: 11119925
    Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 14, 2021
    Assignee: Arm Limited
    Inventors: Stuart David Biles, Graeme Peter Barnes
  • Patent number: 11119694
    Abstract: The invention discloses a solid-state drive control device and a learning-based solid-state drive data access method, wherein the method comprises the steps of: presetting a hash table, the hash table comprising more than one hash value, the hash value is used to record and represent data characteristics of data pages in the solid-state drive. Obtaining an I/O data stream of the solid-state drive, and obtaining a hash value corresponding to the I/O data stream in the hash table. Predicting a sequence of data pages and/or data pages that are about to be accessed by a preset first learning model. Prefetching data is performed in the solid-state drive based on an output result of the first learning model. Through the embodiment of the present invention, when predicting prefetched data, learning can be performed in real time to adapt to different application categories and access modes through adaptive adjustment parameters, so that better data prefetching performance can be obtained.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 14, 2021
    Assignee: SHENZHEN DAPU MICROELECTRONICS CO., LTD.
    Inventors: Jing Yang, Haibo He, Qing Yang
  • Patent number: 11115343
    Abstract: In one embodiment, a method comprises: receiving, by a transport layer executed by a processor circuit in an apparatus, a flow of application data having been originated by an executable application; storing, by the transport layer, the application data as transport layer packets in a buffer circuit in the apparatus, each transport layer packet having a corresponding transport sequence identifier identifying a corresponding position of the transport layer packet relative to a transmit order of the transport layer packets; and causing, by the transport layer, a plurality of deterministic network interface circuits to deterministically retrieve the transport layer packets, in the transmit order, from the buffer circuit for deterministic transmission across respective deterministic links, the transport sequence identifiers enabling a destination transport layer to recover the transmit order of the transport layer following the deterministic transmission across the deterministic links, regardless of order of rece
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: September 7, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Pascal Thubert, Patrick Wetterwald, Eric Michel Levy-Abegnoli
  • Patent number: 11113063
    Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 7, 2021
    Inventors: James David Dundas, Xiaoxin Fan, Shashank Nemawarkar, Madhu Saravana Sibi Govindan
  • Patent number: 11113199
    Abstract: Systems and methods for a low-overhead index for a cache. The index is used to access content or segments in the cache by storing at least an identifier and a location. The index is accessed using the identifier. The identifier may be shortened or be a short identifier. Because a collision may occur, the index may also include one or more meta-data values associated with the data segment. Collisions can be resolved by also comparing the metadata of the segment with the metadata stored in the index. If both the short identifier and metadata match those of the segment, the segment is likely in the cache and can be accessed. Segments can also be inserted into the cache.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 7, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Grant R. Wallace, Philip N. Shilane
  • Patent number: 11106583
    Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 31, 2021
    Assignee: Texas Instmments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria
  • Patent number: 11106779
    Abstract: A method for backing up data includes: receiving, by a driver in a host controller of a data storage device, an indication of a threatening event identifying one or more data files in the data storage device; delaying, by the driver, the threatening event; and backing up, by the driver, the one or more data files in the data storage device, prior to allowing the threatening event.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 31, 2021
    Assignee: CIGENT TECHNOLOGY, INC.
    Inventor: Tony Edward Fessel
  • Patent number: 11106390
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a first read command from a command queue is forwarded to a non-volatile memory (NVM) to request retrieval of a first set of readback data. While the NVM initiates in-process execution of the first read command, an expanded read command is issued to the NVM. The expanded read command supercedes the first read command and requests an expanded set of readback data that includes the first set of readback data as well as a second set of readback data. The second set of readback data may be associated with a second read command in the command queue. The NVM transfers the expanded set of readback data to a read buffer responsive to the expanded read command. The first and second read commands may be client reads, background reads or both.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 31, 2021
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Daniel John Benjamin, David W. Claude, Graham David Ferris, Ryan Charles Weidemann
  • Patent number: 11099996
    Abstract: In accordance with certain techniques, prefetching operation may be divided into two parts: a trigger part and an execution part, thereby simplifying the prefetching process. Such techniques may further support prefetching of concurrent flows and enhance anti-interference capability. Certain techniques involve receiving a read request for a memory page, and determining whether the read request satisfies a trigger condition of a prefetching operation for the memory page. These certain techniques further involve, in response to the read request satisfying the trigger condition, determining a window size of the prefetching operation based on historical information of historical prefetching operations for the memory page, and triggering, based on the window size, execution of the prefetching operation.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 24, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuo Lv, Ming Zhang
  • Patent number: 11099738
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a read request for data stored on a magnetic tape. For each portion of the requested data, an iterative process is performed. In preferred approaches, the iterative process includes: instructing a tape drive to read the portion of the requested data from the magnetic tape, and determining whether a copy of the portion of the requested data is located in a cache. In response to determining that a copy of the portion of the requested data is located in the cache, the tape drive is instructed to discard the portion of the requested data read from the magnetic tape. However, in response to determining that a copy of the portion of the requested data is not located in the cache, the portion of the requested data read from the magnetic tape is received from the tape drive.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Atsushi Abe, Setsuko Masuda
  • Patent number: 11093248
    Abstract: A computer system, processor, and method for processing information is disclosed that includes allocating a prefetch stream; providing a protection bubble to a plurality of cachelines for the allocated prefetch stream; accessing a cacheline; and preventing allocation of a different prefetch stream if the accessed cacheline is within the protection bubble. The system, processor and method in an aspect further includes providing a safety zone to a plurality of cachelines for the allocated prefetch stream, and advancing the prefetch stream if the accessed cacheline is one of the plurality of cachelines in the safety zone. In an embodiment, the number of cachelines within the safety zone is less than the number of cachelines in the protection bubble.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vivek Britto, Mohit Karve, George W. Rohrbaugh, III, Brian W. Thompto
  • Patent number: 11093404
    Abstract: Managing a cache memory in a storage system includes maintaining a first queue that stores data indictive of the read requests for a particular logical storage unit of the storage system in an order that the read requests are received by the storage system and maintaining a second queue that stores data indictive of the read requests for the particular logical storage unit in a sort order corresponding to page numbers of the read requests, the second queue persisting for a plurality of iterations of read requests. A read request is received and data indicative of the read request is placed in the first queue and in the second queue while maintaining the sort order of the second queue. The second queue is used to determine a prefetch metric that varies according to a number of adjacent elements in the second queue.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 17, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinicius Gottin, Jonas F. Dias, Hugo de Oliveira Barbalho, Romulo D. Pinho, Tiago Calmon
  • Patent number: 11086781
    Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 10, 2021
    Assignee: Arm Limited
    Inventors: Natalya Bondarenko, Florent Begon, Nathanael Premillieu, Pierre Marcel Laurent
  • Patent number: 11061679
    Abstract: A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Graphcore Limited
    Inventors: Alan Graham Alexander, Simon Christian Knowles, Mrudula Chidambar Gore
  • Patent number: 11057465
    Abstract: A distributed storage system places data in a time-based manner. The distributed storage system comprises a plurality of storage nodes for storing user data, and each user in at least one user is assigned a storage node sub-set for storing user data thereof. The distributed storage system monitors and records user accesses on storage nodes. The distributed storage system calculates a time-based access pattern of a user and time-based access patterns of the storage nodes outside the storage node sub-set of the user in the distributed storage system according to recorded user accesses. The distributed storage system adjusts the storage node sub-set of the user according to the time-based access pattern of the user and the time-based access patterns of the storage nodes outside the storage node sub-set of the user in the distributed storage system.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kuan Feng, Hao Chen Gui, Sheng Xu, Jun Wei Zhang
  • Patent number: 11055214
    Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 6, 2021
    Assignee: RAYMX MICROELECTRONICS, CORP.
    Inventors: Yen-Chung Chen, Jiunn-Jong Pan, Wei-Ren Hsu, Yi-Ting Wei
  • Patent number: 11048634
    Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 29, 2021
    Assignee: Fungible, Inc.
    Inventors: Wael Noureddine, Jean-Marc Frailong, Felix A. Marti, Charles Edward Gray, Paul Kim
  • Patent number: 11030135
    Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: June 8, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Greg Sadowski
  • Patent number: 11023239
    Abstract: A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: June 1, 2021
    Assignee: Graphcore Limited
    Inventors: Alan Graham Alexander, Simon Christian Knowles, Mrudula Chidambar Gore
  • Patent number: 11023180
    Abstract: A method for managing the file system of a computer terminal having a local memory, connected to a network comprising at least one remote storage device, comprising steps for periodically calculating the local or remote addressing of a digital file to be recorded, read or modified based on a periodically recalculated law, wherein said step of calculating the addressing is based on metadata present in said digital file to be processed, the access history of said file to be processed and the local tree structure of the files, said law is determined from a reference law, recalculated in the background, by processes based on a user's usage, to control the copying of a remote file to the local memory before access to said file is requested, and to erase local files for which the said law determines a usage indicator below a threshold value.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 1, 2021
    Assignee: MOORE
    Inventors: Paul Poupet, Benjamin Poilve, Robin Lambertz, Pierre Peltier
  • Patent number: 11016899
    Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Nikhil Narendradev Sharma, Eric Francis Robinson, Garrett Michael Drapala, Perry Willmann Remaklus, Jr., Joseph Gerald McDonald, Thomas Philip Speier
  • Patent number: 11010299
    Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method may include receiving a current read command and determining whether the current read command is a random read command, for example based on a data chunk length identified by the current read command. The method may further include updating a prior read command data structure with the current read command, for random read commands; determining a predicted next read command from the prior read command data structure based on the current read command; and pre-fetching data associated with the predicted next read command. Functionality for prediction of next read commands, or pre-fetch of predicted next read commands, may be turned on or off based on resource availability or prediction success rate measurements.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Eran Sharon, Idan Alrod
  • Patent number: 11003596
    Abstract: The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Richard C. Murphy
  • Patent number: 10999395
    Abstract: Disclosed is a dynamically adaptable stream segment prefetcher for prefetching stream segments from different media streams with different segment name formats and with different positioning of the segment name iterator within the differing segment name formats. In response to receiving a client issued request for a particular segment of a particular media stream, the prefetcher identifies the segment name format and iterator location using a regular expression matching to the client issued request. The prefetcher then generates prefetch requests based on the segment name format and incrementing a current value for the iterator in the segment name of the client issued request.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 4, 2021
    Assignee: Verizon Digital Media Services Inc.
    Inventor: Ravikiran Patil
  • Patent number: 10997080
    Abstract: In a method for address table cache management, a first logical address associated with a first read command may be received. The first logical address may be associated with a first segment of an address mapping table. A second logical address associated with a second read command may then be received. The second logical address may be associated with a second segment of the address mapping table. A correlation metric associating the first segment to the second segment may be increased in response to receiving the first logical address before the second logical address. The first logical address and second logical address may each map to a physical address within the address mapping table, and a mapping table cache may be configured to store two or more segments. The mapping table cache may then be managed based on the correlation metric.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Tzvi Eliash, Alex Bazarsky, Ariel Navon, Eran Sharon
  • Patent number: 10990403
    Abstract: An apparatus is described, comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of an outcome of the earlier instruction and a prediction of an outcome of the later instruction, wherein the prediction of the outcome of the earlier instruction causes a first control flow path to be executed. The apparatus also comprises storage circuitry to store the outcome of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the outcome of the earlier instruction being incorrect. When re-executing the later instruction in a second control flow path following the flush, the processing circuitry is adapted to generate the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry during execution of the first control flow path.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: April 27, 2021
    Assignee: Arm Limited
    Inventors: Joseph Michael Pusdesris, Yasuo Ishii, Muhammad Umar Farooq
  • Patent number: 10977041
    Abstract: A method includes allocating a first entry in a global completion table (GCT) on a processor, responsive to a first instruction group being dispatched, where the first entry corresponds to the first instruction group. A data value applicable to the first instruction group is identified. An offset value applicable to the first instruction group is calculated by subtracting, from the data value, a base value previously written to a second entry of the GCT for a second instruction group. The offset value is written in the first entry of the GCT in lieu of the data value.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Avery Francois, Richard Joseph Branciforte, Gregory William Alexander
  • Patent number: 10977062
    Abstract: A method and apparatus for starting a virtual machine. A specific implementation of the method comprises: acquiring, by a physical machine, a mirror image file required for starting a to-be-started target virtual machine from a distributed block storage system, in response to an entered instruction to start the target virtual machine; and starting the target virtual machine by using the mirror image file. The mirror image file required for starting the virtual machine is stored in the cloud-based distributed block storage system, and a virtual disk is mapped to the physical machine. When the physical machine needs to start the virtual machine, the mirror image file required for starting the virtual machine is acquired from the cloud-based distributed block storage system by reading the virtual disk.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 13, 2021
    Assignee: Beijing Baidu Netcom Science and Technology Co., Ltd.
    Inventor: Yu Zhang
  • Patent number: 10977036
    Abstract: An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Lu, Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Martin P. Dimitrov
  • Patent number: 10970082
    Abstract: A startup accelerating method is provided. In response to determining that a login process of an application is started up, pre-fetched data corresponding to a main process of the application is obtained. The pre-fetched data is loaded into a cache, the pre-fetched data being obtained according to a historical startup procedure for the main process. In response to determining that a startup of the login process is completed or determining that the main process is started up, the pre-fetched data is obtained, and a startup procedure of the main process is completed according to the pre-fetched data loaded in the cache. In response to at least portion of total data remaining upon determining that the startup of the login process is completed or determining that the main process is started up, the remaining at least portion of the total data is not pre-fetched, the total data corresponding to pre-fetched information.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: April 6, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Xue Wei, Qianwen Jin, Wenqiang Wang, Xuyang Li, Kang Gao, Qiru Chen
  • Patent number: 10972574
    Abstract: A method for stream-processing biomedical data includes receiving, by a file system on a computing device, a first request for access to at least a first portion of a file stored on a remotely located storage device. The method includes receiving, by the file system, a second request for access to at least a second portion of the file. The method includes determining, by a pre-fetching component executing on the computing device, whether the first request and the second request are associated with a sequential read operation. The method includes automatically retrieving, by the pre-fetching component, a third portion of the requested file, before receiving a third request for access to least the third portion of the file, based on a determination that the first request and the second request are associated with the sequential read operation.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: April 6, 2021
    Assignee: Seven Bridges Genomics Inc.
    Inventor: Nemanja Zbiljic
  • Patent number: 10970225
    Abstract: An apparatus and method are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element may be arranged to issue a cache maintenance operation request specifying a memory address range in order to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Arm Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
  • Patent number: 10963430
    Abstract: Shared workspaces with selective content item synchronization. In one embodiment, for example, a personal computing device is configured to send a request to a server of a cloud-based content management system to join a shared workspace. The personal computing device then receives content item metadata about content items associated with the shared workspace. The content item metadata allows a user of the personal computing device to browse a content item-folder hierarchy for the content items even if only some but not all of the content items have been downloaded and stored at the personal computing device.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: March 30, 2021
    Assignee: Dropbox, Inc.
    Inventors: Marcio von Muhlen, George Milton Underwood, IV, Anthony DeVincenzi, Nils Bunger, Colin Dunn, Adam Polselli, Sam Jau, Nathan Borror
  • Patent number: 10963258
    Abstract: A data processing apparatus is provided that includes lookup circuitry to provide first prediction data in respect of a first block of instructions and second prediction data in respect of a second block of instructions. First processing circuitry provides a first control flow prediction in respect of the first block of instructions using the first prediction data and second processing circuitry provides a second control flow prediction in respect of the second block of instructions using the second prediction data. The first block of instructions and the second block of instructions collectively define a prediction block and the lookup circuitry uses a reference to the prediction block as at least part of an index to both the first prediction data and the second prediction data.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 30, 2021
    Assignee: Arm Limited
    Inventors: Yasuo Ishii, Muhammad Umar Farooq, Chris Abernathy
  • Patent number: 10963388
    Abstract: According to one general aspect, an apparatus may include a multi-tiered cache system that includes at least one upper cache tier relatively closer, hierarchically, to a processor and at least one lower cache tier relatively closer, hierarchically, to a system memory. The apparatus may include a memory interconnect circuit hierarchically between the multi-tiered cache system and the system memory. The apparatus may include a prefetcher circuit coupled with a lower cache tier of the multi-tiered cache system, and configured to issue a speculative prefetch request to the memory interconnect circuit for data to be placed into the lower cache tier. The memory interconnect circuit may be configured to cancel the speculative prefetch request if the data exists in an upper cache tier of the multi-tiered cache system.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 30, 2021
    Inventors: Vikas Sinha, Teik Tan, Tarun Nakra
  • Patent number: 10949853
    Abstract: Methods and systems are presented for providing concurrent data retrieval and risk processing while evaluating a risk source of an online service provider. Upon receiving a request to evaluate the risk source, a risk analysis module may initiate one or more risk evaluation sub-processes to evaluate the risk source. Each risk evaluation sub-process may require different data related to the risk source to perform the evaluation. The risk analysis module may simultaneously retrieve the data related to the risk source and perform the one or more risk evaluation sub-processes such that the risk analysis module may complete a risk evaluation sub-process whenever the data required by the risk evaluation sub-process is made available.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 16, 2021
    Assignee: PayPal, Inc.
    Inventors: Srinivasan Manoharan, Vinesh Poruthikottu Chirakkil
  • Patent number: 10942854
    Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 10936317
    Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy David Anderson, Duc Quang Bui, Joseph Zbiciak, Sahithi Krishna, Soujanya Narnur
  • Patent number: 10929297
    Abstract: Providing control over processing of a prefetch request in response to conditions in a receiver of the prefetch request and to conditions in a source of the prefetch request. A processor generates a prefetch request and a tag that dictates processing the prefect request. A processor sends the prefetch request and the tag to a second processor. A processor generates a conflict indication based on whether a concurrent processing of the prefetch request and an atomic transaction by the second processor would generate a conflict with a memory access that is associated with the atomic transaction. Based on an analysis of the conflict indication and the tag, a processor processes (i) either the prefetch request or the atomic transaction, or (ii) both the prefetch request and the atomic transaction.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • Patent number: 10915244
    Abstract: Communicating data with a medium is provided. A cache is provided for storing target data of a file identified by an access request from an application of a host. The cache is divided into a read cache, a write cache, and an index cache. Responsive to receiving the access request: the medium is loaded onto a drive using a file system; target data is stored to the write cache and to the read cache; and the index file stored in the index cache is updated to reflect position metadata about the target data stored in the write cache. Responsive to initiating unloading of the medium from the drive: the updated index file stored in the index cache is written to the index partition of the medium; and the target data stored in the write cache is written onto a data partition of the medium without using the file system.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ashida, Tohru Hasegawa, Hiroshi Itagaki, Shinsuke Mitsuma, Terue Watanabe
  • Patent number: 10909045
    Abstract: A system, apparatus and method for accessing an electronic storage medium, such as a memory location storing a page table, or range table. A virtual address of the electronic storage medium is identified that corresponds to designated portions, such as a range of addresses of the electronic storage medium. The virtual address is translated to a corresponding physical address and one or more commands are identified as being excluded from execution in the designated portions of the electronic storage medium. This may be accomplished by using a routine such as mprotect( ). A fault indication, or decoration, is provided to meta-data associated with the physical address, which is associated with the designated portions of the electronic storage medium when excluded commands are provided to the physical address. A mechanism, such as hardware, is actuated when the fault is generated.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 2, 2021
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Curtis Glenn Dunham, Reiley Jeyapaul, Roxana Rusitoru
  • Patent number: 10901631
    Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory. The at least one memory comprise instructions which are executed by the at least one processor and configure the processor to implement a read-ahead manager for adaptive read-ahead in log structured storage. The read-ahead manager determines a probability value P representing a probability to read into cache a temporal environment for a front-end read for a given segment in user space in a log structured storage. Responsive to performing a front-end read of a record of the given segment in the log structured storage, the read-ahead manager performs pre-fetch of the temporal environment for the record with probability P.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Avraham Bab-Dinitz, Dorit Hakmon, Asaf Porat-Stoler, Yosef Shatsky
  • Patent number: 10884637
    Abstract: Some implementations relate to storage of data in a storage device with a plurality of chips. In some implementations, a computer-implemented method includes identifying a plurality of software applications that are configured to access data from the storage device, determining a data access pattern for each of the plurality of software applications, and based on the data access pattern, assigning a respective subset of the plurality of storage chips to each software application such that each storage chip is configured for access by a specific software application.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Elastic Flash Inc.
    Inventors: Darshan Rawal, Monish Suvarna, Arvind Pruthi
  • Patent number: 10884631
    Abstract: The method for preloading data of a file containing the following steps of defining a plurality of bins of predetermined sizes in a file, for each input and/or output operation executed on the file, determining the bin involved in the operation, counting the number of input and/or output operations executed in each bin of the file by taking into account only a predetermined number of last operations on the whole file, and when the sum of the operations counted in a bin is greater than a predetermined threshold, loading, in a memory medium, at least one area of the file determined on the basis of this bin.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Inventors: Simon Derr, Gaël Goret, Grégoire Pichon
  • Patent number: 10877896
    Abstract: A method for managing a readahead cache in a memory subsystem based on one or more active streams of read commands is described. The method includes receiving a read command that requests data from a memory component and determining whether the read command is part of an active stream of read commands based on a comparison of a set of addresses of the read command with one or more of (1) a command history table, which stores a set of command entries that each correspond to a received read command that has not been associated with an active stream, or (2) an active stream table, which stores a set of stream entries that each corresponds to active streams of read commands. The method further includes modifying a stream entry in the set of stream entries in response to determining that the read command is part of an active stream.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: December 29, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: David A. Palmer
  • Patent number: 10877815
    Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 29, 2020
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, David Cowperthwaite, Abhishek R. Appu, Joydeep Ray, Vasanth Ranganathan, Altug Koker, Balaji Vembu
  • Patent number: 10877895
    Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Luke Yen, Niket Choudhary, Pritha Ghoshal, Thomas Philip Speier, Brian Michael Stempel, William James McAvoy, Patrick Eibl