Abstract: In some embodiments, apparatuses and methods are provided to enable wide access to numerous different previously compiled forecast modeling. In some embodiments, a system is provided that enables wide access to forecasting, comprising: a forecast model database that maintains numerous different forecast models that when run produce resulting forecast data relevant to making business decisions; and a forecasting interface system configured to receive multiple different forecast requests for forecast request data, which comprises a forecast model index comprising identifiers of the numerous different predefined forecast models and for each of the numerous different forecast models relevance characteristics, wherein the forecasting interface system selects, for each received forecast request, a forecast model of the numerous different forecast models based on a relationship between the corresponding forecast request data and the relevance characteristics.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.

Abstract: A computer system comprising: a data storage medium comprising a plurality of storage devices configured to store data; and a data storage controller coupled to the data storage medium; wherein the data storage controller is configured to: receive read and write requests targeted to the data storage medium; schedule said read and write requests for processing by said plurality of storage devices; detect a given device of the plurality of devices is exhibiting an unscheduled behavior comprising variable performance by one or more of the plurality of storage devices, wherein the variable performance comprises at least one of a relatively high response latency or relatively low throughput; and schedule one or more reactive operations in response to detecting the occurrence of the unscheduled behavior, said one or more reactive operations being configured to cause the given device to enter a known state.

Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

Abstract: An apparatus is provided that includes cache circuitry that comprises a plurality of cache lines. The cache circuitry treats one or more of the cache lines as trace lines each having correlated addresses and each being tagged by a trigger address. Prefetch circuitry causes data at the correlated addresses stored in the trace lines to be prefetched.

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

Abstract: Apparatus, method, and system for enhancing data prefetching based on non-uniform memory access (NUMA) characteristics are described herein. An apparatus embodiment includes a system memory, a cache, and a prefetcher. The system memory includes multiple memory regions, at least some of which are associated with different NUMA characteristic (access latency, bandwidth, etc.) than others. Each region is associated with its own set of prefetch parameters that are set in accordance to their respective NUMA characteristics. The prefetcher monitors data accesses to the cache and generates one or more prefetch requests to fetch data from the system memory to the cache based on the monitored data accesses and the set of prefetch parameters associated with the memory region from which data is to be fetched. The set of prefetcher parameters may include prefetch distance, training-to-stable threshold, and throttle threshold.

Abstract: Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.

Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.

Abstract: A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Abstract: Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a large read operation can include receiving a pre-fetch command, a parameter list and a read command at a storage system. In certain examples, the pre-fetch command can provide an indication of the length of the parameter list, and the parameter list can provide location identifiers of the storage system from which the read command can sense the read data.

Abstract: Systems and methods for processing requests to execute a program code of a user use a message queue service to store requests when there are not enough resources to process the requests. The message queue service determines whether a request to be queued is associated with data that the program code needs in order to process the request. If so, the message queue service locates and retrieves the data and stores the data in a cache storage that provides faster access by the program code to the pre-fetched data. This provides faster execution of asynchronous instances of the program code.

Abstract: Methods and systems for automatically discovering data types required by a computer-based rule engine for evaluating a transaction request are presented. Multiple potential paths for evaluating the transaction request according to the rule engine are determined. An abstract syntax tree may be generated based on the rule engine to determine the multiple potential paths. Based on an initial set of data extracted from the transaction request, one or more potential paths that are determined to be irrelevant to evaluating the transaction request are identified. Types of data required to evaluate the transaction request according to the remaining potential paths are determined. Only data that corresponds to the determined types of data is retrieved to evaluate the transaction request.

Abstract: A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

Abstract: An arithmetic processing apparatus includes: a memory; and a processor coupled to the memory, wherein the processor: detects whether intervals of a plurality of addresses to be accessed by a memory access instruction that performs memory access to the plurality of addresses by a single instruction are all the same; decodes the memory access instruction as the single instruction when detecting that the intervals are all the same; decodes the memory access instruction as a plurality of instructions when detecting that the intervals are not all the same; and performs the memory access in accordance with the single instruction or the plurality of instructions.

Abstract: Methods and systems for using machine learning to automatically determine a data loading configuration for a computer-based rule engine are presented. The computer-based rule engine is configured to use rules to evaluate incoming transaction requests. Data of various data types may be required by the rule engine when evaluating the incoming transaction requests. The data loading configuration specifies pre-loading data associated with at least a first data type and lazy-loading data associated with at least a second data type. Statistical data such as use rates and loading times associated with the various data types may be supplied to a machine learning module to determine a particular loading configuration for the various data types. The computer-based rule engine then loads data according to the data loading configuration when evaluating a subsequent transaction request.

Abstract: Efficient pre-reading is performed in data transmission and reception between an Edge node and a Core node. An information processing device includes a storage device, outputs client request data based on a request of a client, and stores predetermined pre-read data in the storage device before the request of the client. The device includes: a relevance calculation module configured to calculate relevance between data based on an access history of the data; and a pre-reading and deletion module configured to determine data to be deleted from the storage device using the relevance when data having predetermined relevance with the client request data is to be stored to the storage device as the pre-read data and a storage capacity of the storage device is insufficient if at least one of the client request data and the pre-read data is to be stored to the storage device.

Abstract: The present application is directed towards systems and methods for identifying and grouping code objects into functional areas with boundaries crossed by entry points. An analysis agent may select a first functional area of a source installation of an application to be transformed to a target installation of the application from a plurality of functional areas of the source installation, each functional area comprising a plurality of associated code objects; and identify a first subset of the plurality of associated code objects of the first functional area having associations only to other code objects of the first functional area, and a second subset of the plurality of associated code objects of the first functional area having associations to code objects in additional functional areas, the second subset comprising entry points of the first functional area.

Abstract: In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch data into a data cache. A primary prefetch circuit may be configured to generate first prefetch requests in response to a demand access, and may be configured to invoke a second prefetch circuit in response to the demand access. The second prefetch circuit may implement a different prefetch mechanism than the first prefetch circuit. If the second prefetch circuit reaches a threshold confidence level in prefetching for the demand access, the second prefetch circuit may communicate an indication to the primary prefetch circuit. The primary prefetch circuit may reduce a number of prefetch requests generated for the demand access responsive to the communication from the second prefetch circuit.

Abstract: Methods, systems, apparatus, and articles of manufacture to reduce memory latency when fetching pixel kernels are disclosed. An example apparatus includes a prefetch kernel retriever to generate a block tag based on a first request from a hardware accelerator, the first request including first coordinates of a first pixel disposed in a first image block, a memory interface engine to store the first image block including a plurality of pixels including the pixel in a cache storage based on the block tag, and a kernel retriever to access two or more memory devices included in the cache storage in parallel to transfer a plurality of image blocks including the first image block when a second request is received including second coordinates of a second pixel disposed in the first image block.

Abstract: The method for performing read-ahead operations in the data storage systems is disclosed and includes determining a sequential address space interval of a request and a time of the request, placing the data into a read-ahead interval list if the address space interval exceeds a threshold, and placing the data about request intervals having a length shorter than the threshold into a random request interval list, identifying a partial overlap between the address space interval of the current request and the interval stored in one of the lists, verifying whether the length of the address space interval exceeds a threshold and if so—placing the data about this sequential interval into the read-ahead interval list, performing read-ahead of data.

Abstract: Disclosed is a computer implemented method to dynamically adjust prefetch depth, the method comprising sending, to a first prefetch machine, a first prefetch request configured to fetch a first data address from a first stream at a first depth to a lower level cache. The method also comprises sending, to a second prefetcher, a second prefetch request configured to fetch the first data address from the first stream at a second depth to a highest-level cache. The method further comprises determining the first data address is not in the lower level cache, determining, that the first prefetch request is in the first prefetch machine, and determining, in response to the first prefetch request being in the first prefetch machine, that the first stream is at steady state. The method comprises adjusting, in response to determining that the first stream is at steady state, the first depth.

Abstract: A graphics processing device comprises a set of compute units to execute multiple threads of a workload, a cache coupled with the set of compute units, and a prefetcher to prefetch instructions associated with the workload. The prefetcher is configured to use a thread dispatch command that is used to dispatch threads to execute a kernel to prefetch instructions, parameters, and/or constants that will be used during execution of the kernel. Prefetch operations for the kernel can then occur concurrently with thread dispatch operations.

Abstract: In some embodiments, an electronic device is disclosed for intelligently prefetching data via a computer network. The electronic device can include a device housing, a user interface, a memory device, and a hardware processor. The hardware processor can: communicate via a communication network; determine that the hardware processor is expected to be unable to communicate via the communication network; responsive to determining that the hardware processor is expected to be unable to communicate via the communication network, determine prefetch data to request prior to the hardware processor being unable to communicate via the communication network; request the prefetch data; receive and store the prefetch data prior to the hardware processor being unable to communicate via the communication network; and subsequent to the hardware processor being unable to communicate via the communication network, process the prefetch data with an application responsive to processing a first user input with the application.

Abstract: A temporal DB that stores data having been stored in a DB of a mainframe is provided in a DB dedicated device 20. During a DB update, when an application on a mainframe issues an update SQL, a DBMS updates the DB and stores an update log, and an update-log capturing unit periodically reads out the update log. In the DB dedicated device 20, an update-log applying unit updates the temporal DB based on the update log. During DB reference, when the application on the mainframe issues an inquiry SQL with inquiry target time attached, the DBMS transfers the inquiry SQL to the inquiry processing unit. In the DB dedicated device, the inquiry processing unit inquires the temporal DB about data for the inquiry target time and returns an inquiry result to the DBMS.

Abstract: A network interface device comprises a programmable interface configured to provide a device interface with at least one bus between the network interface device and a host device. The programmable interface is programmable to support a plurality of different types of a device interface.

Abstract: The invention discloses a solid-state drive control device and a learning-based solid-state drive data access method, wherein the method comprises the steps of: presetting a hash table, the hash table comprising more than one hash value, the hash value is used to record and represent data characteristics of data pages in the solid-state drive. Obtaining an I/O data stream of the solid-state drive, and obtaining a hash value corresponding to the I/O data stream in the hash table. Predicting a sequence of data pages and/or data pages that are about to be accessed by a preset first learning model. Prefetching data is performed in the solid-state drive based on an output result of the first learning model. Through the embodiment of the present invention, when predicting prefetched data, learning can be performed in real time to adapt to different application categories and access modes through adaptive adjustment parameters, so that better data prefetching performance can be obtained.

Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.

Abstract: In one embodiment, a method comprises: receiving, by a transport layer executed by a processor circuit in an apparatus, a flow of application data having been originated by an executable application; storing, by the transport layer, the application data as transport layer packets in a buffer circuit in the apparatus, each transport layer packet having a corresponding transport sequence identifier identifying a corresponding position of the transport layer packet relative to a transmit order of the transport layer packets; and causing, by the transport layer, a plurality of deterministic network interface circuits to deterministically retrieve the transport layer packets, in the transmit order, from the buffer circuit for deterministic transmission across respective deterministic links, the transport sequence identifiers enabling a destination transport layer to recover the transmit order of the transport layer following the deterministic transmission across the deterministic links, regardless of order of rece

Abstract: Systems and methods for a low-overhead index for a cache. The index is used to access content or segments in the cache by storing at least an identifier and a location. The index is accessed using the identifier. The identifier may be shortened or be a short identifier. Because a collision may occur, the index may also include one or more meta-data values associated with the data segment. Collisions can be resolved by also comparing the metadata of the segment with the metadata stored in the index. If both the short identifier and metadata match those of the segment, the segment is likely in the cache and can be accessed. Segments can also be inserted into the cache.

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

Abstract: A method for backing up data includes: receiving, by a driver in a host controller of a data storage device, an indication of a threatening event identifying one or more data files in the data storage device; delaying, by the driver, the threatening event; and backing up, by the driver, the one or more data files in the data storage device, prior to allowing the threatening event.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a first read command from a command queue is forwarded to a non-volatile memory (NVM) to request retrieval of a first set of readback data. While the NVM initiates in-process execution of the first read command, an expanded read command is issued to the NVM. The expanded read command supercedes the first read command and requests an expanded set of readback data that includes the first set of readback data as well as a second set of readback data. The second set of readback data may be associated with a second read command in the command queue. The NVM transfers the expanded set of readback data to a read buffer responsive to the expanded read command. The first and second read commands may be client reads, background reads or both.

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

Abstract: In accordance with certain techniques, prefetching operation may be divided into two parts: a trigger part and an execution part, thereby simplifying the prefetching process. Such techniques may further support prefetching of concurrent flows and enhance anti-interference capability. Certain techniques involve receiving a read request for a memory page, and determining whether the read request satisfies a trigger condition of a prefetching operation for the memory page. These certain techniques further involve, in response to the read request satisfying the trigger condition, determining a window size of the prefetching operation based on historical information of historical prefetching operations for the memory page, and triggering, based on the window size, execution of the prefetching operation.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving a read request for data stored on a magnetic tape. For each portion of the requested data, an iterative process is performed. In preferred approaches, the iterative process includes: instructing a tape drive to read the portion of the requested data from the magnetic tape, and determining whether a copy of the portion of the requested data is located in a cache. In response to determining that a copy of the portion of the requested data is located in the cache, the tape drive is instructed to discard the portion of the requested data read from the magnetic tape. However, in response to determining that a copy of the portion of the requested data is not located in the cache, the portion of the requested data read from the magnetic tape is received from the tape drive.

Abstract: A computer system, processor, and method for processing information is disclosed that includes allocating a prefetch stream; providing a protection bubble to a plurality of cachelines for the allocated prefetch stream; accessing a cacheline; and preventing allocation of a different prefetch stream if the accessed cacheline is within the protection bubble. The system, processor and method in an aspect further includes providing a safety zone to a plurality of cachelines for the allocated prefetch stream, and advancing the prefetch stream if the accessed cacheline is one of the plurality of cachelines in the safety zone. In an embodiment, the number of cachelines within the safety zone is less than the number of cachelines in the protection bubble.

Abstract: Managing a cache memory in a storage system includes maintaining a first queue that stores data indictive of the read requests for a particular logical storage unit of the storage system in an order that the read requests are received by the storage system and maintaining a second queue that stores data indictive of the read requests for the particular logical storage unit in a sort order corresponding to page numbers of the read requests, the second queue persisting for a plurality of iterations of read requests. A read request is received and data indicative of the read request is placed in the first queue and in the second queue while maintaining the sort order of the second queue. The second queue is used to determine a prefetch metric that varies according to a number of adjacent elements in the second queue.

Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry.

Abstract: A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.

Abstract: A distributed storage system places data in a time-based manner. The distributed storage system comprises a plurality of storage nodes for storing user data, and each user in at least one user is assigned a storage node sub-set for storing user data thereof. The distributed storage system monitors and records user accesses on storage nodes. The distributed storage system calculates a time-based access pattern of a user and time-based access patterns of the storage nodes outside the storage node sub-set of the user in the distributed storage system according to recorded user accesses. The distributed storage system adjusts the storage node sub-set of the user according to the time-based access pattern of the user and the time-based access patterns of the storage nodes outside the storage node sub-set of the user in the distributed storage system.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Abstract: Techniques are described in which a system having multiple processing units processes a series of work units in a processing pipeline, where some or all of the work units access or manipulate data stored in non-coherent memory. In one example, this disclosure describes a method that includes identifying, prior to completing processing of a first work unit with a processing unit of a processor having multiple processing units, a second work unit that is expected to be processed by the processing unit after the first work unit. The method also includes processing the first work unit, and prefetching, from non-coherent memory, data associated with the second work unit into a second cache segment of the buffer cache, wherein prefetching the data associated with the second work unit occurs concurrently with at least a portion of the processing of the first work unit by the processing unit.

Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.

Abstract: A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.

Abstract: A method for managing the file system of a computer terminal having a local memory, connected to a network comprising at least one remote storage device, comprising steps for periodically calculating the local or remote addressing of a digital file to be recorded, read or modified based on a periodically recalculated law, wherein said step of calculating the addressing is based on metadata present in said digital file to be processed, the access history of said file to be processed and the local tree structure of the files, said law is determined from a reference law, recalculated in the background, by processes based on a user's usage, to control the copying of a remote file to the local memory before access to said file is requested, and to erase local files for which the said law determines a usage indicator below a threshold value.

Abstract: Selective honoring of speculative memory-prefetch requests based on bandwidth constraint of a memory access path component(s) in a processor-based system. To reduce memory access latency, a CPU includes a request size in a memory read request of requested data to be read from memory and a request mode of the requested data as required or preferred. A memory access path component includes a memory read honor circuit configured to receive the memory read request and consult the request size and request mode of requested data in the memory read request. If the selective prefetch data honor circuit determines that bandwidth of the memory system is less than a defined bandwidth constraint threshold, then the memory read request is forwarded to be fulfilled, otherwise, the memory read request is downgraded to only include any requested required data.