Abstract: A processor may include a programmable memory prefetcher that includes a programmable hardware prefetch engine and a prefetch engine control register.

Abstract: Data processing circuitry comprises a processing element to execute successive iterations of program code to access a set of data elements in memory, each iteration accessing one or more respective data elements of the set; a data element structure memory to store a memory address relationship between the data elements of the set; and prefetch circuitry, responsive to an access by a current program code iteration to a current data element of the set, to detect, using the memory address relationship stored in the data element structure memory a memory address defining a subsequent data element to be accessed by a next program iteration and to initiate prefetching of at least a portion of the subsequent data element from memory.

Abstract: A method is provided that allows tracking boundaries of allocated memory blocks while still capturing byte-level properties. This is achieved with a particular shadow memory encoding scheme which captures boundaries and lengths of allocated memory blocks. Analyzing the shadow memory state allows detecting memory safety issues. In particular, for a memory location given by its address a, the proposed invention allows computing the following information: whether a has been allocated, whether a has been initialized, the start (base) address of the memory block a belongs to, the byte-length of the memory block a belongs to, the byte offset of a within its block. Such information allows for detection of specific memory safety issues at runtime.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory, the processor specifies a function including a branch instruction including one or more branch destinations in a program code; determines, based on a first number of arguments which are referenced in one branch destination among the one or more branch destinations, whether or not an argument of one function obtained by functionalizing the one branch destination are passable through a register; and converts, when determining to be passable, the specified function using one or more functions obtained by functionalizing the one or more branch destinations and does not convert, when determining not to be passable, the specified function.

Abstract: The method includes receiving a read request for a record stored on the tape. The tape is mounted in a tape drive which includes a data buffer. The tape stores data as a plurality of data sets. Each of the plurality of data sets contains one or more records. The method also includes buffering at least one of the plurality of data sets to the data buffer. At least one of the plurality of data sets includes a target data set which includes the requested record. The method also includes monitoring read operations on the tape to count a number of continuous read operations occurring in a backward direction relative to the tape. The method also includes, in response to the number of continuous read operations reaching a threshold, activating a read-behind mode that executes an extended buffer operation on data preceding a record requested to be read next.

Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.

Abstract: Embodiments of the invention are directed to methods for handling cache prefetch requests. The method includes receiving a request to prefetch data from main memory to a cache. The method further includes based on a determination that the prefetch request is a speculative prefetch request, determining if the cache is being used for transactional memory. The method further includes based on a determination that the cache is not being used for transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, processing the prefetch request. The method further includes based on a determination that the cache is being used for transactional memory, and a determination if the prefetch request can be processed without affecting transactional memory, rejecting the prefetch request.

Abstract: In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

Abstract: A system, method and computer program product for maintaining an age and validity of entries in a structure associated with a processor is disclosed. An age tracking matrix is created for the structure. Each row of the age tracking matrix corresponds to an entry of the structure and each column of the age tracking matrix corresponds to an entry of the structure. When initiating an entry: a row corresponding to the entry is determined and a field in the determined row that is on a diagonal of the matrix is marked. For each other field in the determined row, the values that are in a diagonal field that is in a same column of the field are copied into the field. A relative age of the entries is determined by counting a number of marked fields in a column of the age tracking matrix.

Abstract: In one embodiment, a processor includes: a core including a decode unit to decode a memory access instruction having a no-locality hint to indicate that data associated with the memory access instruction has at least one of non-spatial locality and non-temporal locality; and a locality controller to determine whether to override the no-locality hint based at least in part on one or more performance monitoring values. Other embodiments are described and claimed.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to receive a plurality of non-sequential memory access commands directed to the set of non-volatile memory cells, predict a predicted memory access command based on the plurality of non-sequential memory access commands, and access the set of non-volatile memory cells according to the predicted memory access command.

Abstract: A solution is provided for selectively caching streaming media based on playback data associated with the streaming media. Each media stream is divided into a number of media chunks. Spatial locality and temporal locality of each media chunk is analyzed based on playback data of the media chunk and the corresponding media stream. Based on the spatial locality and temporal locality, a spatial score and temporal score are generated, respectively. Aggregation of the spatial score and temporal score produces a final score for the media chunk. The media chunks are ranked based on their final scores, where all or a number of media chunks are selected based on their rankings for being cached. The ranking of a cached media chunk decays over time, and the ranking of a cached media chunk is dynamically recalculated when another video chunk is to be cached.

Abstract: A processor includes a prefetcher that prefetches data in response to memory accesses, wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table and the associated MATs of the memory accesses.

Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Abstract: In an embodiment, a processor comprises a prefetch history array and a prefetch circuit. The prefetch history array comprises a plurality of entries corresponding to prefetch addresses, each entry of the plurality of entries comprising a sublength value associated with a frequency that a stride is repeated. The prefetch circuit is to: for each entry of the plurality of entries, adjust the sublength value based on stride matches for an address of the entry; adjust a short stream counter based on the sublength values of the plurality of entries in the prefetch history array; determine whether the short stream counter has exceeded a throttling threshold; and in response to a determination that the short stream counter has exceeded the throttling threshold, throttle a prefetch level of the prefetch circuit. Other embodiments are described and claimed.

Abstract: A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

Abstract: Methods and devices for graphics shading in a computing device. The methods and devices may include receiving a respective cache line of a plurality of cache lines of a shader stored in a memory, wherein the respective cache line and one or more other ones of the plurality of cache lines include at least one jump instruction. Further, the methods and devices may include executing the respective cache line of the shader and skipping to a next portion of the plurality of cache lines based on the at least one jump instruction. Moreover, the methods and devices may include executing one or more prefetchers contemporaneously with the shader in response to the at least one jump instruction, each prefetcher requesting a subsequent one of the plurality of cache lines from the memory, wherein each prefetcher corresponds to a respective jump instruction.

Abstract: Described are techniques for determining a confidence value associated with the probability that a user will access a particular second user interface by interacting with a first user interface. The confidence value may be determined based on user interaction data indicative of prior interactions by the user. Based on the confidence value, the second user interface may be pre-generated, in advance of user interaction with the first user interface. If the user interacts with the first user interface in a manner that would cause presentation of the second user interface, the user may be provided with the second user interface promptly, avoiding the latency that would normally be experienced during the time that the second user interface is generated. Pre-generation of only the user interfaces indicated by the user interaction data may limit unnecessary use of computing resources.

Abstract: A prefetch circuit may include a memory, each entry of which may store an address and other prefetch data used to generate prefetch requests. For each entry, there may be at least one “quality factor” (QF) that may control prefetch request generation for that entry. A global quality factor (GQF) may control generation of prefetch requests across the plurality of entries. The prefetch circuit may include one or more additional prefetch mechanisms. For example, a stride-based prefetch circuit may be included that may generate prefetch requests for strided access patterns having strides larger than a certain stride size. Another example is a spatial memory streaming (SMS)-based mechanism in which prefetch data from multiple evictions from the memory in the prefetch circuit is captured and used for SMS prefetching based on how well the prefetch data appears to match a spatial memory streaming pattern.

Abstract: Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.

Abstract: Described is a startup accelerating method and apparatus. The method includes: obtaining, when it is monitored that a login process of an application is started up, pre-fetched data corresponding to a main process of the application, and loading the obtained pre-fetched data into a cache, the pre-fetched data being obtained according to a historical startup procedure for the main process of the application; stopping, when it is monitored that the startup of the login process is completed or it is monitored that the main process of the application is started up, obtaining the pre-fetched data corresponding to the main process of the application; and completing a startup procedure of the main process according to the pre-fetched data loaded in the cache. The apparatus includes: an obtaining module, a stopping module and a startup module.

Abstract: A storage cloud enabled platform includes storage nodes and application nodes which are the part of the same operating environment. The storage nodes and computation nodes are interconnected inside platform via an interface to provide improved response time and high bandwidth paths for storage applications. The computation nodes may include virtual or non-virtual machines. The interface may support various protocols depending on desired ease of use and response time. For example, a standardized protocol such as SCSI could be used for ease of use and data safety, or a direct data placement protocol could be used to help maximize response rate.

Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory. The at least one memory comprise instructions which are executed by the at least one processor and configure the processor to implement a read-ahead manager for adaptive read-ahead in log structured storage. The read-ahead manager determines a probability value P representing a probability to read into cache a temporal environment for a front-end read for a given segment in user space in a log structured storage. Responsive to performing a front-end read of a record of the given segment in the log structured storage, the read-ahead manager performs pre-fetch of the temporal environment for the record with probability P.

Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.

Abstract: In a system and a method for control and/or analytics of an industrial process and especially a system and a method for the prioritization of the data transmission of process data from plant-side automation and processing units to remote processing units external to the plant, the system has an the plant side at least one automation or processing unit, which carries out first process variable computations and acts on the process. On the side external to the plant, the system has a remote processing unit that carries out a number of second process variable computations and that receives local data from the at least one automation or processor unit via a data connection and at least one data collector unit. The data collector unit prioritizes the data transfer via the data connection between the at least one automation or processor unit and the processing unit external to the plant.

Abstract: Embodiments of apparatuses, methods, and systems for independent tuning of multiple hardware prefetchers are described. In an embodiment, an apparatus includes a processor core, a cache memory, a hardware prefetcher, and a prefetch tuner. The hardware prefetcher is to prefetch data for the processor core from a system memory to the cache memory. The prefetch tuner is to adjust a prefetch rate of the hardware prefetcher based on a fraction of late prefetches. The prefetch tuner includes a late prefetch counter to count a number of late prefetches for the hardware prefetcher, a prefetch counter to count a number of prefetches for the hardware prefetcher, and a late prefetch calculator to calculate the fraction of late prefetches based on the number of late prefetches and the number of prefetches.

Abstract: A system, method, and computer-readable medium are disclosed for performing a multi-level application cache operation, comprising: defining a first application level cache; defining an intermediate second application level cache; communicating with a last memory level, the last memory level including a source for a plurality of data objects; and, accessing a data object via the first application level cache when the data object is present and valid within the first application level cache.

Abstract: A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.

Abstract: Systems, methods, and articles of manufacture comprising processor-readable storage media are provided to implement read-ahead memory operations using learned memory access patterns for memory management systems. For example, a method for managing memory includes receiving a request from requestor (e.g., an active process) to perform a memory access operation, which includes a requested memory address. A determination is made as to whether a data block (e.g., page) associated with the requested memory address resides in a cache memory.

Abstract: An arithmetic processing device includes a core, and a first control circuit that controls a memory request issued by the processing core. The first control circuit includes a miss access control unit with input entries that assigns an input entry to the memory request to control a process of the memory request, and a control pipeline circuit that performs a cache hit determination and issues a memory request to the miss access control unit in a case of cache miss. The control pipeline circuit includes a speculative request control unit that issues a speculative memory request to the miss access control unit before the cache hit determination is performed, cancels the issued speculative memory request in a case of cache hit, and more suppresses issuing the speculative memory request when the number of input entries assigned to the canceled speculative memory request increases.

Abstract: Techniques and systems are provided for tracking commands. Such methods and systems can include receiving a data access request in a controller coupled to (a) a non-volatile memory configured to store a set of physical data pages, and (b) a volatile memory configured to store a plurality of physical data page addresses, wherein each physical data page address corresponding to a physical data page in the set of physical data pages, and each physical data page address is accessed via a corresponding logical address in a set of logical addresses; accessing, by the controller based on the received data access request, a bitmap stored on the volatile memory, the bitmap including a set of bits, each bit configured to indicate a validity state of a different plurality of logical addresses in a set of logical addresses; and determining, via the controller, an invalid state of at least one of a selected (a) logical address, or (b) plurality of logical addresses, based on a bit in the bitmap.

Abstract: In one embodiment, a processor includes: a first cache controller to control a first cache memory. This cache controller may include a replacement circuit to: associate a first priority indicator with a first cache line based on storage of demand data in the first cache line and first learning information associated with a set of demand-based categories of cache lines; and associate a second priority indicator with a second cache line based on storage of prefetch data in the second cache line and second learning information associated with a set of prefetch-based categories of cache lines. Other embodiments are described and claimed.

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.

Abstract: A method includes obtaining a trigger instruction responsive to execution of an application reaching a specific location and state, wherein the trigger instruction includes an index into a preload engine offset table and a base address, accessing the preload engine offset table based on the index and base address to determine an offset specific to the application location and state, and prefetching data into cache as a function of the base address and offset.

Abstract: Disclosed herein are methods, systems, and processes track access patterns of inodes, and to issue read-ahead instructions to pre-fetch inodes into memory. An inode is accessed and a directory of the inode is determined. Also determined is whether an entry for the directory exists in a global inode list. If the entry exists in the global inode list, whether a file structure of the directory is sequential or non-sequential is determined. If the entry does not exist in the global inode list, a new entry for the directory is added in the global inode list.

Abstract: A processor includes a first memory interface to be coupled to a plurality of dual in-line memory module (DIMM) sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the DIMMs disposed in the plurality of DIMM sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power DIMM disposed in one of the DIMM sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power DIMM as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.

Abstract: This invention involves a particular cache hazard. It is possible that an instruction request that is a miss in the cache occurs while the cache system is servicing a pending prefetch for the same instructions. In the prior art, this hazard is detected by comparing request addresses for all entries in a scoreboard. The program memory controller stores the allocated way in the scoreboard. The program memory controller compares the allocated way of the demand request to the allocated way of all the scoreboard entries. The cache hazard only occurs when the allocated ways match. Following way compare, the demand request address is compared to the request addresses of only those scoreboard entries having matching ways. Other address comparators are not powered during this time. This serves to reduce the electrical power required in detecting this cache hazard.

Abstract: In an embodiment, a processor may implement an access map-pattern match (AMPM)-based prefetch circuit for a multi-level cache system. The access patterns that are matched to the access maps may include prefetches for different cache levels. Centralizing the generation of prefetches into one prefetch circuit may provide better observability and controllability of prefetching at various levels of the cache hierarchy, in an embodiment. Prefetches at different levels may be controlled individually based on the accuracy of those prefetches, in an embodiment. Additionally, in an embodiment, access patterns that are longer that a given threshold may have the granularity of the prefetches change so that more data is prefetched and the prefetches occur farther in advance, in some embodiments.

Abstract: In at least some embodiments, a cache memory of a data processing system receives a speculative memory access request including a target address of data speculatively requested for a processor core. In response to receipt of the speculative memory access request, transactional memory logic determines whether or not the target address of the speculative memory access request hits a store footprint of a memory transaction. In response to determining that the target address of the speculative memory access request hits a store footprint of a memory transaction, the transactional memory logic causes the cache memory to reject servicing the speculative memory access request.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the prefetch request is greater than priority of the transaction, by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: Techniques are disclosed relating to set-associative caches in processors. In one embodiment, an integrated circuit is disclosed that includes a set-associative cache configured to receive a request for a data block stored in one of a plurality of ways within the cache, the request specifying an address, a portion of which is a tag value. In such an embodiment, the integrated circuit includes a way prediction circuit configured to predict, based on the tag value, a way in which the requested data block is stored. The integrated circuit further includes a tag array circuit configured to perform a comparison of a portion of the tag value with a set of previously stored tag portions corresponding to the plurality of ways. The tag array circuit is further configured to determine whether the request hits in the cache based on the predicted way and an output of the comparison.

Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells, and a memory controller. The semiconductor memory device includes first, second, and third caches for storing data before the data are written into the memory cells. The memory controller is configured to issue commands to the semiconductor memory device, the commands including a first command issued with write data to store the write data in the first cache and a second command issued with write data to store the write data in the first cache and then transfer the write data in the first cache to one of the second and third caches.

Abstract: A cache device of an embodiment includes a tag/data memory. The tag/data memory includes a storage area capable of storing a plurality of pieces of tag data and a plurality of pieces of compressed cache data corresponding to the plurality of pieces of tag data; and each of the pieces of tag data includes a flag indicating whether the piece of tag data is a piece of tag data read last or not and a compression information field C indicating whether each of the pieces of cache data is compressed or not.

Abstract: A system and method for determining a sequential access efficiency for a database table includes determining a number of data block changes that occur during a sequential access of a plurality of rows in a database table. The sequential access efficiency is determined based on the determined number of data block changes.

Abstract: A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC nodes has respective memory resources integral therewith. Each one of the SoC nodes has information computing resources accessible by one or more data processing systems. Each one of the SoC nodes configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the SoC nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the SoC nodes thereto based on a workload thereof.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include storing one or more data volumes to a small computer system interface storage device, and receiving a request to map a given data volume to a host computer. One or more attributes of the given data volume are identified, and using the identified one or more attributes, a unique logical unit number (LUN) for the given data volume is generated. The given data volume is mapped to the host computer via the unique LUN. In some embodiments, the generated LUN includes one of the one or more attributes. In additional embodiments, the generated LUN includes a result of a hash function using the one or more attributes. In storage virtualization environments, the data volume may include secondary logical units, and mapping the given data volume to the host may include binding the SLU to the host.

Abstract: A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode.