Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: A computer-implemented method for maintaining a storage volume in a virtual tape system includes writing one or more logical volumes associated with a first category and one or more logical volumes associated with a second category to a primary storage in a virtual tape system. The computer-implemented method further includes performing a first automatic removal process in order to free up space on the primary storage, wherein the first automatic removal process removes logical volumes associated with the first category in priority to logical volumes associated with the second category. The computer-implemented method further includes performing a second automatic removal process, wherein the second automatic removal process dynamically alters the priority of the first automatic removal process such that one or more virtual volumes associated with the second category are removed in priority to one or more virtual volumes associated with the first category.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by receiving a dispersed storage network (DSN) access request and determining an endpoint address from which the DSN access request is originating. The method continues by determining a first geographic location based on the endpoint address. The method continues by determining a target bucket and object the DSN access request is associated with and determining a second geographic location of the target bucket. For differing first and second geographic locations, the method continues by creating a mirror bucket in the first geographic location and configuring an access layer to route future DSN access requests to the mirror bucket based on TTL needs.

Abstract: Utilizing physical cache address comparison for maintaining coherency. Operations are performed on data in lines of a cache of the computing system and virtual addresses are loaded into a cache controller. The virtual addresses correspond with lines associated with performing the operations. A physical address of a line is determined in response to having performed a first cache directory lookup of the line. The physical address from the first operation is compared with other physical addresses associated with other operations to determine whether the other operations utilize the same physical address as the first operation. In response to matching physical locations, determinations are made as to whether a conflict exists in the data at the physical addresses that match. Thus, the coherency maintenance is free from looking up virtual addresses to determine whether the line of the cache includes incoherent data.

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Abstract: Disclosed is a technique in which an application can record changes it makes to physical memory. In the technique, the application specifies a virtual memory region which is converted to a plurality of cache lines, each of which is monitored for changes by a device connected to a coherence interconnect coupled to the processor caches. The application sends a start signal to start the logging process and an end signal to stop the process. During the logging process, when a change occurs to one of the cache lines, an undo entry corresponding to the change is created and entered into a transaction log residing in persistent memory. The transaction log containing the undo entries makes the set of changes recorded in the transaction log atomic. If a failure occurs, the recorded changes can be undone as if they never occurred.

Abstract: A method to determine if a value is present in a storage hierarchy which comprises initialization of a range of the collection that resides on a first storage device that is in a tier slower than a fastest tier of a storage hierarchy; partitioning the range into disjointed range partitions such that a first subset of the range partitions is designated as cached and a second subset is designated as uncached; partitioning the collection into a subset of uncached data and cached data; copying, the subset of the collection which lies in the one or more cached range partitions into a cache, wherein the cache resides on a second storage device that is in a tier faster than the first storage device; determination of a target range partition to which the value belongs, and determining if the target range partition is cached or uncached.

Abstract: A state of a first architectural register in a processing system is changed from a first state to a second state that indicates that the first architectural register is to be monitored during speculative execution. A second architectural register in the processing system is associated with a third state in response to the first architectural register being a source register for a memory load instruction that loads data from a memory into the second architectural register during speculative execution. Use of data in the second architectural register is constrained during speculative operations while the second architectural register is in the third state. In some cases, a “set taint” instruction is executed to change the state of the first architectural register from the first state to the second state.

Abstract: In a data write control method, a write control apparatus currently runs a program in a write-back mode in which data are written to a volatile memory. When the apparatus detects that a quantity of dirty blocks in the volatile memory has reached a threshold, it predicts a first amount of execution progress of the program within a prediction time period under an assumption of the apparatus being in a write-through mode in which data are written to the volatile memory and a non-volatile memory. The apparatus also predicts a second amount of execution progress of the program within the prediction time period under an assumption of the apparatus being in the write-back mode. When the predicted first amount of execution progress exceeds the predicted second amount of execution progress, the apparatus switches from the write-back mode to the write-through mode.

Abstract: An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

Abstract: Processing prefetch memory operations and transactions. A local processor receives a write prefetch request from a remote processor. Prior to execution of a write prefetch request received from a remote processor, determining whether a priority of the write prefetch request is greater than a priority of a pending transaction of a local processor. The write prefetch request is executed in response to a determination that the priority of the write prefetch request is greater than the priority of a pending transaction. Prefetch data produced by execution of the write prefetch request is provided to the remote processor.

Abstract: Systems, methods, and apparatuses relating to low latency communications in a configurable spatial accelerator are described.

Abstract: One embodiment of the present invention provides a system for facilitating a distributed storage system. The system receives, by a first client-serving machine, a first request to write data. The system writes the data to a first persistent cache associated with the first client-serving machine, wherein a persistent cache includes non-volatile memory. The system records, in an entry in a global data structure, a status for the data prior to completing a write operation for the data in a storage server, wherein the status indicates that the data has been stored in the first persistent cache but has not yet been stored in the storage server.

Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.

Abstract: Destaging data from a first tier data store to a second tier data store can be performed periodically and concurrently while processing user I/O operations. Each round of destaging can be delayed by certain amount (sleep time). A throttling factor can be used to compute the sleep time as a fraction of a base sleep time. The throttling factor can vary based on the usage level of first tier data store, and can be used to determine the destage frequency.

Abstract: A database system may implement database system recovery using non-volatile system memory. An update to a data page of a database may be received. A version of the data page may be obtained in system memory. A new version of the data page may be determined according to the received update. The new version of the data page may be maintained in a non-volatile portion of system memory irrespective of a failure of the database. In at least some embodiments, the update may be performed without generating recovery log records indicating the update. Upon recovery from a database failure, data pages maintained in non-volatile system memory may be made available to service access requests.

Abstract: A data processing system for processing data comprising: ownership circuitry to enforce ownership rights of memory regions, a given more privileged state memory region having a given owning process specified from among a plurality of processes, said given owning process having exclusive rights to control access to said given memory region; and context switching circuitry responsive to receipt of an interrupt to trigger a context switch from a first active process to a second active process whereby one or more items of state for use in restarting said first process is saved to one or more context data memory regions owned by said first process and one or more items of state accessible to said second process and dependent upon processing by said first process is overwritten prior to commencing execution of said second process.

Abstract: A method, computer program product, and computer system for determining, by a computing device, a number of dirty pages capable of being generated per process on a backing device. It may be determined whether the number of dirty pages capable of being generated per process on the backing device exceeds a threshold set point of actual dirty pages currently generated per process on the backing device. A variable amount of time to sleep may be determined. Sleep may be executed for the variable amount of time, wherein generation of additional dirty pages is paused.

Abstract: In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node.

Abstract: In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

Abstract: In one embodiment, a load-balancer in a computer network receives an end-device request for a particular network-based resource, and determines a popularity of the particular network-based resource being requested in comparison to other network-based resources requested by end devices in the computer network. In response to the particular network-based resource being popularly requested, the load-balancer forwards the end-device request into a Fog network to cause the Fog network to respond to the end-device request with particular network-based resource. Conversely, in response to the particular network-based resource not being popularly requested, the load-balancer forwards the end-device request into a Cloud network to cause the Cloud network to respond to the end-device request with particular network-based resource.

Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.

Abstract: Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.

Abstract: A computer implemented method, system, and computer program product comprising intercepting an interaction with a data storage capability at the abstraction layer enabled to intercept data interactions for different types of data storage capabilities; wherein the interaction changes data on the data storage capability; sending a copy of the interaction to a replication data storage capability; and sending the interaction to the data storage capability.

Abstract: The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.

Abstract: In one embodiment, a task control block (TCB) for allocating cache storage such as cache segments in a multi-track cache write operation may be enqueued in a wait queue for a relatively long wait period, the first time the task control block is used, and may be re-enqueued on the wait queue for a relatively short wait period, each time the task control block is used for allocating cache segments for subsequent cache writes of the remaining tracks of the multi-track cache write operation. As a result, time-out suspensions caused by throttling of host input-output operations to facilitate cache draining, may be reduced or eliminated. It is appreciated that wait classification of task control blocks in accordance with the present description may be applied to applications other than draining a cache. Other features and aspects may be realized, depending upon the particular application.

Abstract: A hypervisor deduplcation system includes a memory, a processor in communication with the memory, and a hypervisor executing on the processor. The hypervisor is configured to scan a first page, detect that the first page is an unchanged page, check a first free page hint, and insert the unchanged page into a tree. Responsive to inserting the unchanged page into the tree, the hypervisor compares the unchanged page to other pages in the tree and determine a status of the unchanged page as matching one of the other pages or mismatching the other pages in the tree. Responsive to determining the status of the page as matching another page, the hypervisor deduplicates the unchanged page. Additionally, the hypervisor is configured to scan a second page of the memory, check a second free page hint, deduplicate the second page if the free page hint indicates the page is unused.

Abstract: A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.

Abstract: Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

Abstract: A system that includes circuitry to access memories in both coherent and non-coherent domains is disclosed. The circuitry may receive a command to access a memory included in the coherent domain and generate one or more commands to access a memory in the non-coherent domain dependent upon the received command. The circuitry may send the generated one or more commands to the memory in the non-coherent domain via communication bus.

Abstract: A computer system includes a main memory, a lower class memory, and a secondary storage medium and executes an operating system, an in-memory computing program, and a prefetch optimizer program. The in-memory computing program writes processing target data including a plurality of data objects stored in the secondary storage medium into a plurality of continuous areas on a virtual memory space and executes a process while accessing the continuous area. When detecting that the operating system executes a class-in process triggered upon a page fault for a predetermined virtual page, the prefetch optimizer program acquires information of the continuous area from the in-memory computing program and directs the operating system to execute a class-in process for virtual pages included in the predetermined continuous area including the predetermined virtual page.

Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.

Abstract: A translation lookaside buffer (TLB) index valid bit is set in a first line of a virtually indexed, virtually tagged (VIVT) cache. The first line of the VIVT cache is associated with a first TLB entry which stores a virtual address to physical address translation for the first cache line. The TLB index valid bit of the first line is cleared upon determining that the translation is no longer stored in the first TLB entry. An indication of a received invalidation instruction is stored. When a context synchronization instruction is received, the first line of the VIVT cache is cleared based on the TLB index valid bit being cleared and the stored indication of the invalidate instruction.

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

Abstract: Techniques for providing file system functionality over a PCIe interface are disclosed. In some embodiments, the techniques may be realized as a method for providing file system functionality over a PCIe interface including receiving from a host device a storage command, specially devised for such a standard protocol, at a PCIe-based device controller, parsing, using at least one computer processor of the PCIe-based device controller, the storage command, traversing, using PCIe-based device controller, one or more portions of file system metadata of an associated storage media device, wherein the PCIe-based device controller is configured to traverse the one or more portions of file system metadata based on the parsed storage command independent of any subsequent communication with the host device, and returning data to the host device.

Abstract: Systems, methods, and articles of manufacture comprising processor-readable storage media are provided for implementing an accelerated data storage synchronization to protect data in a storage system. For example, a first server node accesses a data block from a protected storage system in response to a request from an application executing on the first server node. A modified data block is written to a write-back cache of the first server node. A synchronization operation is performed in response to a request by the application, which includes sending a copy of the modified data block in the write-back cache to a second server node to temporarily store the copy of the modified data block in a storage media of the second server node, and informing the application that the synchronization operation is deemed complete after the copy of the modified data block is stored in the storage media of the second server node.

Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.

Abstract: Systems and methods for reducing input/output operations in a computing system that uses a cache. Input/output operations associated with cache index lookups are reduced by tracking the location of the requested data such that the data can be invalidated without having to access the cache index. Input/output operations can be reduced by invalidating the entry in the cache index when reading the corresponding data.

Abstract: Methods and apparatuses for managing data using an in-memory database are provided. One of the methods comprises, determining whether a memory utilization rate is equal to or greater than a threshold value, reducing the value of replication factor of data stored in the memory, when the memory utilization rate is equal to or greater than the threshold value as a result of the determination, and deleting at least one data duplicated with the data, in accordance with the reducing the value of replication factor.

Abstract: A data storage device includes a data storage medium having a plurality of data blocks. A cache includes a plurality of cache blocks. Each cache block includes a corresponding cache block address. A metadata table includes a plurality of table entries for the data blocks, respectively. Each of the table entries is configured to store the cache block address of one of the cache blocks in which data of a corresponding one of the data blocks is written. A bitmap is configured to store statuses of all of the cache blocks, respectively.

Abstract: A snapshot analysis system analyzes a plurality of data snapshots taken in connection with data stored on a block device allocated by a data storage system. The snapshot analysis system may include an ingestor capable of initially detecting new snapshots and adding a root node for the snapshots. The system may include a block device analyzer that analyzes each snapshot to determine its contents, the relationship within data structures extant within the snapshot, and the snapshot's relationship to other snapshots and/or that of other block devices. The system may also include a clustering analyzer capable of determining whether snapshots are associated with multipart block devices, such as LVM or MD RAID devices. The system may further include a block device emulator that exposes data associated with a given snapshot as an addressable block device without necessitating retrieval or exposure of the full block device to which the snapshot is associated.

Abstract: A cache device has a data memory capable of storing a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form, and a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including uncompressed data writing state information, an absence flag, and a compression information field. In case of modifying only part of a cache line, i.e., a partial write, a request converter converts a write request into a read request, and a read-out piece of data is decompressed and written in a write status buffer. Data may be written from the write status buffer to the data memory without being compressed, which eliminates a need for decompression and compression for every writing or modifying operation of a piece of partial data, thereby reducing latency and power consumption.

Abstract: A datum to be preloaded includes the acquisition of a, so-called “model”, statistical distribution of the deltas of a model access sequence, the construction of a, so-called “observed”, statistical distribution of the deltas of an observed access sequence, the identification in the observed statistical distribution, by comparing it with the model statistical distribution, of the most deficient class, that is to say of the class for which the difference NoDSM?NoDSO is maximal, where NoDSM and NoDSO are the numbers of occurrences of this class that are deduced, respectively, from the model statistical distribution and from the observed statistical distribution, the provision as prediction of the datum to be preloaded into the cache memory, of at least one predicted address where the datum to be preloaded is contained, this predicted address being constructed on the basis of the most deficient class identified.

Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.

Abstract: A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; a cache storage circuit coupled to send and received packets to and from the packet processing circuit; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit; and wherein the packet processing circuit is configured to control cache read requests, cache write requests and cache data eviction.

Abstract: A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache.

Abstract: In addition to caching I/O operations at a host, at least some data management can migrate to the host. With host side caching, data sharing or deduplication can be implemented with the cached writes before those writes are supplied to front end storage elements. When a host cache flush to distributed storage trigger is detected, the host deduplicates the cached writes. The host aggregates data based on the deduplication into a “change set file” (i.e., a file that includes the aggregation of unique data from the cached writes). The host supplies the change set file to the distributed storage system. The host then sends commands to the distributed storage system. Each of the commands identifies a part of the change set file to be used for a target of the cached writes.

Abstract: Various systems and methods to achieve load balancing among a plurality of compute elements accessing a shared memory pool. The shared memory pool is configured to store and serve a plurality of data sets associated with a task, a first data interface's internal registry is configured to keep track of which data sets have been extracted from the shared memory pool and served to the compute elements, the first data interface is configured to extract from the shared memory pool and serve to the compute elements data sets which have not yet been extracted and served, the rate at which data sets are extracted and served to each particular compute element is proportional to the rate at which that compute element requests data sets, and the system may continues to extract, serve, and process data sets until all of the data sets associated with the task have been processed once.