Abstract: According to a method of cache management in a data storage system including a write cache and bulk storage media, a storage controller of the data storage system caches, in the write cache, write data of write input/output operations (IOPs) received at the storage controller. In response to a first performance-related metric for the data storage system satisfying a first threshold, the storage controller decreases a percentage of write IOPs for which write data is cached in the write cache of the data storage system and increases a percentage of write IOPs for which write data is stored directly in the bulk storage media in lieu of the write cache. In response to a second performance-related metric for the data storage system satisfying a second threshold, the storage controller increases the percentage of write IOPs for which write data is cached in the write cache of the data storage system.

Abstract: A tape recording device, method, and computer program product are provided for performing operations of position movement, reading, and writing on a tape medium, and receiving a series of commands from an upper-layer device. The tape recording device includes a buffer for temporarily storing data related to the reading and an append write, a tape for recording the data stored in the buffer, a reading and writing head for reading data from the tape into the buffer and writing the data onto the tape, control means for reading data from a designated position of the tape and storing the data in the buffer, and for writing the data stored in the buffer onto the tape from a written data end position in response to an append write command, and a non-volatile memory for storing data stored in the buffer in response to an append write command.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Embodiments include a local cache management system that is configured to be coupled to a local cache and that includes an index engine configured to store fingerprints of message segments stored in the local cache and a redundancy management engine coupled to the index engine. The redundancy management engine includes an adaptive emitter configured to receive a message segment to be transmitted to a remote device, determine expected latency costs of a plurality of transmission algorithms, and select a transmission algorithm, such as by selecting the lowest expected latency cost. The adaptive emitter is also configured to determine whether the message segment is stored within a remote cache management system associated with the remote device, and transmit the message segment through a network to the remote cache management system using the selected transmission algorithm upon a determination that the message segment is not stored within the remote cache management system.

Abstract: An embodiment generally relates to a method of updating clients from a server. The method includes maintaining a master copy of a software on a server and capturing changes to the master copy of the software on an update disk image, where the changes are contained in at least one chunk. The method also includes merging the update disk image with one of two client disk images of the client copy of the software.

Abstract: A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.

Abstract: A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (WB-E) memory space for an application running on the processing unit. The memory management system maps the WB-E memory space to the persistent memory. The application creates WB-E data by executing an instruction to store data to an address in the WB-E memory space. The WB-E data is automatically stored in a cache associated with the processing unit in response to creation of the WB-E data by the application. In response to execution of a commit instruction by the application after the application has created WB-E data for multiple memory addresses, the memory management system automatically ensures that all of the WB-E data for the application has been saved to the persistent memory domain. Other embodiments are described and claimed.

Abstract: According to one aspect of the present disclosure, a method and technique for variable cache line size management is disclosed. The method includes: determining whether an eviction of a cache line from an upper level sectored cache to an unsectored lower level cache is to be performed, wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache; responsive to determining that an eviction is to be performed, identifying referenced sub-sectors of the cache line to be evicted; invalidating unreferenced sub-sectors of the cache line to be evicted; and storing the referenced sub-sectors in the lower level cache.

Abstract: The present disclosure is directed to a method for managing a cache based on a charge of a power source. The method includes the step of determining a charge of the power source at a first time instance. The method also includes the step of designating for write back cache an amount of data in the cache which can be offloaded from the cache based on the charge of the power source at the first time instance. The method also includes the step of designating as write through cache an amount of data remaining in the cache which was not designated as write back cache.

Abstract: A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory.

Abstract: According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.

Abstract: Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Abstract: A technique for scheduling cache cleaning operations maintains a clean distance between a set of least-recently-used (LRU) clean lines and the LRU dirty (modified) line for each congruence class in the cache. The technique is generally employed at a victim cache at the highest-order level of the cache memory hierarchy, so that write-backs to system memory are scheduled to avoid having to generate a write-back in response to a cache miss in the next lower-order level of the cache memory hierarchy. The clean distance can be determined by counting all of the LRU clean lines in each congruence class that have a reference count that is less than or equal to the reference count of the LRU dirty line.

Abstract: An invention is provided for recovering from an unexpected shutdown in a write-back caching environment. The invention includes storing a logical block address (LBA) mapping table on a caching device. The LBA mapping table maps logical block addresses of a target storage device to logical block addresses of the caching device. In addition, a LBA mapping table change log is maintained on the caching device. The LBA mapping table change log includes changes to the LBA mapping table since the LBA mapping table was last written to the caching device. During startup after an unexpected shutdown, the unexpected shutdown is detected using a header stored on a caching device. Among other data, the header includes an indicia indicating whether or not a clean shutdown occurred. When the unexpected shutdown is detected, a recovered LBA mapping table is generated based on the LBA mapping table, which is stored on the caching device, and the LBA mapping table change log.

Abstract: A technique for scheduling cache cleaning operations maintains a clean distance between a set of least-recently-used (LRU) clean lines and the LRU dirty (modified) line for each congruence class in the cache. The technique is generally employed at a victim cache at the highest-order level of the cache memory hierarchy, so that write-backs to system memory are scheduled to avoid having to generate a write-back in response to a cache miss in the next lower-order level of the cache memory hierarchy. The clean distance can be determined by counting all of the LRU clean lines in each congruence class that have a reference count that is less than or equal to the reference count of the LRU dirty line.

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Abstract: Enhancing management of controllers in a RAID system when a post-write-cache of a is disabled, by supplying a stripe buffer that stores sequential write requests—and before such requests are actually written in to the physical disc drives. The stripe buffer can temporarily store data, until the data level reaches the stripe buffer size. Thereafter, contents of the stripe buffer can be flushed onto disc.

Abstract: A method begins by a dispersed storage network (DSN) access module encoding a data segment to produce slices and sending temporary write requests to DSN storage modules, wherein the temporary write requests includes slices. In response to one of the temporary write requests, the method continues with a DSN storage module temporarily storing a slice to produce a temporarily stored slice and sending an indication of temporary storage of the slice. When a write threshold number of indications of temporary storage has been received by the DSN access module, the method continues with the DSN access module sending permanent write requests to DSN storage modules. In response to one of the permanent write requests, the method continues with the DSN storage module storing the temporarily stored slice in permanent memory and sending an indication of permanent storage of the slice.

Abstract: A computer system is provided including a central processing unit having an internal cache, a memory controller is coupled to the central processing unit, and a closely coupled peripheral is coupled to the central processing unit. A coherent interconnection may exist between the internal cache and both the memory controller and the closely coupled peripheral, wherein the coherent interconnection is a bus.

Abstract: Techniques for replicating a write-back cache are provided. In one embodiment, a first computer system can receive a write request from a virtual machine (VM) that includes data to be written to a shared storage device. The first computer system can further save the data in a local cache device and transmit, via a network interface controller (NIC), a data packet including the data to a second computer system. Upon determining that the data packet has been transmitted via the NIC, the first computer system can communicate an acknowledgment to the VM indicating that the write request has been successfully processed.

Abstract: Various systems and methods for performing write-back caching in a cluster. For example, one method can involve a first node detecting that no failover nodes are available. A determination is made whether the first node should use write-back caching or not. If the first node is to continue using write-back caching, a first local cache identifier and a global cache identifier are both updated.

Abstract: This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.

Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.

Abstract: Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.

Abstract: A cache controller receives a reference request from a CPU executing a program in which information indicative of a reference request specifying in shared memory, an area not having an update request and information indicative of a snoop reference request are distinguished from one another. When the reference request specifying an area not having the update request is received, the cache controller acquires from the shared memory and without performing a snoop process, information stored in the specified area. The cache controller stores the information acquired from the shared memory to the cache memory of the CPU executing the program.

Abstract: A processor includes: a primary cache memory; an instruction control unit that issues a store request to the primary cache memory; a pipeline processing unit that, upon receiving the store request, writes data to the primary cache memory; a buffer unit that obtains an address output to the primary cache memory from the pipeline processing unit during an output period of the store request regarding certain data to hold the obtained address in an entry, and when the output period ends, issues a write-back request for writing the data indicated by the address held in the entry to a memory; and a secondary cache memory that, upon receiving the write-back request from the buffer unit, writes the data of the primary cache memory to the memory, the certain data is quickly written back to the memory from the primary cache memory.

Abstract: An operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory configured to store the first data and third data, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first, second and third data, wherein when the setting unit sets the operation processing unit to the non-operating state and the third data is requested from another operation processing apparatus, which triggers cache miss in the cache memory, the control unit reads the requested data from the main memory and holds the requested data in the cache memory and sends the read data to another operation processing apparatus.

Abstract: An operation processing apparatus connected with another operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by another operation processing apparatus and acquired from another operation processing apparatus, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first data and the second data, wherein when the setting unit sets the operation processing unit to the operating state and the second data is evicted from the cache memory, the control unit sends to another operation processing apparatus the evicted data and a request which is a trigger for storing the evicted data in a cache memory in another operation processing apparatus.

Abstract: Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.

Abstract: Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed.

Abstract: A method includes monitoring a number of read access requests to an address for data stored on a backing store. The method also includes comparing the number of read access requests to a read access threshold. The read access threshold includes a threshold number of read access requests for the address. The method also includes caching data corresponding to a write access request to the address in response to determining that the number of read access requests satisfies the read access threshold.

Abstract: A cache control device includes: a tag storage section configured to manage, for each cache line of a cache memory, whether or not the cache line is valid, and whether or not a write-back instruction to a shared storage section is provided; and a tag control section configured not to invalidate a cache line for which the write-back instruction is already provided, and to invalidate a cache line for which the write-back instruction is not provided, when a predetermined instruction is provided.

Abstract: A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.

Abstract: A storage controller that includes a cache, receives a command from a host, wherein a set of criteria corresponding to read response times for executing the command have to be satisfied. A destage application that destages tracks based at least on recency of usage and spatial location of the tracks is executed, wherein a spatial ordering of the tracks is maintained in a data structure, and the destage application traverses the spatial ordering of the tracks. Tracks are destaged from at least inside or outside diameters of disks at periodic intervals, while traversing the spatial ordering of the tracks, wherein the set of criteria corresponding to the read response times for executing the command are satisfied.

Abstract: A storage controller that includes a cache, receives a command from a host, wherein a set of criteria corresponding to read response times for executing the command have to be satisfied. A destage application that destages tracks based at least on recency of usage and spatial location of the tracks is executed, wherein a spatial ordering of the tracks is maintained in a data structure, and the destage application traverses the spatial ordering of the tracks. Tracks are destaged from at least inside or outside diameters of disks at periodic intervals, while traversing the spatial ordering of the tracks, wherein the set of criteria corresponding to the read response times for executing the command are satisfied.

Abstract: A method and an apparatus for implementing multi-processor memory coherency are disclosed. The method includes: a Level-2 (L2) cache of a first cluster receives a control signal of the first cluster for reading first data; the L2 cache of the first cluster reads the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, where the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and the L2 cache of the first cluster provides the first data read to the first cluster for processing. The technical solution under the present invention implements memory coherency between clusters in the ARM Cortex-A9 architecture.

Abstract: Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.

Abstract: Provided are a method, system, and computer program product for processing read and write requests in a storage controller. A host adaptor in the storage controller receives a write request from a host system for a storage address in a storage device. The host adaptor sends write information indicating the storage address updated by the write request to a device adaptor in the storage controller. The host adaptor writes the write data to a cache in the storage controller. The device adaptor indicates the storage address indicated in the write information to a modified storage address list stored in the device adaptor, wherein the modified storage address list indicates modified data in the cache for storage addresses in the storage device.

Abstract: Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.

Abstract: A method of accelerating memory operations using virtualization information includes executing a hypervisor on hardware resources of a computing system. A plurality of domains are created under the control of the hypervisor. Each domain is allocated memory resources that include accessible memory space that is exclusively accessible by that domain. Each domain is allocated one or more processor resources. The hypervisor identifies domain layout information that includes a boundary of accessible memory space of each domain. The hypervisor provides the domain layout information to each processor resource. Each processor resource is configured to implement, on a per domain basis, a restricted coherency protocol based on the domain layout information. The restricted coherency protocol bypasses, relative to the domain, downstream caches when a cache line falls within the accessible memory space of that domain.

Abstract: A method for managing data, the method includes: providing a write-back cache unit coupled to at least one storage unit; receiving a request to write a new data version to a certain cache data allocation unit; determining, in response to a data storage policy, whether to overwrite a cached data version being cached in the certain cache data allocation unit or to perform a destage of the cached data version to a first storage unit before writing the new data version to the certain cache allocation unit; receiving a request to read a data version that corresponds to a certain point in time and scanning a first data structure representative of write operations and a second data structure representative of revert operations to determine a location of the requested data version.

Abstract: A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.

Abstract: A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure.

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

Abstract: A method for distributing IO load in a RAID storage system is disclosed. The RAID storage system may include a plurality of RAID volumes and a plurality of processors. The IO load distribution method may include determining whether the RAID storage system is operating in a write-through mode or a write-back mode; distributing the IO load to a particular processor selected among the plurality of processors when the RAID storage system is operating in the write-through mode, the particular processor being selected based on a number of available resources associated with the particular processor; and distributing the IO load among the plurality of processors when the RAID storage system is operating in the write-back mode, the distribution being determined based on: an index of a data stripe, and a number of processors in the plurality of processors.

Abstract: A save control section included in a storage apparatus continuously performs writeback by which a data group is read out from a plurality of storage sections of the storage apparatus and by which the data group is saved in a data group storage section of the storage apparatus, or staging by which a data group saved in the data group storage section is distributed and stored in the plurality of storage sections according to storage areas of the data group storage section which store a plurality of data groups. An output section of the storage apparatus outputs in block a data group including the data stored in each of the plurality of storage sections. The data group storage section has the storage areas for storing a data group.