Snooping Patents (Class 711/146)
  • Patent number: 11561901
    Abstract: A data processing system includes a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. Based on receiving on a system fabric a cache injection request requesting injection of a data into a cache line identified by a target real address, the data is written into a cache in a first vertical cache hierarchy among the plurality of vertical cache hierarchies. Based on a value in a field of the cache injection request, a distribute field is set in a directory entry of the first vertical cache hierarchy. Upon eviction of the cache line the first vertical cache hierarchy, a determination is made whether the distribute field is set. Based on determining the distribute field is set, a lateral castout of the cache line from the first vertical cache hierarchy to a second vertical cache hierarchy is performed.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Bernard C. Drerup, Hugh Shen, Alexander Michael Taft, Luke Murray, Richard Nicholas
  • Patent number: 11556472
    Abstract: A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Alexander Michael Taft, Guy L. Guthrie, Bernard C. Drerup
  • Patent number: 11550485
    Abstract: Provided are systems and methods for paging data into main memory from checkpoint data stored on disk. In one example, the method may include one or more of receiving a request for a database record in main memory, determining whether the database record has been previously stored in the main memory, in response to determining that the database record has been previously stored in the main memory, identifying a slice where the database record was stored from among a plurality of slices included in the main memory, and paging content of the identified slice including a copy of the requested database record into the main memory from a snapshot captured of content included in the identified slice and previously stored on disk. Accordingly, documents can be paged into main memory on-demand from snapshots of slice content rather than paging an entire partition of content.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 10, 2023
    Assignee: SAP SE
    Inventors: Christian Bensberg, Steffen Geissinger
  • Patent number: 11550455
    Abstract: Embodiments of the present invention provide a system for querying a graph based on applying filters to a visual representation of the graph. The system allows complicated graph query operations to be performed with ease visually. During operation, the system obtains data indicating vertices and edges of a graph. The system displays a visual representation of the graph for a user. The system receives, from the user, a command defining a local graph filter comprising a region in the visual representation. The system then filters a representation of the graph, and stores the filtered representation.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 10, 2023
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ryan A. Rossi, Rong Zhou
  • Patent number: 11544192
    Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 3, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Hayakawa, Toshiyuki Kaya, Shinichi Shibahara
  • Patent number: 11544193
    Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: January 3, 2023
    Assignee: Apple Inc.
    Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
  • Patent number: 11521953
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 6, 2022
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
  • Patent number: 11513964
    Abstract: A data-relationship-based FAST cache system includes a storage controller that is coupled to first storage device(s) and second storage device(s). The storage controller identifies a relationship between first data stored in the first storage device(s) and second data stored in the first storage device (s), with the relationship based on a difference between a first number of accesses of the first data associated with a first time period and a second number of accesses of the second data associated with the first time period being within an access difference threshold range. Subsequent to identifying the relationship, the storage controller determines that the first data has been accessed in the first storage device(s) a number of times within a second time period that exceeds a FAST cache threshold and, in response, moves both the first data and the second data to the second storage device(s) based on the relationship.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: November 29, 2022
    Assignee: Dell Products L.P.
    Inventors: Chi Chen, Ruiyang Zhang, Weilan Pu
  • Patent number: 11513962
    Abstract: An apparatus comprises a write buffer to buffer store requests issued by the processing circuitry, prior to the store data being written to at least one cache. Draining circuitry detects a draining trigger event having potential to cause loss of state stored in the at least one cache. In response to the draining trigger event, the draining circuitry performs a draining operation to identify whether the write buffer buffers any committed store requests requiring persistence, and when the write buffer buffers at least one committed store request requiring persistence, to cause the store data associated with the at least one committed store request to be written to persistent memory. This helps to eliminate barrier instructions from software, simplifying persistent programming and improving performance.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: November 29, 2022
    Assignee: Arm Limited
    Inventors: Wei Wang, Prakash S. Ramrakhyani, Gustavo Federico Petri
  • Patent number: 11500741
    Abstract: A data write method and a corresponding storage system are provided. The storage system includes a first controller and a second controller, and the method includes: after receiving a first data write request, determining, by the second controller, whether a locally stored first time tag is in an expired state; when determining that the locally stored first time tag is in the expired state, reading, by the second controller, the first time tag from the first controller; and storing, by the second controller, a correspondence between the first time tag and the first data write request. According to the present invention, time consistency is ensured when a snapshot operation is performed on a logical storage area, and performance fluctuation is reduced.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: November 15, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Wendi Weng
  • Patent number: 11494303
    Abstract: In a method of flushing cached data in a data storage system, instances of a working-set structure (WSS) are used over a succession of operating periods to organize cached data for storing to the persistent storage. In each operating period, leaf structures of the WSS are associated with respective address ranges of a specified size. Between operating periods, a structure-tuning operation is performed to adjust the specified size and thereby dynamically adjust a PD-to-leaf ratio of the WSS, including (1) comparing a last-period PD-to-leaf ratio to a predetermined ratio range, (2) when the ratio is below the predetermined ratio range, increasing the specified size for use in a next operating period, and (3) when ratio is above the predetermined ratio range, then decreasing the specified size for use in the next operating period.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: November 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Geng Han, Yousheng Liu
  • Patent number: 11481331
    Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 25, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish Kotra, John Kalamatianos
  • Patent number: 11468033
    Abstract: A method and apparatus for performing storage and retrieval in an information storage system cache is disclosed that uses the hashing technique with the open-addressing method for collision resolution. Insertion, retrieval, and deletion operations are limited to a predetermined number of probes, after which it may be assumed that the table does not contain the desired data. Moreover, when using linear probing, the technique facilitates maximum concurrent, multi-thread access to the table, thereby improving system throughput, since only a relatively small section is locked and made unavailable while a thread modifies that section, allowing other threads complete access to the remainder of the table.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 11, 2022
    Inventors: Richard Michael Nemes, Mikhail Lotvin, David Garrod
  • Patent number: 11461042
    Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: George Pax, Jonathan Scott Parry
  • Patent number: 11461024
    Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Jun-Seo Lee
  • Patent number: 11409656
    Abstract: A semiconductor device includes a core which includes a first cache and a second cache; and a third cache configured to connect to the core, wherein the core is configured to: hold a read instruction that is issued from the first cache to the second cache, hold a write-back instruction that is issued from the first cache to the second cache, process the read instruction and the write-back instruction, determine whether a target address of the read instruction is held by the first cache by using a cache tag that indicates a state of the first cache, and when data of the target address is held by the first cache, abort the read instruction until it is determined that data of the target address is not held by the first cache.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 9, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Hiroyuki Ishii
  • Patent number: 11366750
    Abstract: Techniques for caching may include: determining an update to a first data page of a first cache on a first node, wherein a second node includes a second cache and wherein the second cache includes a copy of the first data page; determining, in accordance with one or more criteria, whether to send the update from the first node to the second node; responsive to determining, in accordance with the one or more criteria, to send the update, sending the update from the first node to the second node; and responsive to determining not to send the update, sending an invalidate request from the first node to the second node, wherein the invalidate request instructs the second node to invalidate the copy of the first data page stored in the second cache of the second node.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: June 21, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Alex Soukhman, Uri Shabi, Bar David
  • Patent number: 11354242
    Abstract: Data units are stored in private caches in nodes of a multiprocessor system, each node containing at least one processor (CPU), at least one cache private to the node and at least one cache location buffer (CLB) private to the node. In each CLB location information values are stored, each location information value indicating a location associated with a respective data unit, wherein each location information value stored in a given CLB indicates the location to be either a location within the private cache disposed in the same node as the given CLB, to be a location in one of the other nodes, or to be a location in a main memory. Coherence of values of the data units is maintained using a cache coherence protocol. The location information values stored in the CLBs are updated by the cache coherence protocol in accordance with movements of their respective data units.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 7, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Erik Hagersten, Andreas Sembrant
  • Patent number: 11354256
    Abstract: The present invention discloses a multi-core interconnection bus, including a request transceiver module adapted to receive a data request from a processor core, and forward the data request to a snoop and caching module through a request execution module, where the data request includes a request address; the snoop and caching module adapted to look up cache data validity information of the request address, acquire data from a shared cache, and sequentially return the cache data validity information and the data acquired from the shared cache to the request execution module; and the request execution module adapted to determine, based on the cache data validity information, a target processor core whose local cache stores valid data, forward the data request to the target processor core, and receive returned data; and determine response data from the data returned by the target processor core and that returned by the snoop and caching module, and return, through the request transceiver module, the response d
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 7, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Xiaoyan Xiang, Taotao Zhu
  • Patent number: 11269774
    Abstract: Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Timothy David Anderson
  • Patent number: 11263720
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • Patent number: 11243883
    Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson, Kai Chirca
  • Patent number: 11226900
    Abstract: An approach for tracking data stored in caches uses a Bloom filter to reduce the number of addresses that need to be tracked by a coherence directory. When a requested address is determined to not be currently tracked by either the coherence directory or the Bloom filter, tracking of the address is initiated in the Bloom filter, but not in the coherence directory. Initiating tracking of the address in the Bloom filter includes setting hash bits in the Bloom filter so that subsequent requests for the address will “hit” the Bloom filter. When a requested address is determined to be tracked by the coherence directory, the Bloom filter is not used to track the address.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 18, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Weon Taek Na, Yasuko Eckert, Mark H. Oskin, Gabriel H. Loh, William Louie Walker, Michael Warren Boyer
  • Patent number: 11194579
    Abstract: A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: December 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Sung Shin, Sung-Ho Park, Chan-Kyung Kim, Yong-Sik Park, Sang-Hoon Shin
  • Patent number: 11182295
    Abstract: The disclosure provides for a reactive cache coherence protocol that has efficiencies over proactive approaches. Rather than proactively performing remediation when a data item is invalidated, a destination endpoint checks cache coherence upon receiving an indication of a cache hit, and based at least on detecting a lack of coherence, performs a reactive remediation process. For example, the incoherence may be fixed by replacing, as a cached data item, a data block indicated by the cache hit with a replacement data block that triggered the cache hit.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 23, 2021
    Assignee: VMware, Inc.
    Inventor: Oleg Zaydman
  • Patent number: 11169929
    Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Rupin Vakharwala, Amin Firoozshahian, Stephen Van Doren, Rajesh Sankaran, Mahesh Madhav, Omid Azizi, Andreas Kleen, Mahesh Maddury, Ashok Raj
  • Patent number: 11144209
    Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for managing an input/output (I/O). The method comprises, in response to receiving a first I/O request of a first type for a storage device, determining whether there exists at least one credit available to the first type of I/O requests. Each of the at least one credit indicates I/O processing capability reserved by the storage device for the first type of I/O requests. The method further comprises allocating a first credit to the first I/O request based on a result of the determining. The method further comprises performing, by using the first credit, an I/O operation requested by the first I/O request on the storage device. Moreover, the method further comprises, in response to completion of the I/O operation, recycling the first credit for use by a subsequent I/O request. Embodiments of the present disclosure can implement dynamic allocation of I/O processing capability for different types of I/Os.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: October 12, 2021
    Assignee: Dell Products L.P.
    Inventors: Lifeng Yang, Xinlei Xu, Liam Li, Ruiyong Jia, Yousheng Liu
  • Patent number: 11139270
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: October 5, 2021
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
  • Patent number: 11126429
    Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include a computation module that includes one or more bitwise processors and a combiner. The bitwise processors may be configured to perform bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results. The combiner may be configured to combine the one or more operation results into an output vector.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 21, 2021
    Assignee: Cambricon Technologies Corporation Limited
    Inventors: Tao Luo, Tian Zhi, Shaoli Liu, Tianshi Chen, Yunji Chen
  • Patent number: 11126354
    Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Inventors: Dongyan Jiang, Hongzhong Zheng
  • Patent number: 11106468
    Abstract: Methods and systems for maintaining validity of a memory model in a multiple core computer system are described. A first core prevents a store instruction from being performed by another core until a condition is met which enables reordered instructions to validly execute.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 31, 2021
    Assignee: ETA SCALE AB
    Inventors: Alberto Ros, Stefanos Kaxiras
  • Patent number: 11106584
    Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 31, 2021
    Assignee: Texas Instmments Incorporated
    Inventors: Abhijeet Ashok Chachad, David Matthew Thompson, Naveen Bhoria
  • Patent number: 11062391
    Abstract: Method and apparatus for interfacing middleware applications with a financial market snapshot feed. Financial market data are retrieved from the snapshot feed and the retrieved data are stored in transactions. Prior to transmitting the financial market data to the middleware, the transactions are processed in order to determine value/added information. For example, errors in the financial market data may be determined or additional financial data may be calculated.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventor: Jason Mast
  • Patent number: 11048652
    Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 29, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Perry V. Lea
  • Patent number: 11029878
    Abstract: An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 8, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Kazama
  • Patent number: 11016902
    Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: May 25, 2021
    Assignee: Arm Limited
    Inventors: Geoffray Matthieu Lacourba, Andrew John Turner, Alex James Waugh
  • Patent number: 10929018
    Abstract: A mega cluster storage system includes clusters of multiple storage modules. Each module is able to access a portion of the data within the mega cluster and serves as a proxy in order for another storage module to access the remaining portion of the data. A cluster is assigned to a unique cluster volume and all the data within the cluster volume is accessible by all of the modules within the cluster. Each host connection to the mega cluster is associated with a particular cluster volume. A module that receives a host I/O request determines whether the I/O request should be satisfied by a module within its own cluster or be satisfied by a module within a different cluster. The module may forward the I/O request to a module within a different cluster as indicated by a distribution data structure that is allocated and stored within each storage module.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Zah Barzik, Dan Ben-Yaacov, Mor Griv, Maxim Kalaev, Rivka M. Matosevich
  • Patent number: 10922265
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a transaction request to perform a transaction with the memory, the transaction request including a synchronization indication to indicate utilization of transaction synchronization to perform the transaction. Embodiments may include sending a request to a caching agent to perform the transaction, receiving a response from the caching agent, the response to indicate whether the transaction conflicts or does not conflict with another transaction, and performing the transaction if the response indicates the transaction does not conflict with the other transaction, or delaying the transaction for a period of time if the response indicates the transaction does conflict with the other transaction.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Nicolae Popovici, Thomas Willhalm
  • Patent number: 10917198
    Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: February 9, 2021
    Assignee: Arm Limited
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Tushar P. Ringe
  • Patent number: 10908958
    Abstract: Multiple partitions can be run on a computing device, each partition running multiple processes referred to as a workload. Each of the multiple partitions, is isolated from one another, preventing the processes in each partition from interfering with the operation of the processes in the other partitions. Using the techniques discussed herein, some memory pages of a partition (referred to as a sharing partition) can be shared with one or more other partitions. The pages that are shared are file backed (e.g., image or data files) or pagefile backed memory pages. The sharing partition can be, for example, a separate partition that is dedicated to sharing memory pages.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 2, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Yevgeniy M. Bak, Mehmet Iyigun, Landy Wang
  • Patent number: 10802966
    Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arun Iyengar, Tim Bronson, Michael Andrew Blake, Vesselina Papazova, Arthur o'Neill, Jason D Kohl, Kenneth Klapproth
  • Patent number: 10795818
    Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: October 6, 2020
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Per H. Hammarlund, Brian P. Lilly, Michael Bekerman, James Vash, Manu Gulati, Benjamin K. Dodge
  • Patent number: 10783081
    Abstract: A method controlling near caches in a distributed cache environment including distributed cache servers is provided. The method includes steps of: a specific distributed cache server among the distributed cache servers, if a request signal for original cache data is obtained from a client node, transmitting replicated cache data for the original cache data to the client node, to support the client node to store and refer to the replicated cache data in its corresponding near cache storage part, and managing a reference map with a correspondence between the client node referring to the replicated cache data, and the original cache data; and if the original cache data is changed, checking the number of the client nodes referring to the replicated cache data by referring to the reference map, and invalidating the replicated cache data according to the number of the checked client nodes.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 22, 2020
    Assignee: TMAXSOFT. CO., LTD.
    Inventor: Cliff Roh
  • Patent number: 10776282
    Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 15, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amit P. Apte, Ganesh Balakrishnan, Vydhyanathan Kalyanasundharam, Kevin M. Lepak
  • Patent number: 10761985
    Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 1, 2020
    Assignee: Xilinx, Inc.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10635323
    Abstract: Embodiments of the present disclosure provide methods, apparatuses and computer program products for managing a storage system. The storage system comprises a plurality of cache devices and a bottom storage device, and the plurality of cache devices comprise a first cache device group and a second cache device group. The method according to an aspect of the present disclosure comprises: receiving an input/output (I/O) request for the storage device; in response to determining that the I/O request triggers caching of target data, storing the target data from the storage device into the first cache device group if the I/O request is a read request; and storing the target data into the second cache device group if the I/O request is a write request.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: April 28, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bob Biao Yan, Bernie Bo Hu, Jia Huang, Jessica Jing Ye, Vicent Qian Wu
  • Patent number: 10621342
    Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kenneth D. Johnson, Sai Ganesh Ramachandran, Xin David Zhang, Arun Upadhyaya Kishan, David Alan Hepkin
  • Patent number: 10565129
    Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: February 18, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Felix Schuster, Olga Ohrimenko, Istvan Haller, Manuel Silverio da Silva Costa, Daniel Gruss, Julian Lettner
  • Patent number: 10546157
    Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Jungju Oh, Siddhartha Chhabra, David M. Durham
  • Patent number: 10540115
    Abstract: Memory systems may include a memory including a plurality of dies, and a controller suitable for receiving a host read request during programming of one of the plurality of dies; determining a suspendable die among the plurality of dies based on a suspension threshold; and suspending the determined suspendable die and performing the received request.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 21, 2020
    Assignee: SK hynix Inc.
    Inventors: Wei Zang, Chun Hok Ho