Abstract: Embodiments of the present disclosure provide a method, an apparatus and a computer program product for managing an input/output (I/O). The method comprises, in response to receiving a first I/O request of a first type for a storage device, determining whether there exists at least one credit available to the first type of I/O requests. Each of the at least one credit indicates I/O processing capability reserved by the storage device for the first type of I/O requests. The method further comprises allocating a first credit to the first I/O request based on a result of the determining. The method further comprises performing, by using the first credit, an I/O operation requested by the first I/O request on the storage device. Moreover, the method further comprises, in response to completion of the I/O operation, recycling the first credit for use by a subsequent I/O request. Embodiments of the present disclosure can implement dynamic allocation of I/O processing capability for different types of I/Os.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include a computation module that includes one or more bitwise processors and a combiner. The bitwise processors may be configured to perform bitwise operations between each of the first elements and a corresponding one of the second elements to generate one or more operation results. The combiner may be configured to combine the one or more operation results into an output vector.

Abstract: Methods and systems for maintaining validity of a memory model in a multiple core computer system are described. A first core prevents a store instruction from being performed by another core until a condition is met which enables reordered instructions to validly execute.

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

Abstract: Method and apparatus for interfacing middleware applications with a financial market snapshot feed. Financial market data are retrieved from the snapshot feed and the retrieved data are stored in transactions. Prior to transmitting the financial market data to the middleware, the transactions are processed in order to determine value/added information. For example, errors in the financial market data may be determined or additional financial data may be calculated.

Abstract: The present disclosure includes apparatuses and methods for in data path compute operations. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array. A plurality of shared input/output (I/O) lines provides a data path. The plurality of shared I/O lines selectably couples a first subrow of a row of the array via the sensing circuitry to a first compute component in the data path to move a first data value from the first subrow to the first compute component and a second subrow of the respective row via the sensing circuitry to a second compute component to move a second data value from the second subrow to the second compute component. An operation is performed on the first data value from the first subrow using the first compute component substantially simultaneously with movement of the second data value from the second subrow to the second compute component.

Abstract: An information processing system includes a first processor, a second processor, a first buffer circuit, a second buffer circuit, and a first memory, wherein the first processor is configured to generate a first read command specifying a first data stored in a first address area of the first memory, the second processor is configured to, based on the first read command, generate a second read command specifying a second data stored in a second address area of the first memory, the first buffer circuit is configured to store the first read command, the second buffer circuit is configured to store the second read command, the second processor is configured to execute the first read command stored in the first buffer circuit, and the second processor is configured to execute the second read command stored in the second buffer circuit when the first buffer circuit is in an empty state.

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

Abstract: A mega cluster storage system includes clusters of multiple storage modules. Each module is able to access a portion of the data within the mega cluster and serves as a proxy in order for another storage module to access the remaining portion of the data. A cluster is assigned to a unique cluster volume and all the data within the cluster volume is accessible by all of the modules within the cluster. Each host connection to the mega cluster is associated with a particular cluster volume. A module that receives a host I/O request determines whether the I/O request should be satisfied by a module within its own cluster or be satisfied by a module within a different cluster. The module may forward the I/O request to a module within a different cluster as indicated by a distribution data structure that is allocated and stored within each storage module.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a transaction request to perform a transaction with the memory, the transaction request including a synchronization indication to indicate utilization of transaction synchronization to perform the transaction. Embodiments may include sending a request to a caching agent to perform the transaction, receiving a response from the caching agent, the response to indicate whether the transaction conflicts or does not conflict with another transaction, and performing the transaction if the response indicates the transaction does not conflict with the other transaction, or delaying the transaction for a period of time if the response indicates the transaction does conflict with the other transaction.

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

Abstract: Multiple partitions can be run on a computing device, each partition running multiple processes referred to as a workload. Each of the multiple partitions, is isolated from one another, preventing the processes in each partition from interfering with the operation of the processes in the other partitions. Using the techniques discussed herein, some memory pages of a partition (referred to as a sharing partition) can be shared with one or more other partitions. The pages that are shared are file backed (e.g., image or data files) or pagefile backed memory pages. The sharing partition can be, for example, a separate partition that is dedicated to sharing memory pages.

Abstract: Provided are systems, methods, and media for simultaneous, non-atomic request processing of snooped operations of a broadcast scope within a SMP system. An example method includes detecting, by a first controller, based on a set of coherency resolution conditions, whether there are coherency resolution problems between two snooped operations. The method includes in response to detecting, by the first controller, that coherency resolution problems will not result, transmitting, from the first controller to a second controller, an indication signal indicating that coherency resolution problems will not result from the operation. The set of coherency resolution conditions includes: (a) detecting that a second operation of the two snooped operations operation is of a predetermined type, (b) detecting at time of snooping of the second operation that a directory state does not allow for exclusive data, and (c) detecting that the first controller has started committing to an update.

Abstract: Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

Abstract: A method controlling near caches in a distributed cache environment including distributed cache servers is provided. The method includes steps of: a specific distributed cache server among the distributed cache servers, if a request signal for original cache data is obtained from a client node, transmitting replicated cache data for the original cache data to the client node, to support the client node to store and refer to the replicated cache data in its corresponding near cache storage part, and managing a reference map with a correspondence between the client node referring to the replicated cache data, and the original cache data; and if the original cache data is changed, checking the number of the client nodes referring to the replicated cache data by referring to the reference map, and invalidating the replicated cache data according to the number of the checked client nodes.

Abstract: Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.

Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.

Abstract: Embodiments of the present disclosure provide methods, apparatuses and computer program products for managing a storage system. The storage system comprises a plurality of cache devices and a bottom storage device, and the plurality of cache devices comprise a first cache device group and a second cache device group. The method according to an aspect of the present disclosure comprises: receiving an input/output (I/O) request for the storage device; in response to determining that the I/O request triggers caching of target data, storing the target data from the storage device into the first cache device group if the I/O request is a read request; and storing the target data into the second cache device group if the I/O request is a write request.

Abstract: Speculative side channels exist when memory is accessed by speculatively-executed processor instructions. Embodiments use uncacheable memory mappings to close speculative side channels that could allow an unprivileged execution context to access a privileged execution context's memory. Based on allocation of memory location(s) to the unprivileged execution context, embodiments map these memory location(s) as uncacheable within first page table(s) corresponding to the privileged execution context, but map those same memory locations as cacheable within second page table(s) corresponding to the unprivileged execution context. This prevents a processor from carrying out speculative execution of instruction(s) from the privileged execution context that access any of this memory allocated to the unprivileged execution context, due to the unprivileged execution context's memory being mapped as uncacheable for the privileged execution context.

Abstract: In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.

Abstract: The present disclosure is directed to a flexible counter system for memory protection. In general, a counter system for supporting memory protection operations in a device may be made more efficient utilizing flexible counter structures. A device may comprise a processing module and a memory module. A flexible counter system in the memory module may comprise at least one data line including a plurality of counters. The bit-size of the counters may be reduced and/or varied from existing implementations through an overflow counter that may account for smaller counters entering an overflow state. Counters that utilize the overflow counter may be identified using a bit indicator. In at least one embodiment selectors corresponding to each of the plurality of counters may be able to map particular memory locations to particular counters.

Abstract: A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

Abstract: A coherence decoupling buffer. In accordance with a first embodiment, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.

Abstract: Memory systems may include a memory including a plurality of dies, and a controller suitable for receiving a host read request during programming of one of the plurality of dies; determining a suspendable die among the plurality of dies based on a suspension threshold; and suspending the determined suspendable die and performing the received request.

Abstract: Techniques for automated speech recognition (ASR) are described. A user can upload an audio file to a storage location. The user then provides the ASR service with a reference to the audio file. An ASR engine analyzes the audio file, using an acoustic model to divide the audio data into words, and a language model to identify the words spoken in the audio file. The acoustic model can be trained using audio sentence data, enabling the transcription service to accurately transcribe lengthy audio data. The results are punctuated and normalized, and the resulting transcript is returned to the user.

Abstract: An integrated circuit can include a slave processor configured to execute instructions. The slave processor can be implemented in programmable circuitry of the integrated circuit. The integrated circuit also can include a processor coupled to the slave processor. The processor can be hardwired and configured to control operation of the slave processor.

Abstract: A data processing system includes a processor and a cache controller coupled to the processor, and adapted to be coupled to a memory. The cache controller uses the memory to form a pseudo direct mapped cache having a plurality of groups of pages. The memory forms a first number of selected pages, including a first page for storing a plurality of sets of tags and a plurality of remaining pages for storing data. Each tag, of the plurality of sets of tags, stores tags for respective entries in a corresponding one of the plurality of remaining pages.

Abstract: A method includes: receiving a coherent request from a requester; looking up a state array of a snoop filter table corresponding to an index identified by the coherent request; determining state information corresponding to the coherent request; and determining to access one or more address tag arrays of the snoop filter table based on one or more of the state information, the requester, and a type of the coherent request.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: An embodiment of a memory apparatus may include a managed flash controller to control a managed flash device, and a flash access restriction enforcer communicatively coupled to the managed flash controller to enforce access controls on read and write transactions to the managed flash device. Other embodiments are disclosed and claimed.

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.

Abstract: In an operation scheduler adapted to schedule in an asynchronous contention-based system a first FIFO queue is adapted to store one trigger message or one operation request. A message router is coupled to the first FIFO queue and is adapted to route instructions to a second FIFO queue or a memory and locate in the memory the instructions of a suspended operation associated with a trigger message and authorize execution of the suspended operation. An arbitration unit is coupled to the second FIFO queue and to the memory, and is adapted to schedule the execution of instructions associated with a standalone non-preemptable operation during a period of time within which at least one operation of the first sequence is being suspended.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.

Abstract: Techniques are described for providing a local cache for media content playback. A proxy device on a local network can store fragments of media content received from a media server in a local cache. Viewer devices on the local network can request the fragments from the local cache when a bandwidth of a communication connection between the viewer devices and the media server degrades.

Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

Abstract: Test cases for testing speculative execution of instructions are replicated into a memory with non-naturally aligned data boundaries to create a non-contiguous instruction stream to efficiently test a processor. Placing test cases with test code and test data in the non-naturally aligned data boundaries as described herein allows test code to test speculative execution of branches. The test case includes a branch with a hint bit set to cause the hardware to mispredict the path of the branch to cause speculative execution of test code, bad code or erroneously execute data. The processor can then be tested to see if it properly flushes the speculatively executed code upon taking the opposite branch of the mispredicted path.

Abstract: According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.

Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.

Abstract: A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to a prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table. The method further comprises determining if the matching entry provides a valid prediction and, if valid, retrieving a location for the prior aliasing store instruction using the distance field. The method finally comprises performing a gating operation on the load operation.

Abstract: A data processing apparatus is provided including a memory hierarchy having a plurality of cache levels including a forwarding cache level, at least one bypassed cache level, and a receiver cache level. The forwarding cache level forwards a data access request relating to a given data value to the receiver cache level, inhibiting the at least one bypassed cache level from responding to the data access request. The receiver cache level includes presence determination circuitry for performing a determination as to whether the given data value is present in the at least one bypassed cache level. In response to the determination indicating that the data value is present in the at least one bypassed cache level, one of the at least one bypassed cache level is made to respond to the data access request.

Abstract: A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

Abstract: An apparatus for gating a load operation is presented. The apparatus comprises a memory resident data structure, wherein the memory resident data structure is a prediction table comprising a plurality of entries, wherein a matching entry corresponding to the load operation within the prediction table comprises a prediction regarding a dependence of the load operation on a prior aliasing store instruction, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to the prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table, wherein the prediction strength influences a gating of the load operation.

Abstract: The present application includes apparatuses and methods for compute enabled cache. An example apparatus includes a compute component, a memory and a controller coupled to the memory. The controller configured to operate on a block select and a subrow select as metadata to a cache line to control placement of the cache line in the memory to allow for a compute enabled cache.

Abstract: A microprocessor comprises a cache including a tag array; a tagpipe that arbitrates access to the tag array; and a logic analyzer for investigating a starvation, livelock, or deadlock condition. The logic analyzer, which comprises read logic coupled to the tagpipe, is configured to record snapshots of transactions to access the tag array.