Plural Shared Memories Patents (Class 711/148)
  • Patent number: 7801903
    Abstract: Large-scale table data stored in a shared memory are sorted by a plurality of processors in parallel. According to the present invention, the records subjected to processing are first divided for allocation to the plurality of processors. Then, each processor counts the numbers of local occurrences of the field value sequence numbers associated with the records to be processed. The numbers of local occurrences of the field value sequence numbers counted by each processor is then converted into global cumulative numbers, i.e., the cumulative numbers used in common by the plurality of processors. Finally, each processor utilizes the global cumulative numbers as pointers to rearrange the order of the allocated records.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: September 21, 2010
    Assignee: Turbo Data Laboratories, Inc.
    Inventor: Shinji Furusho
  • Patent number: 7797496
    Abstract: A multiprocessor system comprises a first processor (P1) and a second processor (P2) each having an input/output set up for the connection of a tightly coupled semiconductor memory. Furthermore, the multiprocessor system comprises a shared tightly coupled integrated semiconductor memory (101), which can be accessed by both processors (P1, P2) via their input/output.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: September 14, 2010
    Assignee: Infineon Technologies AG
    Inventors: Hans-Georg Gruber, Carsten Mielenz
  • Publication number: 20100228908
    Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 9, 2010
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Dinesh Maheshwari
  • Publication number: 20100223432
    Abstract: A physical memory location among multiple programs is shared among multiple programs. In one embodiment, multiple memory units are scanned to detect duplicated contents in the memory units. The memory units are used by programs running on a computer system. A data structure is used to identify memory units of identical contents. To improve performance, an additional data structure can be used to identify memory units of identical contents. Memory units that are identified to have identical contents can share the same physical memory space.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 2, 2010
    Applicant: Red Hat, Inc.
    Inventors: Izik Eidus, Andrea Arcangeli, Christopher M. Wright
  • Patent number: 7783716
    Abstract: Systems and methods for optimizing storage network functionality. The methods and systems of the present invention are particularly useful for optimizing storage network performance for cases in which some components of the network may be separated by significant distances and/or which include communication links with relatively limited bandwidth. In certain aspects, the present invention provides methods and systems for implementing access to and management of geographically distributed storage resources through multiple peer-to-peer storage network array management functions (AMFs) that may also be geographically distributed. The methods and systems of the present invention, in certain aspects, provide geographically aware cache sharing, cache replication, cache coherence, traffic routing, redundancy group structure, source and destination selection, pre-fetching of data, message gathering and other useful features.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: August 24, 2010
    Assignee: EMC Corporation
    Inventor: Geoff Hayward
  • Publication number: 20100211748
    Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
    Type: Application
    Filed: April 11, 2008
    Publication date: August 19, 2010
    Applicant: RAMBUS INC.
    Inventors: Richard E. Perego, Frederick A. Ware
  • Patent number: 7774554
    Abstract: A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Piyush Chaudhary, Rama K. Govindaraju, Jay Robert Herring, Peter Hochschild, Chulho Kim, Rajeev Sivaram, Hanhong Xue
  • Patent number: 7774562
    Abstract: A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: August 10, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard W. Adkisson, Christopher Greer, Huai-ter Victor Chong
  • Patent number: 7769861
    Abstract: An apparatus, system, and method are disclosed for provisioning storage resources according to a modeling policy. The modeling apparatus includes a monitoring module, a policy module, and a provisioning module. The monitoring module monitors the storage resources on the storage system. The policy module stores and maintains storage management, storage provisioning, and storage resource modeling policies. A user may access and specify these policies via a specification module. The provisioning module automatically provisions new storage resources, such as logical unit numbers (LUNs) according to the storage provisioning policies and modeling policies. The modeling policy defines a modeling strategy by which new storage resources are provisioned to include some or all of the attributes of a model storage resource.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Justin Russell Bendich, David Maxwell Cannon, Alireza Razzaghi Daryan, Brian Augustine Delaire, Barry Lynn Eberly, David Wilson Groves, Srinivas Jandhyala, Michael Loren Lamb, Edward Martin McCrickard, Raymond Matthew Swank
  • Patent number: 7765339
    Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data addressing is distributed amongst channels to improve system performance and durability. In one embodiment, each channel has an address translation table or address map which is utilized to gain performance improvement during data transfer or erasure, and an increase of the device's useful life span.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: July 27, 2010
    Assignee: STEC, Inc.
    Inventors: Nader Salessi, Hooshmand Torabi
  • Patent number: 7765370
    Abstract: During the normal operation state of a computer system 1000, the data stored in a primary storage system 200P is copied to an intermediate storage system 200I via synchronous copying and the data stored in the intermediate storage system 200I is copied to a secondary storage system 200R via asynchronous copying. During the reverse operation state, however, the data stored in the secondary storage system 200R is copied to the intermediate storage system 200I via asynchronous copying and the data stored in the intermediate storage system 200I is copied to the primary storage system 200P via synchronous copying. In this way, practical remote copying can be carried out in a computer system in which three or more storage devices are installed at different locations and connected serially.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 27, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Iwamura, Yoshihiro Asaka, Hiroshi Arakawa, Kenta Ninose
  • Patent number: 7757049
    Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 13, 2010
    Assignee: Oracle America, Inc.
    Inventors: Andrew B. Hastings, Anton B. Rang, Alok N. Choudhary
  • Publication number: 20100175064
    Abstract: A method is provided for data storage management in a virtualized information handling system that includes a first and second network storage resource, a hypervisor allowing multiple virtual machines to run on the virtualized information handling system, and a data access agent. The data access agent may intercept a data access request initiated by a virtual machine and intended for the first network storage resource. In response to intercepting the data access request, the data access agent may establish a connection with the first network storage resource, and retrieve from the first network storage resource metadata associated with the data access request. The retrieved metadata may identify a location of the second network storage resource. Additionally, the data access may establish a connection with the second network storage resource using the location of the second network storage resource identified by the retrieved metadata.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Applicant: DELL PRODUCTS L.P.
    Inventor: Surender Brahmaroutu
  • Publication number: 20100171748
    Abstract: A motion desktop, including a moving image, may be presented on a display screen of a processing device. Foreground items such as, for example, icons and associated text, or other information, may appear on a surface of the motion desktop. In embodiments consistent with the subject matter of this disclosure, foreground content may be rendered to a composing surface, which may be an alpha-enabled surface capable of presenting translucent items. A motion desktop module may render content for at least a portion of a background of the motion desktop to a respective shared memory, shared with a composer. The composer may periodically copy the rendered content from the shared memory to the composing surface, where the composer may compose and blend a scene from background and foreground content. The composed scene may then be presented as the motion desktop.
    Type: Application
    Filed: March 16, 2010
    Publication date: July 8, 2010
    Applicant: Microsoft Corporation
    Inventors: John Shepard, Felix Cheung, Alex Aben-Athar Kipman
  • Patent number: 7752281
    Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: July 6, 2010
    Assignee: Broadcom Corporation
    Inventor: Joseph B. Rowlands
  • Patent number: 7747827
    Abstract: The storage system includes disk control clusters. Each cluster has channel IF units, disk IF units and local shared memory units. The channel IF units, disk IF units and local shared memory units in the plurality of disk control clusters are connected to each other across the disk control clusters by interconnection, global information control unit for storing management information about the disk control clusters is connected to the interconnection. Host computers and the channel IF units of the disk control clusters are connected via front-end switch for storing copy of the management information. Since the front-end switch reflects the contents of the copy of the management information on routing table, an access request from the host computer can be sent to a suitable disk control cluster.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: June 29, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Kazuhisa Fujimoto
  • Patent number: 7739458
    Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: June 15, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Junichi Minato
  • Patent number: 7739457
    Abstract: An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii
  • Patent number: 7739349
    Abstract: A multiple computer system is disclosed in which the local memory of each computer (M1, M2, . . . Mn) can be different having some memory locations (A, B) which are replicated in other computers and other memory locations (E) which are not. When any computer seeks to acquire or release a synchronizing lock a check (171, 181) is made to see if the relevant memory location is present on any other machine. If yes, synchronization is carried out. However, if no, then no synchronization is required and the synchronizing procedures are by-passed.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: June 15, 2010
    Assignee: Waratek Pty Limited
    Inventor: John M. Holt
  • Patent number: 7734957
    Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: June 8, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Nakamura, Akira Fujibayashi, Mutsumi Hosoya
  • Patent number: 7735099
    Abstract: Method and system for a network for receiving and sending network packets is provided. The system includes a host processor that executes an operating system for a host system and at least one application that runs in a context that is different from a context of the operating system; and a network adapter with a hardware device that can run a network protocol stack, wherein the application can access the network adapter directly via an application specific interface layer without using the operating system and the application designates a named memory buffer for a network connection and when data is received by the network adapter for the network connection, then the network adapter passes the received data directly to the designated named buffer.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 8, 2010
    Assignee: QLOGIC, Corporation
    Inventor: Charles Micalizzi, Jr.
  • Patent number: 7734878
    Abstract: Systems, methods, apparatus and software can make use of separated I/O processors and strategy processors (implemented in hardware and/or software) to perform virtual device I/O operations. I/O processors operating on cluster nodes, storage appliance ports, or other devices can receive I/O operation requests directed to virtual devices, e.g., volumes or virtual logical units. Information about the request is forwarded to a strategy processor, operating independently or as part of larger volume management software where corresponding physical device I/O operations are determined. The physical device I/O operations can include additional information about the operations, e.g., tag information and summary information, for use in processing the virtual device I/O request. The physical device I/O operations are sent back to the I/O processor which executes the operations and/or passes the operation on to the appropriate storage device.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: June 8, 2010
    Assignee: Symantec Operating Corporation
    Inventors: Gopal Sharma, Oleg Kiselev, Santosh Shankar Rao
  • Patent number: 7730154
    Abstract: A method, a system, an apparatus, and a computer program product are presented for fragment caching. After a message is received at a computing device that contains a cache management unit, a fragment in the message body of the message is cached. Subsequent requests for the fragment at the cache management unit result in a cache hit. The cache management unit operates equivalently in support of fragment caching operations without regard to whether the computing device acts as a client, a server, or a hub located throughout the network; in other words, the fragment caching technique is uniform throughout a network. Cache ID rules accompany a fragment from an origin server; the cache ID rules describe a method for forming a unique cache ID for the fragment such that dynamic content can be cached away from an origin server.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Rajesh S. Agarwalla, James R. H. Challenegr, George P. Copeland, Arun K. Iyengar, Mark H. Linehan, Subbarao Meduri
  • Patent number: 7730153
    Abstract: A server storage system operating in a cluster mode, and a method for operating the server system that provides additional memory for use by a non-failed server to store log records while taking over the operations of a failed server.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: June 1, 2010
    Assignee: NetApp, Inc.
    Inventors: Abhijeet Gole, Naveen Bali
  • Patent number: 7730267
    Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventor: Timothy C. Pepper
  • Patent number: 7725663
    Abstract: A shared memory controller is provided for controlling access to a shared memory by a plurality of processors. At least one device includes a storage area for storing a respective address range for each of a plurality of memory regions. The at least one device further includes a permission table containing, for each of the plurality of memory regions, read and write permission data for each of the plurality of processors. A memory fault detector is coupled to the at least one device and has an input for receiving a memory access request including a memory address, a processor identification and a read/write indicator. The memory fault detector includes logic for determining whether a memory access according to the memory access request would conflict with the read and write permission data in the permission table.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 25, 2010
    Assignee: Agere Systems Inc.
    Inventors: William R. Bullman, Scott McCurdy
  • Patent number: 7711909
    Abstract: It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: May 4, 2010
    Assignee: Oracle America, Inc.
    Inventors: Yosef Lev, Mark S. Moir
  • Patent number: 7707351
    Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 27, 2010
    Assignee: Ring Technology Enterprises of Texas, LLC
    Inventors: Melvin James Bullen, Steven Louis Dodd, William Thomas Lynch, David James Herbison
  • Patent number: 7703098
    Abstract: By exploiting an early release facility that may be provided by certain transactional memory designs, we allow for transaction software constructs that wait on removal (or satisfaction) of a condition that would otherwise result in transaction abort. Absent exploitation of such a such a facility, the act of checking the condition would typically introduce a corresponding location into the read set of the transaction, and a subsequent modification of that location that removed (or satisfied) the condition, would result in abortion of the blocked transaction. By exploiting an early release facility such as described herein, a transaction may release the location (or locations) corresponding the condition, retry, and once the transient condition is removed (or satisfied), complete and commit. In this way, computation effort may be conserved while still employing a conceptually simple and convenient coordination facility.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 20, 2010
    Assignee: Sun Microsystems, Inc.
    Inventors: Mark S. Moir, Maurice Herlihy
  • Patent number: 7702755
    Abstract: Methods and apparatus are described which provide secure interactive communication of text and image information between a central server computer and one or more client computers located at remote sites for the purpose of storing and retrieving files describing and identifying unique products, services, or individuals. Textual information and image data from one or more of the remote sites are stored separately at the location of the central server computer, with the image data being in compressed form, and with the textual information being included in a relational database with identifiers associated with any related image data. Means are provided at the central computer for management of all textural information and image data received to ensure that all information may be independently retrieved. Requests are entered from remote terminals specifying particular subject matter, and the system is capable of responding to multiple simultaneous requests.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: April 20, 2010
    Inventor: Barry H. Schwab
  • Patent number: 7702873
    Abstract: An apparatus and method for managing of common storage in a storage system is disclosed. In one embodiment, a storage system receives a request to set a space reservation for a volume associated with a logical aggregation of physical storage. In response, the storage system sets the space reservation to indicate that the logical aggregation of physical storage is to provide a specified amount of space to the volume. In one embodiment, space within the logical aggregation of physical storage is automatically reclaimed to set a delayed space reservation if the amount of unused space within the logical aggregation of physical storage is insufficient to set the space reservation. In one embodiment, the volume is either a space-reclaimable volume or a non-space-reclaimable volume. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 20, 2010
    Assignee: Network Appliance, Inc.
    Inventors: Peter Griess, David A. Grunwald, Jason A. Lango, Qinghua Zheng
  • Patent number: 7698374
    Abstract: Embodiments of the present invention are directed to methods and systems of storing data in storage volumes while ensuring data matching between the storage volumes. In one embodiment, a system for storing data comprises a first storage area to store data, a second storage area to store data, a first storage control unit configured to control the first storage area, and a second storage control unit configured to control the second storage area. In response to a first write request issued to write data in the first storage area, the first storage control unit is configured to write data associated with the first write request to the first storage area and to transfer the first write request to the second storage control unit, and the second storage control unit is configured to write the data associated with the first write request to the second storage area.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 13, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Ido, Mitsuru Kashiwagi
  • Patent number: 7697363
    Abstract: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoe-Ju Chung
  • Patent number: 7698704
    Abstract: Two methods (native and clone) are used for installing software, such as an operating system, on client system(s) booting from shared storage. The native installation method configures an interconnection network to create an exclusive communication zone between the client system and the shared storage system and installs the operating system on the client system using the exclusive communication zone. After the software is installed, the method terminates the exclusive communication zone. The clone installation method utilizes a point-in-time copy feature of the shared storage system to clone an operating system drive instantaneously. After the drive is cloned, it is logically attached to a new client and the operating system is customized for that client.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, James W. Arendt, Mohammad Banikazemi, D. Scott Guthridge, Dan E. Poff, Ziv Rafalovich, Linda A. Riedle, Gary Valentin, Nancy M. Wei
  • Patent number: 7698336
    Abstract: Techniques for associating geographic-related information with objects are described. In one implementation, a search is conducted on a keyword string of one or more keywords descriptive or otherwise representative of a geographically-relevant object. If a location is identified, geographic-related semantic information of the location is associated with the geographically-relevant object. In some cases, multiple possible locations may be identified as a result of searching the keyword string. If multiple locations are identified, a probable location is determined and then geographic-related semantic information of the probable location is associated with the geographically-relevant object described by the keyword string.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: April 13, 2010
    Assignee: Microsoft Corporation
    Inventor: Suman K. Nath
  • Patent number: 7694073
    Abstract: In a cluster-structured disk subsystem, when creating a volume for an online backup separately from a volume for a normal I/O, it is desirable to be able to achieve such a creation for any volume under subsystem. Further, with an increase in the capacity of the subsystem, it becomes more difficult for a user to determine where to place a volume to which data is to be copied. Thus, a cluster-structured storage system is provided in which it is possible to reference/renew snapshot control information in shared memory of other clusters and achieve a snapshot between clusters via an inter-cluster connecting mechanism. In this system, control is performed inside/outside the cluster, and a control is performed inside/outside the cluster, and a volume to which data is to be copied is suggested to the user.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: April 6, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Ai Satoyama, Yasutomo Yamamoto, Takashi Oeda, Kouji Arai
  • Publication number: 20100082909
    Abstract: A control method for a memory system includes a plurality of processing apparatuses each having a comparison data holding area and a replacement data holding area, and a plurality of storage units each having a readout data holding area rewritably holding readout data and a memory unit shared by the plurality of processing apparatuses. The control method includes issuing an exclusive control instruction to exclusively access to one of the memory units from one of the processing apparatuses, sending comparison data to one of the plurality of storage units from the comparison data holding area of the one of the processing apparatuses when the exclusive control instruction is executed, and comparing the comparison data sent from the one of the processing apparatuses with the readout data in the storage unit.
    Type: Application
    Filed: September 11, 2009
    Publication date: April 1, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Asakai
  • Patent number: 7689986
    Abstract: A system for sharing listeners monitoring events occurring in objects shared by multiple applications each running inside its own virtual machine in a computer system.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: March 30, 2010
    Assignee: GemStone Systems, Inc.
    Inventors: David J. Monnie, Robert Bretl
  • Patent number: 7689799
    Abstract: Method and apparatus for specifying and identifying logic volumes in computer systems that store logical volumes on multiple storage elements are disclosed. The logical volume identifier may be unique with respect to all other logical volumes stored on the storage elements. The logical volumes may be conventional logical volumes, partitions, or hyper volumes.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: March 30, 2010
    Assignee: EMC Corporation
    Inventor: David Black
  • Patent number: 7689787
    Abstract: In a control device of a computer system in which a plurality of host computers are capable of sharing a same host interface of a storage system are provided: a VOL status monitoring portion that monitors a VOL status of each VOL mapped to the VVOL and determines whether or not the VOL status is changed, and a path number control portion that updates the number of paths connecting to a VVOL in which the VOL status has changed.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: March 30, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Nakase, Shinya Takeuchi, Yasufumi Uchiyama
  • Patent number: 7689783
    Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Harm Peter Hofstee, Charles Ray Johns, James Allan Kahle
  • Publication number: 20100077253
    Abstract: A method includes establishing a first link between a first processor device and a first memory module at a first time. A second link is established between a second processor device and a second memory module at a second time. In response to receiving a first event indicator, a third link is established between the first processor device and the second memory module at a third time, the third time after the first time and the second time.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 25, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David M. Lynch, Andelon X. Tra, Oswin E. Housty
  • Publication number: 20100077156
    Abstract: A processing device that processes data with use of one or more data blocks shared with a plurality of external processing devices. The device includes: a processor; a shared data storage unit that stores, respectively in one or more storage areas thereof, one or more data blocks to be shared with one or more external processing devices; an output unit that outputs, when the processor makes an access request to write data in a part of one of the data blocks, a block identifier identifying the one of the data blocks, and the data pertaining to the access request; and an input unit that judges whether to share external data outputted from one of the external processing devices, based on a block identifier outputted from the one of the external processing devices, and only when judging affirmatively, causes the shared data storage unit to store the external data.
    Type: Application
    Filed: March 18, 2009
    Publication date: March 25, 2010
    Inventor: Tetsuji Mochida
  • Publication number: 20100070718
    Abstract: Methods, systems and computer program products to maintain cache coherency, in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.
    Type: Application
    Filed: November 18, 2009
    Publication date: March 18, 2010
    Applicant: Broadcom Corporation
    Inventor: Fong Pong
  • Patent number: 7676809
    Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Basu Vaidyanathan, Larry Bert Brenner
  • Patent number: 7676628
    Abstract: Methods, systems, and computer program products for providing access to shared storage by a plurality of nodes are disclosed. According to one method, at a node of a plurality of nodes sharing access to a disk array, an application input/output (I/O) operation and whether sufficient space in the disk array has been mapped at the node for the I/O operation are detected. In response to detecting that sufficient space in the disk array has not been mapped at the node for the I/O operation, a map for the I/O operation including physical disk access information is requested and obtained from a server. The physical disk access information included within the map for the application I/O operation obtained from the server is used to perform the I/O operation by accessing the disk array without intervention by the server.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 9, 2010
    Assignee: EMC Corporation
    Inventors: James T. Compton, Uday K. Gupta, Sorin Faibish, Roy E. Clark, Stephen Fridella, Xiaoye Jiang
  • Patent number: 7669018
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include initiating a first store operation to a cache data block stored in a first cache from a first processing node including the first cache and assigning a modified cache state to the cache data block in response to initiating the first store operation. The method may further include evicting the cache data block from the first cache subsequent to initiating the first store operation, storing the cache data block in a remote cache in response to the evicting, and assigning a remote directory state to a coherence directory entry corresponding to the cache data block in response to storing the cache data block in the remote cache, where the remote directory state is distinct from an invalid directory state.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 23, 2010
    Assignee: Globalfoundries Inc.
    Inventor: Patrick N. Conway
  • Patent number: 7664921
    Abstract: A method for accessing shared memory cards from each of plural processor cards is disclosed. The shared memory cards are composed of a shared memory card of an operating system and a shared memory card of a standby system in a redundant configuration, and each of plural processor cards individually access the shared memory cards. Each of the plural processor cards is connected to the shared memory card of the operating system and the shared memory card of the standby system in a point-to-point structure via corresponding serial buses and executes data transmission on a one to one basis to/from the shared memory card of the operating system and the shared memory card of the standby system.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: February 16, 2010
    Assignee: Fujitsu Limited
    Inventors: Hideo Okawa, Kazunori Uemura, Kunio Yamaguchi
  • Publication number: 20100030976
    Abstract: A control device is connected to a processor, a memory module, and a specification information storage memory for storing specification information indicating specifications of the memory module. The control device includes: a readout unit that reads the specification information from the specification information storage memory when power is turned on to the control device; a storage unit that stores the specification information read from the specification information storage memory; and a transfer unit that receives a specification information read instruction from the processor, and that transfers the specification information stored in the storage unit to the processor.
    Type: Application
    Filed: May 29, 2009
    Publication date: February 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Keisuke Tashima, Yukio Oguma
  • Publication number: 20100023704
    Abstract: A system and method for executing a transaction in a transactional memory system is disclosed. The system includes a processor of a plurality of processors coupled to shared memory, wherein the processor is configured to execute a section of code, including a plurality of memory access operations to the shared memory, as an atomic transaction relative to the execution of the plurality of processors. According to embodiments, the processor is configured to determine whether the memory access operations include any of a set of disallowed instructions, wherein the set includes one or more instructions that operate differently in a virtualized computing environment than in a native computing environment. If any of the memory access operations are ones of the disallowed instructions, then the processor aborts the transaction.
    Type: Application
    Filed: July 28, 2009
    Publication date: January 28, 2010
    Inventors: David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst