Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.

Abstract: A method of creating a copy of a virtualized storage region in a data processing system for virtualizing the storage region. A server manages the correlation between the virtualized storage region and the physical storage region, utilizes the function of the storage unit for those physical storage regions having a function, and the function for those physical storage regions without the function, to efficiently copy the virtualized storage region.

Abstract: A flash memory system for an A/V player, utilizing a two-level round-robin write scheme upon N flash memory planes, enabling the A/V player to be loaded with data at a data throughput essentially N times the write throughput of one of the flash memory planes. The flash chips' memory cores and data registers, and the memory system's write buffers, can be kept fully utilized during data writing.

Abstract: A method for processing data in a computer system using two main concepts for addressing this situation, from which numerous other implementations is achieved using a first and second main concept. The first is a method of managing a common data path among a plethora of facilities with a decentralized distributed management scheme. The second concept is a method for managing a shared data buffer or group of buffers between multitudes of facilities. By employing the concepts discussed in this invention, one can contemplate a complex dataflow consisting of a multiplicity of resources and data paths, whereby virtually any combination of sharing is possible. A single data path can be shared among multiple sources or sinks.

Abstract: The present invention aims to provide a high-reliability, low-cost disk array by emulating an ATA drive so that it can be used in the same way as an FC drive. To achieve this object, a disk array system of the present invention includes: a storage device having a logical unit logically set therein; the storage device includes: a plurality of disk devices having a first interface; and an interface converter converting between signals of the first interface adapted for the disk device and signals of a second interface adapted for the control device. The interface converter includes: a response time monitor portion for monitoring a time until a response is received from the disk device according to the data input/output request; and a notification issue portion for issuing to the control device a notification about an operative state of the disk device according to the monitored response time.

Abstract: A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different nodes. The monitoring process intelligently collects data from monitored threads according to the node it which it is executing to reduce the proportion of inter-node data accesses. Preferably, the monitoring process has the capability to specify a node to which it should be dispatched next to the dispatcher, and traverses the nodes while collecting data from threads associated with the node in which the monitor is currently executing. By intelligently associating the data collection with the node of the monitoring process, the frequency of inter-node data accesses for purposes of collecting data by the monitoring process is reduced, increasing execution efficiency.

Abstract: A method for processing using a shared file that includes allocating a first working buffer between the shared file and a plurality of address spaces, wherein each of the plurality of address spaces is associated with one of a plurality of processors, copying first data from the shared file to the first working buffer by a first aggregator copying the first data from the first working buffer to the plurality of address spaces by the first aggregator, processing the first data, in parallel, by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.

Abstract: Techniques for caching media data, including streaming media data, using content-sensitive identifiers. The content-sensitive identifiers enable a caching proxy or a caching server to unambiguously determine the version or contents of media data cached by the caching proxy for a particular data pointer or data reference (e.g., a URL) such that an appropriate version of the media data can be served to a requesting client system in an efficient and economical manner.

Abstract: A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

Abstract: A first storage system includes a first storage area for storing data written by a computer. A second storage system includes a second storage area to which the data stored in the first storage area migrates. A third storage system includes a virtual storage area corresponding to the second storage area. An access request to the virtual storage area is converted into an access request to the second storage area to be issued. A management computer transmits, to the third storage system, an instruction to migrate the data of the second storage area to a third storage area of the third storage system based on a determination result between a value of the data migrated to the second storage area and a predetermined threshold value.

Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.

Abstract: Dynamic access is provided to automation resources, where, in a distributed automation system having a plurality of automation components, a first automation component searching for an automation resource sends a request to the automation system and, for this request, receives a response regarding availability of suitable automation resources from all automation components which it has been possible to reach, and then selects that automation component which has the suitable automation resource and uses the automation resource.

Abstract: A storage component interconnected via a network includes a recording unit for recording various contents, a first management table, a second management table and a control unit. The first management table manages for each user storage capacity in use by users in each recording unit of the storage components on the network. The second management table manages for each user total storage capacity that each user is allowed to use in all the recording units of the storage components on the network. The control unit restricts the storage capacity in use by the users so that the storage capacity used by the user does not exceed the total storage capacity that the user is allowed to use, on the basis of the first management table and the second management table.

Abstract: A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory.

Abstract: A system and method of maintaining connectivity between a host computer and a target on a storage router. A failover driver is established in a stack of an operating system of the host computer. A first network connection is established between the host computer and the target on the storage router. The failover driver monitors connectivity information associated with the first network connection and, if failure of the first network connection is detected, establishes a second network connection between the host computer and the target on the storage router.

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract: An architecture provides the ability to create and maintain multiple instances of virtual servers, such as virtual filers (vfilers), within a server, such as a filer. A vfiler is a logical partitioning of network and storage resources of the filer platform to establish an instance of a multi-protocol server. Each vfiler is allocated a subset of dedicated units of storage resources, such as volumes or logical sub-volumes (qtrees), and one or more network address resources. Each vfiler is also allowed shared access to a file system resource of a storage operating system. To ensure controlled access to the allocated and shared resources, each vfiler is further assigned its own security domain for each access protocol. A vfiler boundary check is performed by the file system to verify that a current vfiler is allowed to access certain storage resources for a requested file stored on the filer platform.

Abstract: A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by the first and the second processors. The common area has two ports and thereby simultaneously accessible from the first and the second processors. Each capacity of the first, the second, and the common areas can be set arbitrarily.

Abstract: An information-processing apparatus comprises a motion-detecting unit, a motion-compensating unit, a DCT/IDCT unit, a Q/IQ unit, a VLC unit, a VLD unit, and a DSP unit, as a plurality of units. A mode-controlling unit can utilize at least two modes of used of the information-processing apparatus. One mode is a “process mode ” where the processing of moving picture are performed, and another mode is a “memory mode” where all internal memories of the plurality of processing units are logically combined to be directly accessible from the outside as one memory via an interface unit.

Abstract: A shared memory device is disclosed which includes: a plurality of processor elements; a plurality of memory modules configured to be accessible by the plurality of processor elements; and a connection device configured to enable a specific processor element out of the plurality of processor elements to access a specific memory module out of the plurality of memory modules; wherein the plurality of processor elements are allowed to access via the connection device a plurality of memory systems each constituted by at least one memory module; and wherein each of the plurality of memory systems accessible by different processor elements allows the plurality of memory modules to be partially shared and accessed by the different processor elements.

Abstract: A computerized numerical control system includes a human interface computer (1), a PCI bus (4) which is adapted to couple to the human interface computer, and a numerical control device (3). The numerical control device includes an embedded processor (30) and a local bus (34) coupled to the embedded processor. A first and second low cost shared memories such as SDRAMs (10, 11) and a dual bus memory controller (2) are provided. The first and second shared memories are shared by the human interface computer and the embedded processor. The dual bus memory controller is configured for concurrent communication with the PCI bus and the local bus and is adapted to couple to the first and second shared memories.

Abstract: There is a need to improve access speed for a file in a storage system that is provided with multiple storage units having different access speeds.

Abstract: A system and method proxies data access commands across a cluster interconnect between storage appliances in a cluster. Each storage appliance activates two ports for data access, a local port for data access requests directed to clients of the storage appliance and a proxy port for data access requests directed to the partner storage appliance. Clients utilizing multi-pathing software may send data access requests to either the local port of the storage appliance or the proxy port of the storage appliance. The system and method improve high availability especially during a loss of connectivity due to non-storage appliance hardware failure.

Abstract: A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.

Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Abstract: An apparatus for adjusting system performance of computer is fabricated on a motherboard. The apparatus comprises a plurality of performance monitor means and a performance control chip. The performance monitor means are connected separately to bus lines which are applied to connect devices mounted on the motherboard, for monitoring the operating state of each device according to the flow rate of data transferred in the bus lines. The performance control chip is connected separately to the devices, for adjusting the operating rate of the devices responsive to the performance monitor means. The performance control chip is capable of ascertaining the operating rate of each device is busy or not, so as to increasing or decreasing the operating rate of the device.

Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

Abstract: A method for collecting garbage in a computing environment, the method including tracing root objects to their reachable objects in a population of objects, marking the traced objects, unmarking a marked card including any of the objects, tracing any marked object on the unmarked card to an unmarked referent object of the marked object, marking the unmarked referent object, and tracing the marked referent object to its reachable objects, concurrently with the operation of a mutator upon the population of objects within the computing environment, and, while no mutator operates upon the population of objects within the computing environment, marking the traced objects, tracing unmarked root object referents to their reachable objects, marking any of the objects, and designating any unmarked object in the population of objects as available for reallocation.

Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

Abstract: A configurable device interface enhances the ability of a processor to communicate with other devices. The configurable device interface provides programmers with an efficient mechanism for communicating with a wide variety of external memories, each of which may have their own unique interface requirements. As a result, the configurable device interface permits a data processor to operate without hard coded dedicated state machines, and without waiting for an external memory to complete an instruction before the data processor may perform its next instruction.

Abstract: Provided is a method for uniquely masking addressing to the cache memory for each user, thereby reducing risk of a timing attack by one user on another user. The method comprises assigning a first mask value to the first user and a second mask value to the second user. The mask values are unique to one another. While executing a first instruction on behalf of the first user, the method comprises applying the first mask value to set selection bits in a memory address accessed by the first instruction. While executing a second instruction on behalf of the second user, the method comprises applying the second mask value to set selection bits in the memory address accessed by the second instruction. The result offers an additional level of security between users as well as reducing the occurrence of threads or processes contending for the same memory address.

Abstract: Disclosed is a multiprocessor system in which even if contention occurs when a common memory is accessed from each of a plurality of processors, the number of times the common memory is accessed is capable of being reduced. The common memory of the multiprocessor system is provided with a number of data areas that store data and with a control information area that stores control information indicating whether each of the data areas is in use, and each processor is provided with a storage unit equivalent to the common memory and with an access controller. The access controller of a processor that does not have access privilege monitors data and addresses that flow on the common bus, accepts data written to the common memory and data read from the common memory, and stores this data in the storage unit of its own processor, thereby storing content identical with that of the common memory.

Abstract: A data storage facility for transferring data from a data altering apparatus, such as a production data processing site to a remote data receiving site. The data storage facility includes a first data store for recording each change in the data generated by the data altering apparatus. A register set records each change on a track-by-track basis. A second data store has first and second operating modes. During a first operating mode the second data store becomes a mirror of the first data store. During a second operating mode the second data store ceases to act as a mirror and becomes a source for a transfer of data to the data receiving site. Only information that has been altered, i.e., specific tracks that have been altered, are transferred during successive operations in the second operating mode. Commands from the local production site initiate the transfers between the first and second operating modes.

Abstract: An object of the present invention is to allow access to a plurality of logical devices regardless of the number of ports provided in a storage system and the number of logical devices that can be allocated to a single port, and thereby to improve the usability of the logical devices. A storage system comprises a plurality of logical devices, a target device which is the object of access from a computer, and a juke box system for allocating one of the plurality of logical devices to the target device. The juke box system changes the logical device that is allocated to the target device in accordance with a request from the computer.

Abstract: A recording and/or playback apparatus for recording data read out from a first storage medium into a second storage medium, includes a recording device for recording data read out from the first storage medium into the second storage medium, an input unit for inputting identification data identifying the first storage medium in accordance with an operation carried out by the user, and a controller for executing control to associate additional information generated on the basis of the identification data input by the input unit with the data read out from the first storage medium during or after a recording operation carried out by the recording into the second storage medium.

Abstract: A system and methods for sharing configuration information with multiple services, or processes, via shared memory. The configuration information, typically, comprises runtime information utilized by processes during operation, including without limitation, information describing data communication connections between the local computer and other computing resources (i.e., port and wire information), and information defining numeric values or character string values (i.e., genre and record information). The system architecture includes a plurality of APIs which: reside at the local computer; populate, manage, and control access to a shared memory containing the configuration information; and, are executable only by processes executing at the local computer, thereby limiting access to the shared memory. Access to the configuration information is further limited to only those processes identified as having appropriate permission.

Abstract: A method and system for improving memory access patterns of software systems on NUMA systems discovers NUMA system resources where the NUMA system resources comprises a plurality of NUMA nodes; determines a plurality of database threads, processes, and objects for a database configuration; and generates a policy which assigns the plurality of database threads, processes, and objects to the plurality of NUMA nodes, wherein the generating of the policy is performed prior to initialization of the plurality of database threads, processes, and objects. The assignment of the database threads, processes, or objects to NUMA nodes is such that the amount of remote memory accesses is reduced. When the database thread, process, or object initializes, the database server queries the policy for its assigned NUMA node(s). The database thread, process, or object is then bound to the assigned NUMA node(s).

Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.

Abstract: A method of managing a distributed cache structure having separate cache banks, by detecting that a given cache line has been repeatedly accessed by two or more processors which share the cache, and replicating that cache line in at least two separate cache banks. The cache line is optimally replicated in a cache bank having the lowest latency with respect to the given accessing processor. A currently accessed line in a different cache bank can be exchanged with a cache line in the cache bank with the lowest latency, and another line in the cache bank with lowest latency is moved to the different cache bank prior to the currently accessed line being moved to the cache bank with the lowest latency. Further replication of the cache line can be disabled when two or more processors alternately write to the cache line.

Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Abstract: Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than zero. A set of m memories (204) is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic (206) is provided for coupling each of the processing elements to each of the memories. Control logic (208) is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A system and method for writing the same data field to multiple RAM copies during a single write cycle that fans out write data, address data, and control data to multiple RAMs. The multiple copies of data held at the same address in the multiple RAM copies are also read during a single write cycle and the data from each RAM copy is concatenated into a single word that is read during a single read cycle.

Abstract: A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part for at least one of read and write access.

Abstract: A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.

Abstract: An architecture provides the ability to create and maintain multiple instances of virtual servers, such as virtual filers (vfilers), within a server, such as a filer. A vfiler is a logical partitioning of network and storage resources of the filer platform to establish an instance of a multi-protocol server. Each vfiler is allocated a subset of dedicated units of storage resources, such as volumes or logical sub-volumes (qtrees), and one or more network address resources. Each vfiler is also allowed shared access to a file system resource of a storage operating system. To ensure controlled access to the allocated and shared resources, each vfiler is further assigned its own security domain for each access protocol. A vfiler boundary check is performed by the file system to verify that a current vfiler is allowed to access certain storage resources for a requested file stored on the filer platform.

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract: A first array of disk drives overlaps with a second array of disk drives in a Redundant Array of Inexpensive Drives (RAID) system, in which the first and second arrays share at least one disk drive. A first stripe of data from a first client is stored in the first array, and a second stripe of data from a second client is stored in the second array. The shared disk drives are less than the number of drives needed to reconstruct a full stripe. Thus, in the event of a drive failure in the first array, the first client can reconstruct the first data stripe, but is never able to reconstruct the second stripe. Likewise, in the event of a drive failure in the second array, the second client can reconstruct the second data stripe, but is never able to reconstruct the first stripe.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: A distributed cache module that allows for a distributed cache between multiple servers of a network without using a central cache manager. The distributed cache module transmits each message with a logical timestamp. The distributed cache module of a server that receives the message will delay forwarding of the message to, for example, a client computer, if preceding timestamps are not received. This insures a correct order of timestamped messages without requiring a central manager to allocate and control the transmission of the messages within the network. Each distributed cache module will request and possibly retrieve data from the cache of another server in response to a file request for the data. The data of a file may be accessed by a plurality of servers joined in a file context.