Abstract: A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: The present disclosure describes systems and methods for allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distribute shared memory. The systems and methods include allocating memory to input-output devices (I/O devices) based at least in part on which memory resource is physically closest to a particular I/O device. Through these systems and methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory to an I/O device that i80s on the same node as a memory resource, reduces memory access time thereby maximizing data transmission. The present disclosure further describes a system and method for improving performance in a multiprocessor computer system by utilizing a pre-programmed device affinity table. The system and method includes listing the memory resources physically closest to each I/O device and accessing the device table to determine the closest memory resource to a particular I/O device.

Abstract: A method for copying information from a first storage subsystem to a second storage subsystem is disclosed. The first and second storage subsystems are provided in a data storage system. The method comprises transmitting first data block from the first storage subsystem to the second storage subsystem, the first storage subsystem being associated with a first host computer and the second storage subsystem being associated with a second host computer; and transmitting first attribute information from the first storage subsystem to the second storage subsystem without intervention from the first host computer.

Abstract: The present invention discloses a system for sharing a storage device among controllers, which includes a first controller and a second controller connected with each other, and both connected to a storage device including a plurality of logical unit numbers. The controllers detect their respective logical unit numbers and define the respective logical unit number detected by an opposite party as a virtual logical unit number. The controllers separately have a resource allocation unit for specifying the logical unit numbers to perform data accesses for the controllers and define a virtual identification for each virtual logical unit number based on an identification number thereof.

Abstract: The present invention provides a method of implementing a fault-tolerant mutual exclusion lock. The present invention records in a lock structure the IDs of all processes whose failure can lead to the permanent unavailability of the lock. When a process finds the lock unavailable and suspects a permanent failure, it queries the programming environment about the status of all or some of the processes that could have caused the lock's unavailability. If the programming environment determines that these processes have failed, the live process tries to usurp the lock. If it succeeds, it executes some recovery mechanism and frees the lock or proceeds to operate on the objects protected by the lock. The method guarantees recovery from process failures.

Abstract: A number of improvements in network adapters that offload protocol processing from the host processor are provided. Specifically, an improved mechanism for handling receipt of data packets in a system utilizing an offload network adapter. The offload network adapter may include logic that permits the offload network adapter to delay notification of data reception to the host system in different ways. The advantage of delaying the notice of data packet reception to the host system is the potential for aggregation of several data packets, which can arrive immediately after the first one, for example, in a single notification. Given a stream with continuous data packet arrival, a value may be set, either statically or dynamically, for notification delay and this value may be configurable for the host system per communication socket.

Abstract: Provided are a method, system and program for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device.

Abstract: A system comprises a plurality of computing nodes and a plurality of separate memory devices. A separate memory device is associated with each computing node. The separate memory devices are configured as partition memory in which memory accesses are interleaved across multiple of such memory devices. A protected portion of the partition memory is reserved for use by complex management (CM) code that coordinates partitions implemented on the system. The protected portion of partition memory is restricted from access by operating systems running in the partitions.

Abstract: An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.

Abstract: A terminal apparatus and method for controlling access by a processor and coprocessor to data buses that connect memories.

Abstract: A storage system is configured to create and manage virtual ports on physical ports. The storage system can transfer associations between virtual ports and physical ports when a failure occurs in a physical port or a link connected to the physical port so that a host can access volumes under the virtual ports through another physical port. The storage system can also change associations between virtual ports and physical ports by taking into account the relative loads on the physical ports. When a virtual machine is migrated from one host computer to another, the loads on the physical ports in the storage system can be used to determine whether load balancing should take place. Additionally, the storage system can transfer virtual ports to a remote storage system that will take over the virtual ports, so that a virtual machine can be migrated to remote location.

Abstract: A data storage infrastructure is disclosed for a communication network that produces a plurality of data flows of network data. The data storage infrastructure comprises a data storage systems and a storage management system. The data storage systems store the network data using a plurality of data storage service classes, wherein different data storage systems provide different data storage service classes, and wherein the different data storage service classes have different service class values for a plurality of data storage service variables. The storage management system processes characteristics for the data flows to assign data flow values to the data storage service variables for the data flows, compares the data flow values to the service class values, and assigns individual data flows to individual data storage systems based on the comparison of the data flow values to the service class values.

Abstract: A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area.

Abstract: A control method for controlling a recording/reproducing apparatus having plural storage units and an equipment to which the recording/reproducing apparatus is connected. The recording/reproducing apparatus has first and second storage units in which data and management data are stored. The equipment, to which is connected the recording/reproducing apparatus, has a third storage unit in which are stored the data and the management data. It is detected whether the equipment to be connected to the recording/reproducing apparatus has been connected to the recording/reproducing apparatus. If such connection is detected, the management data are read out from the first and second storage units. Based on the read-out management data and the management data stored in the third storage unit of the equipment, connected to the recording/reproducing apparatus, new management data, supervising the first to third storage units as one storage unit, is generated.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: An automated data library system employing a plurality of cartridges, one or more cartridge storage slots and an inventory controller. Each cartridge includes a cartridge memory. The cartridge storage slot(s) is(are) physically configured to store the cartridges. The inventory controller is operable to generate an inventory of the cartridges as stored within the cartridge storage slot(s). A generation by the inventory controller of the inventory of the cartridges as stored within the cartridge storage slot(s) involves the inventory controller simultaneously accessing cartridge identification information on two or more cartridge memories, and generating the inventory including two or more cartridges corresponding to the cartridge identification information.

Abstract: Write order fidelity (WOF) is maintained for totally-active implementations wherein a plurality of access nodes at geographically separated sites can concurrently read and/or write data in a “totally active” fashion on a distributed data system. From the hosts' perspective at diverse geographic locations, a synchronous, cache-coherent view of data is provided. Data transfer is asynchronous. A time ordered data image is created and maintained so operations can be restarted after a partial system failure that causes loss of data not yet asynchronously transferred across the network, but that has been write-acknowledged to the originating host. Time ordered asynchronous data transfer is implemented as a pipeline of changes that reflect contributions from all nodes. WOF also improves network performance and lowers bandwidth consumption.

Abstract: A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved.

Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

Abstract: Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.

Abstract: The storage system includes a plurality of storage nodes and a control device coupling unit. Each of the storage nodes includes at least one storage device configured to store data and at least one control device configured to control input and output of data for the storage device. The control device coupling unit is configured to connect the control devices without using an access path between the control device and a host computer connected to the storage system. The control devices connected by the control device coupling unit are included in mutually different storage nodes.

Abstract: A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area.

Abstract: A data storage system is provided. The data storage system includes a first storage module for storing a first data, a second storage module for storing a second data, a control module and a processing module. The control module generates a first control signal and a second control signal, and accesses the first data and the second data according to the first control signal and the second control signal. The processing module is coupled to the first storage module, the second storage module and the control module, and controls the first storage module and the second storage module to transmit the first data and the second data to the control module according to the first control signal and the second control signal respectively, wherein the processing module bypasses the second storage module when receiving the first control signal.

Abstract: A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

Abstract: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Abstract: A multiple processor system includes a plurality of processors including a first processor and a second processor; a program code storage module coupled to the first processor, the program code storage module for storing program code including first program code for the first processor and second program code for the second processor; and a processor bridge coupled between the first processor and the second processor; wherein the first processor executes the first program code, the second processor is for sending an access request requesting data corresponding to the second program code to the processor bridge; the first processor is for retrieving the access request from the processor bridge, fetching the data from the second program code in the program code storage module according to the access request, and delivering the data to the processor bridge; and the second processor is further for fetching the data from the processor bridge.

Abstract: Provided are a method and apparatus for efficiently transferring a massive amount of multimedia data between two processors. The apparatus includes a first local switch, which connects a virtual page of a first processor element to a shared memory page, a second local switch, which connects a virtual page of a second processor element to the shared memory page, a shared page switch, which connects a predetermined shared memory page of a shared physical memory to the first or second local switch, and a switch manager, which remaps a certain shared memory page of the shared physical memory that stores data of a task performed by the first processor element to the virtual page of the second processor element. Accordingly, since memory remapping is used, the massive amount of multimedia data can be transmitted by changing a method of mapping a memory, unlike a case when multimedia data is transmitted by using a memory bus.

Abstract: A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs.

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract: A memory-use-information memory area stores therein a program ID, a request-source memory address, a request memory size which configure information for uniquely identifying a program file loaded into a storage area for virtual machine-A or storage area for virtual machine-B in association with a physical memory address. A memory reservation section uses, as the retrieval key, the program ID, request-source memory address, and request memory size of a program file corresponding to a memory reservation request to retrieval the memory-use-information memory area. When a entry that matches said retrieval key exists, the memory reservation section allows sharing of the memory area between a plurality of virtual machines.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A method and an apparatus for having a memory shared by a plurality of processors are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a memory, a main processor connected to one side of the memory through a first memory bus, and application processors in a quantity of n connected parallel to the other side of the memory through a second memory bus. Each application processor performs at least one predetermined function. The main processor is connected parallel to the n application processors through a control bus, and delivers a control signal to at least one application processor through the control bus. With the present invention, the structure of a digital processing apparatus can be simplified, and the cost and size of a digital processing apparatus can be minimized.

Abstract: Systems and methods for improved I/O fencing for shared storage in a clustered or grid computing environment. I/O fencing is performed with aid from the storage system and an I/O fencing management client process. The client process detects changes in the operational status of any of the clustered computing nodes. Upon sensing a change from a functional state to a dysfunctional state, the management client process effectuates reconfiguration of the storage system to disallow potentially destructive access by the dysfunctional node to the shared storage volumes. Upon sensing resumption of a functional status for the dysfunctional node, the client effectuates reconfiguration of the storage system to again allow desired access to the shared storage volumes by the now functional node. The client and storage system may share access to a database maintained by the client indicating the shared volumes a node may access and the initiators associated with each node.

Abstract: A device and a method for sharing a memory interface are disclosed. According to preferred embodiments of the present invention, a supplementary control unit included in a digital processor can control some of the pins, constituting a memory interface, to be shared by a plurality of memory. With the present invention, the number of pins included in a memory interface can be minimized, thereby reducing the size of a supplementary control unit, saving the manufacturing cost, and improving the processing efficiency.

Abstract: A method for implementing the invention is carried out in a data-storage system having a data storage unit that includes at least two constituent data storage elements. Each of the constituent data storage elements is either in a first state or a second state. The method includes providing a data structure having an entry corresponding to the data storage unit. The entry includes status information indicating whether at least one constituent data storage element of the data storage unit is in the first state. These entries are updated as necessary following any changes in state of the constituent data storage element. Scanning the data storage units instead of the data storage elements provides a more efficient way to locate data storage elements in the first state, particularly where such data storage elements are rare.

Abstract: An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an identical memory address concurrently, the controller controls the switch device which connects the clusters and the memory banks of the memory subsystem, so that the data item is transmitted from the cluster issuing the store instruction to the cluster issuing the load instruction through the switch device, thereby achieving data exchange between the clusters. Herein, the data item is selectively stored in the memory module depending on the address. Furthermore, the data item is also transmitted between the memory and the clusters over the switch device.

Abstract: A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.

Abstract: A storage processor is constructed on or within an interconnected circuit (IC) chip. The storage processor has a plurality of ports operable to send and/or receive messages to/from storage devices. An output indication circuit is associated with each output port. The indication circuit indicates that data is ready to be transmitted to a storage device from the particular output port. A crossover circuit is interposed between the ports. The crossover circuit has a memory that can store data. When data is received at a port, the storage processor can store the incoming data to the crossover circuit. A memory is also present on the chip. The memory holds data that relates incoming data to outgoing data. Thus, when data comes into the storage processor, the storage processor can determine a specific course of action for that data based upon the information stored in this memory. The chip also has a plurality of processing sub-units coupled to the crossover switch.

Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluster includes mechanisms for instructing probed remote clusters to respond to the request cluster instead of to the home cluster. The home cluster can also include mechanisms for reducing the number of probes sent to remote clusters. Techniques are also included for providing the requesting cluster with information to determine the number of responses to be transmitted to the requesting cluster as a result of the reduction in the number of probes sent at the home cluster.

Abstract: A method and an apparatus to reduce network utilization for source-based snoopy cache coherent protocols have been disclosed. In one embodiment, the method includes receiving at a first processor an invalidating snoop with respect to a physical address of a portion of a memory in a multiprocessor system from a second processor, checking whether a cache of the first processor stores a copy of data associated with the physical address, and recording an identification (ID) of the second processor if the cache of the first processor stores the copy of data associated with the physical address. Other embodiments have been claimed and described.

Abstract: One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. Writes to a memory module are stored in the data cache which allows the writes to be postponed until the DRAM on the memory module is not busy.

Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.

Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data management system receives data from the host system and writes the data as data segments to the multiple storage devices. Each data segment may comprise one sector, more than one sector, or a portion of a sector, depending on the embodiment. The data segments are transferred to and from the multiple storage devices in parallel fashion while the data in each data segment is transferred to its corresponding data storage device sequentially. The data management system reassembles data segments received from the data storage devices and sends the data to the host system.

Abstract: A data storage system includes a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data addressing is distributed amongst channels to improve system performance and durability. In one embodiment, each channel has an address translation table or address map which is utilized to gain performance improvement during data transfer or erasure, and an increase of the device's useful life span.

Abstract: A controller in local site can process a request for storage resources from requestors like host computers, backup servers and tier manager. The controller checks own resource information including information about storage resources in the local site, according to requirements based on the request. The controller also asks other controllers in remote sites to check storage resources in each remote site. The controller in the local site collects the answers about available storage resources (including resources in the local site) under the requirements and selects storage resources to be used. Then the controller in the local site notifies the selected storage resources to the requester. Release of storage resource can also be performed with communication between controllers. Computers and backup servers can utilize these functions provided by the controllers to obtain and release the storage resources.

Abstract: A process of data storage utilizing a data management system that transfers data between a host system and multiple storage devices through multiple channels. The data management system receives data from the host system and writes the data as data segments to the multiple storage devices. Each data segment may comprise one sector, more than one sector, or a portion of a sector, depending on the embodiment. The data segments are transferred to and from the multiple storage devices in parallel fashion while the data in each data segment is transferred to its corresponding data storage device sequentially. The data management system reassembles data segments received from the data storage devices and sends the data to the host system.