Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluster includes mechanisms for instructing probed remote clusters to respond to the request cluster instead of to the home cluster. The home cluster can also include mechanisms for reducing the number of probes sent to remote clusters. Techniques are also included for providing the requesting cluster with information to determine the number of responses to be transmitted to the requesting cluster as a result of the reduction in the number of probes sent at the home cluster.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g.

Abstract: A control method for controlling a recording/reproducing apparatus having plural storage units and an equipment to which the recording/reproducing apparatus is connected. The recording/reproducing apparatus has first and second storage units in which data and management data are stored. The equipment, to which is connected the recording/reproducing apparatus, has a third storage unit in which are stored the data and the management data. It is detected whether the equipment to be connected to the recording/reproducing apparatus has been connected to the recording/reproducing apparatus. If such connection is detected, the management data are read out from the first and second storage units. Based on the read-out management data and the management data stored in the third storage unit of the equipment, connected to the recording/reproducing apparatus, new management data, supervising the first to third storage units as one storage unit, is generated.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.

Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A method and a system for processor nodes configurable to operate in various distributed shared memory topologies. The processor node may be coupled to a first local memory. The first processor node may include a first local arbiter, which may be configured to perform one or more of a memory node decode or a coherency check on the first local memory. The processor node may also include a switch coupled to the first local arbiter for enabling and/or disabling the first local arbiter. Thus one or more processor nodes may be coupled together in various distributed shared memory configurations, depending on the configuration of their respective switches.

Abstract: A system comprises a first node that provides a broadcast request for data. The first node receives a read conflict response to the broadcast request from the first node. The read conflict response indicates that a second node has a pending broadcast read request for the data. A third node provides the requested data to the first node in response to the broadcast request from the first node. The first node fills the data provided by the third node in a cache associated with the first node.

Abstract: Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.

Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.

Abstract: A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.

Abstract: A node in a multi-node system includes a memory, an active device that includes a cache, an interface that sends and receives coherency messages on an inter-node network coupling the node to another node, and an address network that communicates address packets between the devices in the node. In response to receiving a coherency message from the other node requesting an access right to a coherency unit, the interface sends an address packet on the address network. The address packet is a first type of address packet if the coherency unit is in the modified global access state in the node and a second type of address packet otherwise. If the active device is the owner of the coherency unit, the active device responds to the first type of address packet and ignores the second type of address packet.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A storage system which manages a plurality of storage control apparatus in an integrated manner is provided. An I/O request issued by a host apparatus to a second storage control apparatus is forwarded to the second storage control apparatus through a first storage control apparatus. The first storage control apparatus has management information for the second storage control apparatus, allowing a pair comprising a logical device controlled by the first storage control apparatus and a logical device controlled by the second storage control apparatus to be created. In addition, the first storage control apparatus is capable of controlling the second storage control apparatus.

Abstract: A method and system is provided for capturing data from a population of device users with network access. A requestor may request a data capture. The requested data may include, for example, a geographical location or a desired subject matter. Devices capable of providing the requested data capture are identified and requested to provide the data. The devices may be identified based on location, capabilities, availability, etc. The data capture from the identified federated devices may be sent to the requestor. The data may be exchanged for a fee, determined by prearrangement or via an economic model such as a competitive auction.

Abstract: In one embodiment, the present invention includes a method for receiving a first memory request from a first caching agent associated with a first processor, in a home agent associated with a memory, directing the first memory request to a writeback queue of the home agent if the first memory request is a writeback request and otherwise directing the first memory request to a second queue of the home agent. In this way, circular dependencies may be avoided. Other embodiments are described and claimed.

Abstract: In general, embodiments of the invention relate to reading data from and writing data to a storage system. Specifically, embodiments of the invention relate to a read only mode for a portion of a storage system. In one embodiment, a selective read-only mode for a portion of a storage system is implemented by monitoring a condition that may affect a subset of persistent storage in a storage system, by detecting the condition, by entering a read-only mode for the subset, and by enforcing a policy of processing write requests and read requests to the storage system, which includes processing the write requests without modifying user data stored on the subset and processing the read requests, including requests for user data stored on the subset.

Abstract: The present invention discloses a modified computer architecture (50, 71, 72) which enables an applications program (50) to be run simultaneously on a plurality of computers (M1, . . . Mn). Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied locally. During initial program loading (75), or similar, instructions which result in memory being re-written or manipulated are identified (92). Additional instructions are inserted (103) to cause the equivalent memory locations at all computers to be updated.

Abstract: A shared memory control method parallel processes ordered access requests (AccReq) for a shared memory received from processors or threads. The method includes dividing the shared memory into memory areas, receiving the ordered AccReq for each memory area, executing the AccReq when a described order number (OrdNum) described in the AccReq matches an OrdNum expected for access, increasing or decreasing the expected OrdNum expected by the memory area to be accessed by a predetermined number when the type of the AccReq is “READ ONLY” or “WRITE” or “NO OPERATION”, saving the AccReq into a queue independently assigned to each memory area when the described OrdNum in the AccReq does not match the expected OrdNum, and sequentially fetching the AccReq from the queue and executing the AccReq as long as a described OrdNum described in the AccReq preserved in the queue matches an expected OrdNum corresponding to the queue.

Abstract: The present invention discloses a multi-channel memory storage device and control method thereof. The method arranges physical locations for a file's data stored in the storage device. The storage device includes a plurality of memories. The major feature of the method is to decide whether the data is written to a single memory or parallel memories according to the size of the data.

Abstract: A method and system for managing files in a server environment includes launching a plurality of Virtual Private Servers (VPSs) in a computing system; copying a content of a file of a VPS to a shared space; providing access to the file copy in the shared space when the VPS attempts to access the file; detecting files with the same content in other VPSs; and providing access to the file copy in the shared space from the other VPSs when they attempt to access their files with the identical content.

Abstract: A data processing system in the form of an integrated circuit 2 includes a general purpose programmable processor 4 and a hardware accelerator 6. A shared memory management unit 10 provides memory management operations on behalf of both of the processor core 4 and the hardware accelerator 6. The processor 4 and the hardware accelerator 6 share a memory system 8. A first communication channel 12 between the processor 4 and the hardware accelerator 6 communicates at least control signals therebetween. A second communication channel 14 coupling the hardware accelerator 6 and the memory system 8 allows the hardware accelerator 6 to perform its own data access operations upon the memory system 8.

Abstract: The storage control device of the present invention uses a temporary volume to move data rapidly between volume groups. The storage control device forms a plurality of volume groups by grouping volumes of the same performance. At least one or more temporary volumes are each pre-provided in the respective volume groups. The control section calculates and manages the priority levels of the respective data. The data with the highest priority level in the lower volume group are copied beforehand to the temporary volume in the upper volume group at a time when the data are not being accessed by the host. As a result, data can be moved rapidly when data migration is executed and so forth.

Abstract: Systems, methods, and computer program products are presented for transiently clearing a reservation on a device, where the reservation belongs to a host that owns the device and the reservation blocks a host that does not own the device from performing an operation with the device. The reservation is cleared transiently by the host that does not own the device. While the reservation is cleared, the operation is performed with the device using the host that does not own the device.

Abstract: A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Abstract: Provided are a method, system, and program for transferring data between an initiator node and target node. A request is received conforming to a first data transfer protocol at the initiator node to transmit to the target node. A reference to a memory location is obtained to use to transfer the request to the target node. At least one function is called that executes in a user address space of the initiator node, wherein the initiator node includes a kernel address space and the user address space. The at least one function executing in the user address space interfaces with an adaptor to transmit the request and reference to the memory location to the target node using a second data transfer protocol.

Abstract: A monitoring process for a NUMA system collects data from multiple monitored threads executing in different nodes of the system. The monitoring process executes on different processors in different nodes. The monitoring process intelligently collects data from monitored threads according to the node it which it is executing to reduce the proportion of inter-node data accesses. Preferably, the monitoring process has the capability to specify a node to which it should be dispatched next to the dispatcher, and traverses the nodes while collecting data from threads associated with the node in which the monitor is currently executing. By intelligently associating the data collection with the node of the monitoring process, the frequency of inter-node data accesses for purposes of collecting data by the monitoring process is reduced, increasing execution efficiency.

Abstract: An ascending ordered list without duplication is generated based on a value list divided and held by multiple memory modules. An information processing system has multiple PMMs, and the PMMs are interconnected via a data transmission path. The memory in the PMM has a list of values, which are ordered in ascending or descending order without duplication. The PMM determines, for a storage value in the value list (LOCAL_LIST) held by the PMM, whether or not the memory module is a representative module representing one or more memory modules holding the storage value based on rankings determined for the individual PMMs and the value lists received from the other PMMs, and if the memory module is determined to be the representative module (RV-0 . . . RV-7), associates to the storage value and stores information indicating that the memory module is the representative module.

Abstract: In certain aspects, the invention features a system and method for caching results, including receiving a job for computation by a distributed computing system having one or more node computing devices in communication with a cache, processing, on one of the node computing devices, the job to create an intermediate result for storage in the cache, wherein the intermediate result includes data wherein a time required to obtain the data by computation or retrieval from a data storage external to the distributed computer system is at least marginally greater than that of retrieving the intermediate result from the cache. In accordance with such aspects, the system and method further includes storing the intermediate result in the cache, and accessing the cache by presenting a lookup function to the cache, wherein the lookup function includes a key and a compute function configured to produce the intermediate result.

Abstract: A computer cluster for providing hosting services includes a plurality of nodes, and a control center coordinating activity of the nodes. Each node includes a plurality of virtual environments such that each virtual environment responds to user requests and appears to the user as having its own operating system. Multiple virtual environments running on the same node share the same host operating system of the node.

Abstract: A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the hard disk drive. Further, with the addition of an MP3 player controller into the device, the device can function as a stand alone audio playback device, even while the PC is turned off or is in a hibernating mode. Finally with the MP3 player controller, the device can access additional audio data stored on the hard drive, again with the PC in an off mode or a hibernating mode. Finally, the device can function to operate the disk drive, even while the PC is off or is in a hibernating mode, and control USB ports attached thereto.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A system and method for a communication terminal to manage memory and maintain a current application version for multiple applications are provided. The system and method provide for managing memory in a communication terminal coupled to a server device enabling the communication terminal to provide memory capacity for storing in a memory and executing on the communication terminal a plurality of applications downloaded from the server device. Prior to downloading an application, the communication terminal determines an amount of memory capacity required by an application client to be downloaded from the server device. The communication terminal then attempts to allocate the memory capacity.

Abstract: A system in accordance with an embodiment of the invention provides Quality of Service (QoS) for Storage Access. Such QoS is partially enabled in one embodiment by the automatic pooling of storage devices and provisioning virtual targets from those pools. QoS is enforced in one embodiment by keeping the bandwidth for each connection within a specified range, and particularly, by controlling the number of allowed concurrent requests from an initiator. Load balancing is also provided in one embodiment, improving response times for requests, further easing the ability to provide QoS.

Abstract: A collision detection and data synchronization mechanism operates to expand the speed and capability of distributed applications. The execution environment employs collision detection and data synchronization to distribute data objects to appropriate network nodes to support local processing. The collision detection and data synchronization mechanism defines the set of processes and algorithms used to track distributed data objects and to manage changes to the distributed objects throughout a network of intelligent computing devices. Data and code are distributed to local computing devices necessitating tracking and synchronizing updates. The system and method ensures that data updates received during the course of a local transaction do not unwillingly affect the results of other transactions by notifying the local computing devices of changes to the data that are subject of the transaction.

Abstract: A shared memory device capable of simplifying wiring to a memory, preventing a decline of performance due to an increase of the area and long wiring, and improving extensibility of scalability of the system is provided: wherein the device has a plurality of memory systems each including a memory macro, a processor, and a memory control unit for controlling an access to a memory macro; wherein the memory control unit of each of the memory systems transfers information between the processor and memory macro and transfers information with a memory control unit of a different memory system; the memory macro of each of the memory systems has a memory interface capable of transferring data; and the memory interfaces of the memory macros of different memory systems are mutually connected.

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: In one embodiment, a node comprises at least one memory control unit configured to couple to an industry standard memory interface for coupling to a memory; and at least one coherence unit configured to transmit and receive coherence messages to and from other nodes to maintain coherent memory among the nodes. The coherence messages are conveyed on a second interface to which the coherence unit is coupled, wherein the second interface includes at least a physical layer as specified by the industry standard memory interface.

Abstract: A system may include multiple nodes, and each node may include a processing subsystem and an interface that are coupled by an address network and a data network. The nodes' interfaces may communicate over an inter-node network. Each processing subsystem may transition an access right to a coherency unit in response to a data packet on the data network and transition an ownership responsibility for the coherency unit in response to an address packet on the address network such that the access right transitions at a different time than the ownership responsibility transitions. An interface within a node may be configured to delay providing a data packet on the node's data network until the interface receives an indication that shared copies of the coherency unit in other nodes have been invalidated.

Abstract: Managing a computer system's multiple processors as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Abstract: A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

Abstract: In some embodiments a method of addressing advanced memory buffers identifies whether a dual inline memory module includes more than one advanced memory buffer. If the dual inline memory module includes more than one advanced memory buffer, then each of the advanced memory buffers of the dual inline memory module is addressed separately, and an address is computed for a next dual inline memory module. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention provides a computer system including a first memory and a second memory, where the first memory is substantially faster than the second memory. A method includes steps of: inspecting a request queue for block requests from a plurality of concurrent calling processes, the request queue including a plurality of block requests not yet processed by any of the plurality of concurrent calling processes; retrieving one of the plurality of block requests, wherein each block is accessed at most once by each calling process; determining whether the retrieved block request can be fulfilled from the first memory; and returning the retrieved block to the calling process whose state indicates that the block is needed if the retrieved block request can be fulfilled from the first memory.

Abstract: A storage system comprises a plurality of storage nodes and a controller coupling unit interconnecting controllers within the storage nodes. A memory in the controller has a plurality of shared memory areas each associated with a combination of one CPU core with one logical unit controller. When a network controller of a first storage node receives a host command addressed to a logical unit of a second storage node, the CPU core of the first storage node stores the host command in the shared memory area associated with the logical unit controller of the second storage node. The logical unit controller of the second storage node acquires the stored host command in the shared memory area via the controller coupling unit.

Abstract: Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.

Abstract: Daisy-chain memory configuration and usage is disclosed. According to one configuration, a memory system includes a controller and corresponding string of multiple successive memory devices coupled in a daisy-chain manner. The controller communicates commands over the serial control link to configure a first memory device to write a block of data to a second memory device in the chain. For example, the controller initiates copying a block of data by communicating over the daisy-chain control link to configure a first memory device of the multiple memory devices to be a source for outputting data, communicating over the daisy-chain control link to configure a second memory device to be a destination for receiving data, and communicating over the daisy-chain control link to initiate a transfer of the data from the first memory device to the second memory device.

Abstract: A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.