Abstract: Electronic circuit chips which include cryptography functions are arranged in multichip configurations through the utilization of a shared external memory. Security of the chips is preserved via a handshaking protocol which permits each chip to access limited portions of the memory as defined in a way that preserves the same high security level as the tamper proof chips themselves. The chips may be operated to work on different tasks or to work on the same task thus providing a mechanism for trading off speed versus redundancy where desired.

Abstract: A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an mth page of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

Abstract: For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an access to the variable that occurs outside any STM-defined critical region system by starting a hardware based transactional memory based transaction, within the hardware based transactional memory based transaction, checking if the variable is currently owned by a STM transaction, checking if the variable is currently owned by a STM transaction; if the variable is not currently owned by a STM transaction, performing the access and then committing the hardware based transactional memory transaction; and if the variable is currently owned by a STM transaction, performing a responsive action.

Abstract: An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.

Abstract: A method and system for generating a web log that includes transaction entries from transaction queues of one or more cores of a multi-core system. A transaction queue is maintained for each core so that either a packet engine or web logging client executing on the core can write transaction entries to the transaction queue. In some embodiments, a timestamp value obtained from a synchronized timestamp variable can be assigned to the transaction entries. When a new transaction entry is added to the transaction queue, the earliest transaction entry is removed from the transaction queue and added to a heap. Periodically the earliest entry in the heap is removed from the heap and written to a web log. When an entry is removed from the heap, the earliest entry in a transaction queue corresponding to the removed entry is removed from the transaction queue and added to the heap.

Abstract: One disclosed embodiment may comprise a system that includes a home node that provides a transaction reference to a requester in response to a request from the requester. The requester provides an acknowledgement message to the home node in response to the transaction reference, the transaction reference enabling the requester to determine an order of requests at the home node relative to the request from the requester.

Abstract: Provided are a method, system, and article of manufacture for providing a process exclusive access to a page including a memory address to which a lock is granted to the process. A request is received for a memory address in a memory device from a requesting process. A lock is granted to the requested memory address to the requesting process. The requesting process is provided exclusive access to a page including the requested memory address for a page access time period. The exclusive access to the page provided to the requesting process is released in response to an expiration of the page access time period.

Abstract: Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, or a punch out bit field. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level.

Abstract: A method is provided for detecting viruses. According to the method, data is stored in a journal area of memory before changes embodied in the data are written to virtual memory. At least a first portion of the data in the journal area of memory is scanned for viruses. In some embodiments, a second portion of data that immediately precedes and/or immediately follows data to which the first portion of the data pertains is scanned for viruses. Preferably, the virtual memory includes a persistent storage device. Also provided is a system that includes a processor, a memory that includes virtual memory and a journal storage area, and a virus scanner controlled by the processor. The virus scanner scans the journal storage area for viruses.

Abstract: In one embodiment, a solution is provided wherein a lock manager is kept moving among multiple cores or processors in a multi-core or multi-processor environment. By “hopping” the lock manager from processor to processor, a bottleneck at any of the processors is prevented. The frequency of movement may be based on, for example, a counter that counts the number of input/outputs handled by the lock manager and moves the lock manager to a different processor once a determined threshold is met. In another embodiment of the present invention, the frequency of the movement between processors may be based on a time that counts the amount of time the lock manager has been operating on the processor and moves the lock manager to a different processor once a predetermined time is reached.

Abstract: A data processing system with memory access comprising an operating system for supporting processes, such that the process are associated with one or more resources and the operating system being arranged to police the accessing by processes of resources so as to inhibit a process from accessing resources with which it is not associated. Part of this system is an interface for interfacing between each process and the operating system and a memory for storing state information for at least one process. The interface may be arranged to analyze instructions from the processes to the operating system, and upon detecting an instruction to re-initialize a process cause state information corresponding to that pre-existing state information to be stored in the memory as state information for the re-initialized process and to be associated with the resource.

Abstract: A method, apparatus, and system for accessing units of storage in at least one logical unit by processing I/O requests directed to the logical units using a LUN queue and an operation-type queue. By using the queues to process the I/O requests, the requests can be processed without address collisions.

Abstract: Enabling an off-host computer to migrate data of a data volume. In one embodiment, the off-host computer copies data contents of n data blocks of a first data volume to n data blocks, respectively, of a second data volume. A host computer is capable of modifying data contents of a first plurality of data blocks of the n data blocks of the first data volume after the off-host computer begins copying data contents of the n data blocks of the first data volume to the n data blocks, respectively, of the second data volume.

Abstract: A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.

Abstract: Transactional memory (TM) may be used in conjunction with various synchronization mechanisms, such as that copy a current version of an object, update the copy, and then cause the copy to become current atomically by changing a “current version” indicator. Software operations to modify an object may first make a private copy of the object, modify the private copy, and atomically make the private copy the current version while verifying that no other software operation or transaction has concurrently updated the object. A transaction may be used to update the current copy of a collection of data “in place” and thereby avoiding the necessity to make a copy of the data being modified. If the transactional memory mechanism is unable to complete the transaction to modify the collection of data in place, a set of software operations may be used to modify the collection of data.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more command signals, a read data path control signal and one or more write data path control signals in response to an integrity protection control signal and one or more arbitration signals. The second circuit may be configured to write data to a memory and read data from the memory in response to the one or more command signals, the read data path control signal and the one or more write data path control signals. In a first mode, the data may be written and read without integrity protection. In a second mode the data may be written and read with integrity protection, and the integrity protection is written and read separately from the data.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: A hybrid Single-Compare-Single-Store (SCSS) operation may exploit best-effort hardware transactional memory (HTM) for good performance in the case that it succeeds, and may transparently resort to software-mediated transactions if the hardware transactional mechanisms fail. The SCSS operation may compare a value in a control location to a specified expected value, and if they match, may store a new value in a separate data location. The control value may include a global lock, a transaction status indicator, and/or a portion of an ownership record, in different embodiments. If another transaction in progress owns the data location, the SCSS operation may abort the other transaction or may help it complete by copying the other transactions' write set into its own right set before acquiring ownership. A hybrid SCSS operation, which is usually nonblocking, may be applied to building software transactional memories (STMs) and/or hybrid transactional memories (HyTMs), in some embodiments.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: A portable, biometrically-secured device for facilitating various different types of in-person and online transactions. For example, the portable, biometrically-secured device can be used to safely perform in-person financial transactions, such as credit card transactions, in which the user's identity is biometrically authenticated. The portable, biometrically-secured device can also be used for performing biometrically-secured online transactions. For example, the portable, biometrically-secured device can be used to create a secure platform from which to make the online transactions by loading a secure operating system from the device to a host computer's volatile memory. Biometrically-secured online transactions can then be performed using the host computer. In one embodiment, the portable, biometrically-secured device facilitates online financial transactions that can be performed without transmitting a user's financial information to the online merchant.

Abstract: In one embodiment, an image forming device includes a storage device for storing data. A storage access manager is configured to coordinate access to the storage device from a plurality of client devices that communicate with the storage device using at least one uncoordinating communication protocol.

Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: A method, system and apparatus for load balancing workloads in a cluster according to an iterative greatest common divisor approach to weight normalization. A load balancing method can include computing a greatest common divisor for a set of current normalized values for raw weights corresponding to endpoints in a cluster. Each of the current normalized values can be reduced by a factor proportionate to the greatest common divisor. The reduction can produce new normalized values for the raw weights corresponding to the endpoints in the cluster. The computing and reducing steps can be repeated for the new normalized values until the new normalized values are sufficiently low. Finally, workloads can be assigned to the endpoints in the cluster according to the new normalized values which are sufficiently low.

Abstract: A proximity-based content control method “propagates” or positions content based upon “proximity” between various nodes on a network. The nodes between which the content is propagated include content libraries, servers, and clients. In one case, the relative proximities of two content servers to a particular client or group of clients determines which of these servers serves client requests. In another case, the method employs anticipatory loading of content from a library to a server based upon the server's proximity to a given client-base. Yet another application involves adding or removing server capacity to a network based upon proximity to clients. Another application applies proximity affects to cache release algorithms. A “content control system” calculates proximity dynamically and automatically decides whether to move content based upon the proximity calculation.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: A system for managing data in multiple data processing devices using common data paths. Embodiments of the invention comprise a first data processing system comprising a cacheable coherent memory space; and a second data processing system communicatively coupled to the first data processing system with the second data processing system comprising at least one bridge, wherein the bridge is operable to perform an uncacheable remote access to the cacheable coherent memory space of the first data processing system. In some embodiments, the access performed by the bridge comprises a data write to the memory of the first data processing system for incorporation into the cacheable coherent memory space of the first data system. In other embodiments, the access performed by the bridge comprises a data read from the cacheable coherent memory space of the first data system.

Abstract: Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions that include determining by a thread executing on a virtual processor executing in a time slice on a physical processor whether an expected lock time for a critical section of the thread exceeds a remaining entitlement of the virtual processor in the time slice and deferring acquisition of a lock if the expected lock time exceeds the remaining entitlement.

Abstract: Disclosed is an information processing apparatus that has an update procedure semaphore, and a generation management information as management information of a shared data area that requires exclusion control. The generation management information specifies one item of generation information of the shared data area. As generation information provided for every generation, the apparatus has a reference-count measuring counter, a semaphore for updating generation information, a pointer for pointing to old generation information, and a pointer for pointing to the substance of the shared data area. In a case where the latest shared data is updated, a duplicate of the latest shared data area is created, new generation information corresponding to the duplicated shared data area is generated, data in the duplicated shared data area is updated and generation information, which corresponds to the shared data area after the updating thereof, is registered as the latest generation information.

Abstract: A method, system, and program product for reserving resources in a networked environment, e.g. a storage area network. A resource is some object that a user must use or change to complete a task. When a user plans a task, the user selects some high-level resources and properties to reserve and a Reservation Service embodiment creates reservations for them. Accordingly, the method system and program product embodiments overcome inefficiencies in reserving resources in a data storage environment while still allowing such reservations to occur. The method includes selectively reserving properties for resources from more than one available choice.

Abstract: In an IC card, an operating system manages the access order of each channel for each file using a channel management table. An application controls access to each file based on the access order managed in the channel management table. The channel management table stores, as an access order, an order that each logical channel has set a file in a current state. If current setting by a specific logical channel is canceled, a table updating function deletes the logical channel from the channel management table and moves up the access order of each logical channel next to the deleted logical channel.

Abstract: The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.

Abstract: A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.

Abstract: Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device. Accordingly, the memory access device enables multiple processors, which are to simultaneously access a specific memory, to perform other operations during the standby time taken to access the specific memory.

Abstract: A technique for efficiently boosting the priority of a preemptable data reader in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no longer capable of referencing the data elements. Upon the reader being subject to preemption or blocking, it is determined whether the reader is in a read-side critical section referencing any of the shared data elements. If it is, the reader's priority is boosted in order to expedite completion of the critical section. The reader's priority is subsequently decreased after the critical section has completed. In this way, delays in grace period processing due to reader preemption within the critical section, which can result in an out-of-memory condition, can be minimized efficiently with minimal processing overhead.

Abstract: A method of arbitrating access to a storage medium that is shared by M first computers operating on a Windows™ operating comprising (1) determining if the SCSI PR-flag has been set; (2) if yes, preventing the N second computers from writing to the storage medium; and (3) setting the SCSI MC-flag for each of said M first computers after one of the second computers writes to the storage medium to notify the M first computers that the contents of the storage medium may have changed.

Abstract: Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB bridge, has any of a plurality of command bus widths. A burst command is issued via a command bus, having a command bus width of the plurality, from the master device for the slave PLB bridge. The burst command is converted to a native bus width of the slave processor logic block if the command bus width is not equal to the native bus width. The burst command is translated if execution of the burst command will exceed the data size threshold and passed without the translating if the execution of the burst command will not exceed the data size threshold.

Abstract: One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.

Abstract: A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.

Abstract: An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.

Abstract: In a cache coherency protocol a re-snoop may be utilized to resolve a data request conflict condition. The re-snoop may avoid a conflict resolution phase, which may reduce system inefficiencies.

Abstract: According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.

Abstract: A system and method for nearly in-band search indexing. A network switch (or other intermediate network device) is configured to provide port mirroring so that data access requests directed to a storage system are forwarded to both the storage system and to a search appliance. The search appliance collects index information from the received data access requests to update a search index. As the search appliance is nearly in-band, i.e., not directly in-line of the data access request path, no increase of latency occurs for processing data access requests by the storage system.

Abstract: A multiple computer system with hybrid replicated shared memory is disclosed. The local memory (10, 20, . . . 80) of each of the multiple computers M1, M2, . . . Mn is partitioned into a first part (11, 21, . . . 81) and a second part (12, 22, . . . 82). Each of the first parts are identical and each of the second parts are independent. The total memory available to the system is the first memory part plus n times the second memory part, n being the total number of application running multiple computers.

Abstract: A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.

Abstract: It is possible to control the data transfer between a proxy server apparatus and an application server that is connected to the proxy server apparatus. A value added service control command is added to an request message and/or the response data. In accordance with the value added service control command included in the request message, a first proxy server 1a controls whether it relays this request message directly to a destination and it relays this request message to the destination after transferring this request message to an application server 7 and applying the value added service. Further, based on the value added service control command which is included in the response data, the first proxy server 1a controls whether it relays this response data directly to a destination or it relays this response data to the destination after transferring this response data to the application server 7 and applying the value added service.