Abstract: A state machine is provided with outputs that have programmable delays that enable the state machine to be compatible with a number of different devices. The state machine uses shift register look up tables (SRLs) to provide variable output delays. The state machine can be provided in the BRAM of an FPGA, and can be used to provide control logic in a multi-port memory controller (MPMC). The MPMC with such a state machine can then connect to multiple different types of memory devices either simultaneously or separately.

Abstract: It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.

Abstract: Techniques are provided for performing multi-pass erase. An erase command is received at a storage area network (SAN) switch in a storage area network. The erase command is associated with a block of data on a target device. A virtual initiator is determined for performing the erase command on the block of data. Multiple bit patterns are generated using a multi-pass erase algorithm. The multiple bit patterns are generated for writing over the block of data on the target device. Repeated writes are performed over the block of data using the bit patterns. The block of data is repeatedly overwritten to remove remanence of the block of data on the target device.

Abstract: By exploiting an early release facility that may be provided by certain transactional memory designs, we allow for transaction software constructs that wait on removal (or satisfaction) of a condition that would otherwise result in transaction abort. Absent exploitation of such a such a facility, the act of checking the condition would typically introduce a corresponding location into the read set of the transaction, and a subsequent modification of that location that removed (or satisfied) the condition, would result in abortion of the blocked transaction. By exploiting an early release facility such as described herein, a transaction may release the location (or locations) corresponding the condition, retry, and once the transient condition is removed (or satisfied), complete and commit. In this way, computation effort may be conserved while still employing a conceptually simple and convenient coordination facility.

Abstract: A memory access apparatus for accessing a first memory and a second memory, includes: an address outputting unit configured to output a read address to at least one of the first and the second memories; an access request outputting unit configured to output a read request to at least one of the first and the second memories; a data information outputting unit configured to output an information on the data size, and an information on the address, of the read data; and a read data outputting unit configured to generate the read data to be output, from the data output from at least one of the first and the second memories in response to the read address and the read request.

Abstract: Techniques for associating geographic-related information with objects are described. In one implementation, a search is conducted on a keyword string of one or more keywords descriptive or otherwise representative of a geographically-relevant object. If a location is identified, geographic-related semantic information of the location is associated with the geographically-relevant object. In some cases, multiple possible locations may be identified as a result of searching the keyword string. If multiple locations are identified, a probable location is determined and then geographic-related semantic information of the probable location is associated with the geographically-relevant object described by the keyword string.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: A migration framework provides for the migration of services in a cluster. A migratable target contains a list of servers in the cluster capable of hosting a migratable service. A migration manager can migrate the service between servers in the migratable target, and can activate an instance of the service on the selected host server. The migration manager ensures that only one active instance of the service exists in the cluster. A service stub can serve a user request on servers in the migration target, such as by order of preference, until the user request is served on the server hosting the active instance. A lease manager can assign a lease period to determine how long a server hosts an active instance.

Abstract: The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

Abstract: A method of accessing a shared data structure in parallel by multiple threads in a parallel application program is disclosed, in which a lock of the shared data structure is granted to one thread of the multiple threads, an operation of the thread which acquires the lock is performed on the shared data structure, then an operation of each thread of the multiple threads which does not acquire the lock is buffered, and finally the buffered operations are performed on the shared data structure when another thread of the multiple threads subsequently acquires the lock. By using this method, the operations of other threads which do not acquire the lock of the shared data structure can be buffered automatically when the shared data structure is locked by one thread, and all the buffered operations can be performed when another thread acquires the lock.

Abstract: A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently. Additionally, the caching estimator process computes the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads. As a result, the caching estimator applies the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.

Abstract: A method and apparatus are provided for detecting data races that overcome the limitations of the prior art. In some embodiments, this is accomplished by detecting a first access to an object, determining whether the first access is associated with a suspicious pattern, automatically refining a pattern detection granularity from the object to a memory location within the object if a determination is made that the first access is associated with the suspicious pattern, and reporting the data race if a second access associated with the suspicious pattern occurs at the memory location after the pattern detection granularity is refined.

Abstract: Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.

Abstract: Network servers in a cluster share the same network protocol address for incoming client requests, and in a data link layer protocol a reply of a client to a request from a server is returned to this same server. For example: (1) ports of the servers are clustered into one single network channel used for incoming and outgoing requests to and from the servers; or (2) ports of the servers are clustered into one single network channel used for incoming requests to the servers and a separate port of each of the servers is used for outgoing requests from each of the servers; or (3) logical ports of the servers are clustered into one network channel used for requests to the servers and a separate logical port of each of the servers is used for outgoing requests from each of the servers.

Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: Techniques and systems for dynamic binning, in which a stream of requests to access a memory is sorted into a reordered stream that enables efficient access of the memory. A page stream sorter can group requests to access a memory in a manner that results in some “locality” in the stream of requests issued from the page stream sorter to memory, such that as few pages as possible in the same bank are accessed and/or a number of page switches needed is minimized.

Abstract: Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

Abstract: A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A technique for realtime-safe detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A per-processor read/write lock is established for each of one or more processors. When reading a shared data element at a processor, the processor's read/write lock is acquired for reading, the shared data element is referenced, and the read/write lock that was acquired for reading is released. When starting a new grace period, all of the read/write locks are acquired for writing, a new grace period is started, and all of the read/write locks are released.

Abstract: A data processor that allows a CPU to access an external memory in an interval between data accesses from a DSP having a variable data length. In a case where a 24-bit mode is set, when a determination section determines that the DSP is accessing the external memory, a control section commands to place an access from the CPU to the external memory in a wait state. In a case where a 16-bit mode is set, the control section commands an address-data switching section, allowing the CPU to access the external memory by utilizing a third bus cycle, which is free.

Abstract: A system for high-speed access and recording includes a demodulator, a buffer memory, and a hard disk. During a write cycle, a content stream is stored in buffer memory and thereafter transferred to the demodulator. When the buffer memory reaches its storage capacity, its contents are transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. The hard disk further includes includes a high-speed zone and a random-access zone, which are configured to operate in a high-speed mode, a random-access mode, and a buffer-cleaning mode.

Abstract: Methods and apparatus, including computer program products, for workload balancing in environments with multiple clusters of servers. A process for sharing resources from a pool of servers among a first cluster of servers and a second cluster of servers includes determining a current workload of the first cluster and determining a current workload of the second cluster. The process calculates a combined workload of the first and second clusters, and allocates a first number of servers from the pool to the first cluster, the first number equal to a product of a total number of servers in the pool and the first server's workload divided by the combined workload.

Abstract: An interactive client-server authentication system and method are based on Random Partial Pattern Recognition algorithm (RPPR). In RPPR, an ordered set of data fields is stored for a client to be authenticated in secure memory. An authentication server presents a clue to the client via a communication medium, such positions in the ordered set of a random subset of data fields from the ordered set. The client enters input data in multiple fields according to the clue, and the server accepts the input data from the client via a data communication medium. The input data corresponds to the field contents for the data fields at the identified positions of the random subset of data fields. The server then determines whether the input data matches the field contents of corresponding data fields in a random subset.

Abstract: A distributed storage architecture and tiered caching system are employed in a video-on-demand or streaming media application. An illustrative embodiment of a distributed storage architecture, based on block map caching and virtual file system stackable file system modules, includes a controller, a first computer and a second computer, first and second switches, and a storage device. The first computer includes a local file system and uses this to store asset files in the local file system on the first storage device. The first computer employs a process to create a block map for each asset file, the block map including information concerning boundaries where an asset file is stored on the first storage device.

Abstract: A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

Abstract: A shared storage area of a plurality of storage virtualization apparatuses connected to a host apparatus and a storage subsystem stores device configuration information expressing a logical device configuration in the storage virtualization apparatuses. The logical device configuration is a relationship between an external storage device in the storage subsystem, a virtual device serving as a virtualized storage space of a storage resource provided by one or more of the external storage devices, and one or more logical storage devices constituting an internal storage device in the storage virtualization apparatus. A newly connected storage virtualization apparatus reads the device configuration information from the shared storage area, and writes the read device configuration information into a configuration information storage area of the storage virtualization apparatus.

Abstract: A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame al song as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.

Abstract: In a device in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. In a case that the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.

Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Abstract: A compare, swap and store facility is provided that does not require external serialization. A compare and swap operation is performed using an interlocked update operation. If the comparison indicates equality, a store operation is performed. The compare, swap and store operations are performed as a single unit of operation.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.

Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.

Abstract: Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.

Abstract: Enabling secure and efficient marshaling, utilization, and releasing of handles in either of an operating system or runtime environment includes wrapping a handle with a counter to tabulate a number of threads using currently using the handle. Thus, handle administration is implemented to circumvent potential security risks, avoid correctness problems, and foster more efficient handle releasing.

Abstract: A method for transferring data between programming agents and memory resources. The method includes transferring data between a processing agent and a memory resource, designating the memory resource for pushing the data to the processing agent via a push bus having a plurality of sources that arbitrate use of the push bus, and designating the memory resource for receiving the data from the processing agent via a pull bus having a plurality of destinations that arbitrate use of the pull bus.

Abstract: A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating that one of the destinations is available to accept a forward message; simultaneously sending a forward message to each available destination; simultaneously receiving, after a predetermined period of time, a plurality of reverse messages from the destinations, each reverse message corresponding to one of the forward messages simultaneously sent to an available destination; and serially sending the reverse messages to the source.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: Secrecy of printed matter is raised and charges for a storing area are more accurately charged. According to the invention, a printing apparatus is instructed so as to store print data corresponding to a print request into one of a plurality of storing areas. The print data is transmitted to the printing apparatus. The user is notified of authentication information corresponding to the print data stored in one of the plurality of storing areas.

Abstract: A data processing apparatus includes a data processing section that issues a plurality of data transfer requests simultaneously; an internal memory provided inside a circuit including the data processing section; an internal memory control section that performs an access control for the internal memory; an external memory that exchanges data with the data processing section via an external bus; an external memory control section that performs an access control for the external memory; and a memory selecting section that assigns to at least one of the internal memory and the external memory a data transfer request from the data processing section.

Abstract: Techniques are provided for performing changes to a resource governed by a locking mechanism. An entity (such as a server instance in a database system cluster) requests permission to modify the resource. In response to the request, the entity receives a first lock on the resource, which grants permission to perform the change to the resource without making the change permanent. After receiving the first lock, the entity performs the change to a copy of the resource that resides in shared memory without making another copy of the resource. After performing the change and until receiving permission to make the change permanent, the entity prevents the change to the resource from becoming permanent. After performing the change, the entity receives a second lock on the resource, which grants the entity permission to make the change permanent. After receiving the second lock, the entity ceases to prevent the change to the resource from becoming permanent.

Abstract: The present invention discloses a modified computer architecture (50, 71, 72) which enables an applications program (50) to be run simultaneously on a plurality of computers (M1, . . . Mn). Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied locally. During initial program loading (75), or similar, instructions which result in the application program (50) acquiring (or releasing) a lock on a particular asset (50A, 50X-50Y) (synchronization) are identified. Additional instructions are inserted (162, 163) to result in a modified synchronization routine with which all computers are updated.

Abstract: A system and method manages lock state information in a distributed file system. A meta-data volume includes a lock state database which is a comprehensive source for lock state information about a striped volume set in the system. A plurality of data volumes includes local lock caches which contain information about locks. Lock state messaging between the meta-data volume and the data volumes is used to assign locks and to update local lock caches. The meta-data volume is configured to assigned permissive areas in the data containers accessed by clients in order to efficiently manage the lock state information.

Abstract: A system and method for multi-modal context-sensitive applications in a home network are provided. The system includes an input processing agent classifying inputs from a predetermined input device based on at least one criterion selected from the group consisting of an input block, an input type, a priority, and ranking and then outputting the classified inputs; an input collaboration agent performing real-time analysis on each of the inputs fed by the input processing agent to obtain a pre-defined output action for an input type corresponding to each input based on a user's context and performing a probabilistic inference on the inputs fed by the input processing agent to obtain a possible output action based on the user's context; and an agent server obtaining an output resource, which is available in the home network and corresponds to the user's context, based on the output action obtained by the input collaboration agent.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: A method and system for managing files in a server environment includes launching a plurality of Virtual Private Servers (VPSs) in a computing system; copying a content of a file of a VPS to a shared space; providing access to the file copy in the shared space when the VPS attempts to access the file; detecting files with the same content in other VPSs; and providing access to the file copy in the shared space from the other VPSs when they attempt to access their files with the identical content.

Abstract: A multiport semiconductor memory device includes at least three port units coupled respectively to corresponding processors, a shared memory area accessed in common by the processors through the port units, and a data path control unit for controlling a data path between the shared memory area and the port units to perform a data communication between the processors through the shared memory area.

Abstract: Systems, methods, and computer program products are presented for transiently clearing a reservation on a device, where the reservation belongs to a host that owns the device and the reservation blocks a host that does not own the device from performing an operation with the device. The reservation is cleared transiently by the host that does not own the device. While the reservation is cleared, the operation is performed with the device using the host that does not own the device.

Abstract: A method is provided for communicating data in an interconnect system comprising a plurality of nodes. In one aspect, the method includes: issuing a command packet from a first node, the command packet comprising a respective header quadword and at least one respective data quadword for conveying a command to a second node, wherein the command is selected from a group comprising a direct memory access (DMA) command, an administrative write command, a memory copy write command, and a built in self test (BIST) command; receiving the command packet at the second node; issuing an acknowledgement packet from the second node, the acknowledgement packet comprising a respective header quadword for conveying an acknowledgement that the command packet has been received at the second node.