Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: A job is submitted into a first selection of resources in a grid environment from among a hierarchy of discrete sets of resources accessible in the grid environment. Discrete sets of resources may include locally accessible resources, enterprise accessible resources, capacity on demand resources, and grid resources. The performance of the first selection of resources is monitored and compared with a required performance level for the job. If the required performance level is not met, then the discrete sets of resources are queried for available resources to meet the required performance level in an order designated by said hierarchy. Available resources in a next discrete set of resource from the hierarchy of discrete sets of resources are added to a virtual organization of resources handling the job within the grid environment.

Abstract: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware.

Abstract: A system includes a cluster having a plurality of nodes wherein at least one of the nodes is a candidate node, a plurality of resource groups, a clustering mechanism executing on the cluster configured to activate a first resource group of the plurality of resource groups on the candidate node, and a resource group affinity of the plurality of resource groups, wherein the resource group affinity comprises a unidirectional association between the first resource group of the plurality of resource groups and a second resource group of the plurality of resource groups.

Abstract: A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. Furthermore, the second memory device includes a mode register set for setting an internal transfer mode. In accordance with the data transfer method according to the present invention, the transfer of data between the memory devices included in the multi-memory chip is performed through the data transmission bus shared by the memory devices. Accordingly, the multi-memory chip and the data transfer method can considerably improve data transfer rates between devices, as compared to conventional approaches in which data is transferred to the DMA controller of an external system.

Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

Abstract: A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a predictor array to predict the TSB page size. In one embodiment of the invention, the predictor array comprises two-bit saturating up-down counters that are used to enhance the accuracy of the TSB prediction. The saturating up-down counters are configured to avoid making rapid changes in the TSB prediction upon detection of an error. Multiple misses occur before the prediction output is changed. The page size specified by the predictor index is searched first. Using the technique described herein, errors are minimized because the counter leads to the correct result at least half the time.

Abstract: A transactional memory programming interface allows a thread to directly and safely access one or more shared memory locations within a transaction while maintaining control structures to manage memory accesses to those same locations by one or more other concurrent threads. Each memory location accessed by the thread is associated with an enlistment record, and each thread maintains a transaction log of its memory accesses. Within a transaction, a read operation is performed directly on the memory location, and a write operation is attempted directly on the memory location, as opposed to some intermediate buffer. The thread can detect inconsistencies between the enlistment record of a memory location and the thread's transaction log to determine whether the memory accesses within the transaction are not reliable and the transaction should be re-tried.

Abstract: Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit operating systems and applications. As software catches up to hardware, “64-bit-clean” lock-free data structures, which cannot use such techniques, are needed. We present several 64-bit-clean lock-free implementations: including load-linked/store conditional variables of arbitrary size, a FIFO queue, and a freelist. In addition to being portable to 64-bit software (or more generally full-architectural-width pointer operations), our implementations also improve on existing techniques in that they are (or can be) space-adaptive and do not require a priori knowledge of the number of threads that will access them.

Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.

Abstract: A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.

Abstract: A method, system, and storage medium for the InfiniBand™ Poll verb to support a multi-threaded environment without the use of kernel services to provide serialization for mainline Poll logic. Poll is the verb, which allows a consumer to determine which of its work requests have completed, and provides ending status. In addition to multiple concurrent threads using Poll against a single Completion Queue, Poll is serialized with Destroy Queue Pair and Destroy Completion Queue. Completion Queues are used to maintain completion status for work requests. Queue Pairs are used to submit work requests and are related to a Completion Queue at the time they are created.

Abstract: A driver for a data storage device includes an access command and a verification command. The access command initiates an access (write, erase or read) of the data storage device while allowing a calling application to continue running without having to wait for the completion of the access. The verification command queries a preceding access. If the query indicates failure of the preceding access, the verification command repeats the preceding access until the preceding access succeeds. The verification command is called by the access command before the access command initiates a new access. The verification command also is called by an application following a sequence of related access command calls. A write access command saves the data to be written in a memory separate from the data storage device, in case the verification command needs that data to repeat a failed write.

Abstract: A method and apparatus for conditional memory ordering are disclosed. The cost of memory ordering is reduced by determining circumstances in which a memory ordering operation is unnecessary and avoiding the overheads of these operations by reducing the frequency of invoking hardware memory ordering mechanisms. Hardware instructions for implementing a conditional memory ordering method and apparatus is described which may be implemented in a multiprocessor environment. The conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional register is examined and appropriate remote synchronization operations are commanded where necessary.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: An embodiment of the present invention provides a computer system including a first memory and a second memory, where the first memory is substantially faster than the second memory. A method includes steps of: inspecting a request queue for block requests from a plurality of concurrent calling processes, the request queue including a plurality of block requests not yet processed by any of the plurality of concurrent calling processes; retrieving one of the plurality of block requests, wherein each block is accessed at most once by each calling process; determining whether the retrieved block request can be fulfilled from the first memory; and returning the retrieved block to the calling process whose state indicates that the block is needed if the retrieved block request can be fulfilled from the first memory.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: An image recording apparatus includes a CPU. An image file created by the CPU is stored in a directory which is created on a hard disk and a circularly successive directory number is assigned to. When the number of image files accumulated in a latest directory reaches “450”, the CPU determines a total number of the directories, and if the total number reaches “50”, the CPU erases an oldest directory. Furthermore, when the number of the image files accumulated in the latest directory reaches “900”, the CPU creates a new directory to which the directory number succeeding to that of the latest directory is assigned. In addition, when an arbitrary directory is erased by an operation of an erasing key, the CPU assigns the successive directory number to a remaining directory in order of a creation time.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: A system and method for analyzing Java thread deadlocks. A snapshot of threads in a Java Virtual Machine is generated, producing a thread dump file which can be analyzed off line. The thread dump file is optimistically parsed to identify threads which are deadlocked. A user is provided with an interface to select filtering rules for the threads, resulting in a set of filtered threads which are candidates for being in infinite wait conditions.

Abstract: The present disclosure relates to acquiring and releasing a shared resource via a lock semaphore and, more particularly, to acquiring and releasing a shared resource via a lock semaphore utilizing a state machine.

Abstract: Access by multiple hosts, such as computers, to a data storage device by way of a network while maintaining data integrity. In one embodiment, a method for accessing the storage device includes acquiring a resource “lock” that provides exclusive access to one of the hosts at a time. In another embodiment, the file systems of a first and second host provide file system attributes stored in a storage device to provide mutually exclusive access for each host to free blocks of the device. In another embodiment, a networked system contains a first host having exclusive direct access to a storage device over a digital network. A second host requiring access to the storage device communicates with the first host by way of the digital network. File access requests generated by the second host are transferred by a redirection filter driver within the second host to the first host.

Abstract: An exemplary method detects an update to data representing a portion of a render target, according to one embodiment of the invention. Also, this method forms a copy of the portion configured to be overwritten with data for a subsequent update when that portion of the render target is selected to receive subsequent updates. Lastly, the data representing the portion can be designated as texture.

Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: Potentially identical objects (e.g., files) are located across multiple computers based on stochastic partitioning of workload. For each of a plurality of objects stored on a plurality of computers in a network, a portion of object information corresponding to the object is selected. The object information can be generated in a variety of manners (e.g., based on hashing the object, based on characteristics of the object, and so forth). Any of a variety of portions of the object information can be used (e.g., the least significant bits of the object information). A stochastic partitioning process is then used to identify which of the plurality of computers to communicate the object information to for identification of potentially identical objects on the plurality of computers.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made.

Abstract: A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: A method of and system for managing storage resources in a distributed file system is described. A lock for a storage resource is maintained on a lock-holding node. A master node that controls the lock-holding node receives a lock request from a requesting node. The lock request includes a request to obtain a lock for the storage resource, and a request to perform an action by the lock-holding node on the storage resource if the request to obtain the lock is not granted immediately.

Abstract: Resources are partitioned via a virtual partitioning system to distribute the resources over a plurality of resource servers. A virtual partition table can be kept at each of a set of resource managers handling requests for resources in tandem. When a resource is requested, a virtual partition value is calculated algorithmically, and the value is mapped to a resource component via the virtual partition table. The resource component encapsulates information indicating on which of the resource servers the resource resides and can provide a component for performing operations on the resource even though the requester does not have information about where the resource resides. The resources can be repartitioned by modifying the virtual partition table, thus allowing the addition of additional resource servers to the system while the resources remain available. Additional resource types can be added without reengineering the system.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: A multiprocessor system (40) includes a MPU subsystem (12), with master MPU (16) and shared memory (24), and a DSP/Coprocessor subsystem (14), with one or more slave DSP/Coprocessors (26). The system memory (20) is accessed by each DSP/Coprocessor subsystem (14) through a cache (28) and external memory interface (30). A verification interface (42) is used in verification mode to isolate the DSP/Coprocessor subsystem (14) from the MPU subsystem (12) and to translate system memory requests from the external memory interfaces (30) (through an arbiter (52), where multiple external memory interfaces are used) to a protocol which can be used to access the data from the shared memory (24).

Abstract: A control system for a plurality of storage systems has at least one path that is selected from a plurality of paths where one of three or more storage systems is a start point storage system and another one thereof is an end point storage system. According to the selected path, the external connection processing for writing data to an external volume which corresponds to a virtual volume, and/or the remote copy processing for writing data to be written in a copy source volume to a copy destination volume, is/are executed at least once. By this, the data received by the start point storage system is written to the logical volume in the end point storage system.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: In a method of accessing a single port memory, a plurality of read commands are received from a plurality of requestors for memory read access. A respective plurality of parameters corresponding to each of the plurality of read commands is stored in a memory read command queue. The parameters corresponding to one of the read commands are retrieved from the memory read command queue when the single port memory provides the data corresponding to that read command. One or more of the parameters from the memory read command queue are provided while providing the data from the memory.

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i?j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.

Abstract: Managing access to a shared resource includes receiving a request indicating that an operation requires access to the shared resource, associating the operation with a lock in a lock queue that is associated with the shared resource, and determining whether the shared resource is accessible to the operation.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.

Abstract: Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

Abstract: In a memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed. Logical address space is divided into logical groups, a logical group having the same size as one erase block. Adaptive logical blocks are formed from logical groups. One adaptive logical block is stored in one adaptive metablock.

Abstract: A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

Abstract: A method for operating a computer network to preload the content of web addresses on the local memory. The network comprises at least one device, a web cache memory, and internet access apparatus to connect a device on the network to internet using a web browser, relevant devices on the network being accessible to a network administrator and defined network users, a method whereby one of the defined network users uses a modified web browser to define a set of web addresses to be accessed, the set of web addresses being stored in the network, and operates the network to cause the content of the set of web addresses to be stored on the web cache memory. Limits or quotas may be set up for the amount of memory space usable by each user and users may be limited to access web pages defined by one or more preload tasks.