Abstract: Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.

Abstract: Embodiments of the instant invention relate to a system for maintaining the integrity of data transfers in shared memory configuration by different processes to a data buffer located in the contiguous memory locations. The accesses by the different processes can be at the same time. One embodiment employs a CISC CPU and a peripheral using a Direct Memory Access (DMA) controller, both of which have an 8-bit data busses. The Memory Interface is provided with a sequencer and registers coupled to a Random Access Memory (RAM). The sequencer controls read and write operations of the RAM and ensures atomic transfer of multiple bytes to the RAM by one process invoking a special mode. This ensures that the other processes either read the old set of data or the new set of data with a minimum delay.

Abstract: A storage system is provided that includes a plurality of storage devices and a data structure, accessible to the storage system, that includes a plurality of records corresponding to a plurality of network devices that are coupled to the storage system. Each record includes configuration data that identifies each of the plurality of storage devices to which data access by a respective one of the plurality of network devices is authorized. Each record may further include visibility data that identifies whether certain types of non-data access, such as requests for general information relating to a respective storage device, by a respective one of the plurality of network devices is permitted, even though data access to the respective storage device by the respective one of the plurality of network devices is not authorized.

Abstract: An undo operation is executed by an application by performing the inverse actions of the do operation to which the undo operation relates. Previous designs simply swapped memory to execute an undo operation according to code that was entirely dissimilar to the code of the do operation. The dissimilarity of the code caused debugging such operations to be difficult. Using the inverse action to undo an action results in the similar code for the do, undo, and redo operations. Also, undo atoms are logged for do, undo, and redo operations so that any exceptions thrown during an operation allows the application to return to a previous, consistent state by operating on the undo atoms.

Abstract: The present disclosure relates to acquiring and releasing a shared resource via a lock semaphore and, more particularly, to acquiring and releasing a shared resource via a lock semaphore utilizing a state machine.

Abstract: A method of communicating memory mapped page priorities includes a software application storing page priority information for a memory mapped file on a computer readable medium, and an operating system reading the page priority information.

Abstract: A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request. If so, the system determines if the request is from a processor which is in a polite mode. If this is true, the system denies the request to access the cache line and continues executing the existing transaction.

Abstract: Provided are a method, system and program for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device.

Abstract: A data processing system able to raise the access efficiency to a memory when a plurality of processor access to the memory will be provided. An arbitration program executed by one input/output processing device determines a priority order for the access requests to the RAIDs so as to give the access permission with the highest priority to the access request linked with the reproduction port. The arbitration program notifies the result of the determination to the arbitrated programs executed by the other input/output processing devices.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: Architecture for a multi-threaded system that applies fairness to thread memory request scheduling such that access to the shared memory is fair among different threads and applications. A fairness scheduling algorithm provides fair memory access to different threads in multi-core systems, thereby avoiding unfair treatment of individual threads, thread starvation, and performance loss caused by a memory performance hog (MPH) application. The thread slowdown is determined by considering the thread's inherent memory-access characteristics, computed as the ratio of the real latency that the thread experiences and the latency (ideal latency) that the thread would have experienced if it had run as the only thread in the same system. The highest and lowest slowdown values are then used to generate an unfairness parameter which when compared to a threshold value provides a measure of fairness/unfairness currently occurring in the request scheduling process.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes fuller, requests are serviced in a manner that maximizes throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a region of shared memory managed on behalf of the first and second applications. Techniques are used to avoid preemption when the first application is accessing the shared memory region. In this way, the second application will not be unduly delayed when attempting to access the shared memory region due to delays stemming from the first application's access of the shared memory region. This is especially advantageous when the second application and operating system are adapted for real-time processing. Additional benefits can be obtained by taking steps to minimize memory access faults.

Abstract: A technique for processing a request requiring that a first volume of removable storage media be mounted on a storage device is disclosed. It is determined whether the storage device is available. In the event it is determined that the storage device is not available because it currently has mounted on it a second volume of removable storage media associated with a data mover, it is determined whether the data mover should be asked to permit the second volume to be removed from the storage device so that the first volume can be mounted thereon. In the event it is determined that the data mover should be asked to permit the second volume to be removed from the storage device so that the first volume can be mounted thereon, the data mover is prompted to provide an indication that the second volume may be dismounted from the storage device.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: A system for communication between components in a computer storage system includes a drive enclosure device having a plurality of disk drives. A switch module is electrically coupled to the drive enclosure device. The module has a plurality of physical layer links (PHYs). The module generates out-of-band (OOB) signals to transmit to the drive enclosure device, detects a physical location of an active drive enclosure device by interrogating the PHYs, and sends a serial management protocol (SMP) instruction to the drive enclosure device to perform a task, the SMP instruction based on the physical location.

Abstract: Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests.

Abstract: In one embodiment a multi-input, multi output memory system is disclosed. The system can include a plurality of single ported memory modules, an identifier module to provide an identify to each memory access requests of a plurality of memory access requests. The identity can include a port that receives the memory access request. The system can include a memory access controller coupled to the plurality of single ported memory modules that can control movement of the requests.

Abstract: A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

Abstract: Managing access to a shared resource includes receiving a request indicating that an operation requires access to the shared resource, associating the operation with a lock in a lock queue that is associated with the shared resource, and determining whether the shared resource is accessible to the operation.

Abstract: In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to t

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: A method, apparatus, and computer program product for storage pools with write atomicity. An abstraction manager enforces write atomicity and disallows options which are inconsistent with write atomicity. The abstraction manager constructs through a physical device interface a logical continuous view of a storage pool in a manner consistent with write atomicity. Applications collect information specific to write atomicity from the abstraction manager through an application interface.

Abstract: Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is provided achieving benefits over cooperative multitasking by any one or more of (1) executing rendering commands sent to the coprocessor in a different order than they were submitted by applications; (2) preempting the coprocessor during scheduling of non-interruptible hardware; (3) allowing user mode drivers to build work items using command buffers in a way that does not compromise security; (4) preparing DMA buffers for execution while the coprocessor is busy executing a previously prepared DMA buffer; (5) resuming interrupted DMA buffers; and (6) reducing the amount of memory needed to run translated DMA buffers.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used.

Abstract: A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.

Abstract: In order to allow a host computer to specify an operable logical unit (LU), a storage system responds with extended LU information, including at least connection portion numbers, target IDs and logical unit numbers according to an inquiry made from the host computer. An external storage system adds extended LU numbers used in coupling as responses to inquiry commands to specified logical units. Owing to such addition, the host computer is capable of collecting responses of inquiry commands to special device files of all storage systems recognized by the host computer. It is thus possible to obtain a list of extended LU numbers corresponding to all logical units recognized by the host computer. Since such an external storage system using LUN security is capable of effecting coupling operations only on logical units recognized by the host computer, security is enhanced.

Abstract: In one embodiment, a processor is operable to issue a first memory request to access a particular memory location, and, prior to completion of the first memory request, to issue a command to release a memory lock on the particular memory location when access to the particular memory location is complete. The processor is further operable to, prior to release of the memory lock, issue a second memory request to access a different memory location. Also a memory management unit is operable to receive the command to release the memory lock and to monitor for when access to the particular memory location is complete. The memory management unit releases the memory lock in response to completion.

Abstract: A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory request generator is configured to assign priorities to the memory requests based on a presentation order of the presentation elements. The processing apparatus also includes a memory request arbiter connected to the memory request generator. The memory request arbiter is configured to issue the memory requests based on the priorities assigned to the memory requests.

Abstract: A method, system and computer program product for modifying data elements in a shared data element group that must be updated atomically for the benefit of readers requiring group integrity. A global generation number is associated with the data element group and each member receives a copy of this number when it is created. Each time an update is performed, the global generation number is incremented and the updated element's copy of this number is set to the same value. For each updated data element, a link is maintained from the new version to the pre-update version thereof, either directly or using pointer-forwarding entities. When a search is initiated, the current global generation number is referenced at the commencement of the search. As data elements in the group are traversed, the reader traverses the links between new and old data element versions to find a version having a matching generation number, if any.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.

Abstract: One embodiment of the present invention provides a system that facilitates concurrent non-transactional operations in a transactional memory system. During operation, the system receives a load instruction related to a local transaction. Next, the system determines if an entry for the memory location requested by the load instruction already exists in the transaction buffer. If not, the system allocates an entry for the memory location in the transaction buffer, reads data for the load instruction from the cache, and stores the data in the transaction buffer. Finally, the system returns the data to the processor to complete the load instruction. In this way, if a remote non-transactional store instruction is received during the transaction, the remote non-transactional store proceeds and does not cause the local transaction to abort.

Abstract: The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time.

Abstract: A memory system is provided which is configured with a plurality of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). The system communicates via the bus (B) with a host system (HS) by operational memory commands that use logical memory sector numbers. The inventive system is characterized by an arbitration among the memory controllers so that for any memory operation requested by the host system (HS) the memory controller affected with respect to a range of logical memory sector numbers takes over the bus for communication with the host system.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries. A queuing circuit having a plurality of registers interconnected by 2:1 multiplexers is also provided. The circuit is arranged such that each register receives either its own current contents or the contents of a higher order register during each register write cycle.

Abstract: One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or more critical sections which are protected by locks. Next, the system modifies the program so that the critical sections which are protected by locks are executed transactionally without acquiring locks associated with the critical sections.

Abstract: A method for handling a remote copy request in a distributed storage includes providing a plurality of primary volumes within a primary storage system that is coupled to a primary host via a first network, the primary storage system being coupled to a secondary storage system via a second network. A first request is selected from a plurality of requests placed in a queue based on priority information associated with the requests. A first path group is selected from one or more path groups that could be used to transmit the request. The first request is transmitted to the secondary storage system using the first path group, the secondary storage system including a plurality of secondary volumes that are paired to the plurality of primary volumes.

Abstract: Embodiments include methods, apparatus, and systems for prioritizing input/outputs (I/Os) to storage devices. One embodiment includes a method that receives an input/output (I/O) command having a group number field and a priority number field at a target device. The method then generates a new priority value based on the group number field. The I/O command is processed at the target device with the new priority value.