Abstract: A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.

Abstract: A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Abstract: In one embodiment, a solution is provided wherein a lock manager is kept moving among multiple cores or processors in a multi-core or multi-processor environment. By “hopping” the lock manager from processor to processor, a bottleneck at any of the processors is prevented. The frequency of movement may be based on, for example, a counter that counts the number of input/outputs handled by the lock manager and moves the lock manager to a different processor once a determined threshold is met. In another embodiment of the present invention, the frequency of the movement between processors may be based on a time that counts the amount of time the lock manager has been operating on the processor and moves the lock manager to a different processor once a predetermined time is reached.

Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.

Abstract: A method for operating a data storage system that includes a plurality of mass storage devices, which are configured to store data redundantly, the method including determining a characteristic service level of one or more of the mass storage devices and defining a reduced service level, which is less than the characteristic service level. The method further includes performing the following steps automatically: detecting the reduced service level on a first mass storage device in the data storage system; determining that data on the first mass storage device is stored redundantly on a second mass storage device in the data storage system; and in response to detecting the reduced service level, diverting an input/output (IO) request for the data directed to the first mass storage device to the second mass storage device, while operating the first mass storage device at the reduced service level.

Abstract: Various systems and methods are disclosed for storing one or more point-in-time images of data stored in a block device in a sparse file. In one embodiment, a method involves identifying a block of data within a block device and copying the block of data to a sparse file. The block of data is identified in response to being modified. The sparse file stores an incremental image of data stored in the block device. In addition to storing an incremental image, sparse files can be used to store full images. Furthermore, a sparse file can store multiple images (full and/or incremental) of data stored in a block device.

Abstract: A computer system utilizes subsystem supplemental memory resources to implement operating system supplemental disk caching. A main system processor (e.g., a central processing unit) processes information associated with main system functions. A bulk memory (e.g., a hard disk) stores the information. A main system memory (e.g., a main RAM) caches portions of the bulk information. A subsystem supplemental memory (e.g., a graphics subsystem RAM) provides storage capacity for subsystem operations (e.g., graphics operations) and supplemental storage for portions of said bulk information associated with main system functions (e.g., functions performed by the main system processor). Information (e.g., main system information) cached in the subsystem supplemental memory can be accessed by the main system processor directly.

Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.

Abstract: A system calculates the optimal allocation of two or more resources provided by a resource provider to a task within a computer system from a plurality of possible allocations. In doing so, the system calculates the total volume of an N-dimensional cube, where N is the number of resources provided by the resource provider, representing the respective amounts of resources available to be allocated. The system also calculates the average volume of the N?1 dimensional shapes forming the sides of the N-dimensional cube. The system then calculates, at least partly from the ratio of the total volume to the average volume, the balance resulting from the allocation of resources represented by the N-dimensional cube. The system then calculates the imbalance resulting from the allocation of resources at least partly from the balance and determines the smallest imbalance as the optimal allocation of resources.

Abstract: A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed.

Abstract: The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time.

Abstract: File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that failover occurs in a prescribed sequence. Replication of information between the primary designated target and the secondary designated targets allows failover in a manner that maximizes continuity of operation. In addition, user-specified actions may be initiated on failure detection and/or on failover operations and/or on failback operations.

Abstract: A method, system and computer program product for modifying data elements in a shared data element group that must be updated atomically for the benefit of readers requiring group integrity. A global generation number is associated with the data element group and each member receives a copy of this number when it is created. Each time an update is performed, the global generation number is incremented and the updated element's copy of this number is set to the same value. For each updated data element, a link is maintained from the new version to the pre-update version thereof, either directly or using pointer-forwarding entities. When a search is initiated, the current global generation number is referenced at the commencement of the search. As data elements in the group are traversed, the reader traverses the links between new and old data element versions to find a version having a matching generation number, if any.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a region of shared memory managed on behalf of the first and second applications. Techniques are used to avoid preemption when the first application is accessing the shared memory region. In this way, the second application will not be unduly delayed when attempting to access the shared memory region due to delays stemming from the first application's access of the shared memory region. This is especially advantageous when the second application and operating system are adapted for real-time processing. Additional benefits can be obtained by taking steps to minimize memory access faults.

Abstract: Methods of monitoring a computer system. The methods may comprise the steps of calculating a first checksum of a data location and receiving a request from an operation running on the computer system for a lock corresponding to the data location. The methods may also comprise the steps of calculating a second checksum of the data location, and generating an indication if the first checksum and the second checksum are not equivalent. Also, methods of detecting a lock ranking violation in a computer system. The methods may comprise the steps of receiving a request from an operation for a first lock associated with a first data storage location and reviewing a list of locks issued to the operation. The methods may also comprise the step of determining whether the operation possesses a lock ranked higher than the first lock.

Abstract: In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.

Abstract: An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more memory interface modules including circuitry to access an external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to send a message to a memory interface module to determine whether previous memory transactions associated with a tile have been completed.

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: An embodiment of the present invention is directed to an apparatus for sharing memory among a plurality of compute nodes. The apparatus includes a memory, a plurality of interfaces for coupling the apparatus with the compute nodes, a switching fabric coupled with the interfaces, and a processor coupled with the switching fabric and the memory. The processor is operable to assign a portion of the memory to a particular compute node for exclusive access by the particular compute node.

Abstract: In a computer system where a site including a storage device system connected to high-rank apparatuses, via a network such as a SAN, and a site including a storage device system similarly connected to high-rank apparatuses via a network are connected to each other via an inter-high-rank-apparatuses network, arbitration-emulation software is installed in each of the high-rank apparatuses. A two-step arbitration is performed, thereby determining one high-rank apparatus. At first, a shared/exclusive control using an already-existing shared volume is performed based on an arbitration conducted within the site. Next, a shared/exclusive control based on an arbitration conducted between the sites is performed by high-rank apparatuses each of which has won the arbitration within each site.

Abstract: A method and an apparatus for reading and writing data are disclosed. The method includes: storing a request in a bank queue; comparing weight values of different banks in the bank queue, wherein the different banks comply with a time sequence parameter; and scheduling the bank queue according to the comparison result. With the embodiments of the present invention, the operation sequence may be optimized, and the buffer efficiency may be greatly improved.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A method for priority promotion of a service request comprises receiving the service request for a target address space into a set of work requests, the set of work requests comprising a plurality of service requests for the target address space, the service request originating from a source address space, the service request having a priority equivalent to a priority of the target address space, the source address space having a higher priority than the target address space; determining a number of service requests for the target address space in the set of work requests; and, in the event the number of service requests for the target address space exceeds a predetermined value, promoting the priority of the service request to the priority of the source address space.

Abstract: Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions that include determining by a thread executing on a virtual processor executing in a time slice on a physical processor whether an expected lock time for a critical section of the thread exceeds a remaining entitlement of the virtual processor in the time slice and deferring acquisition of a lock if the expected lock time exceeds the remaining entitlement.

Abstract: A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and software entities. The shared memory structure provides a common scratchpad buffer space for holding data that is processed by the various entities, provides interconnection for process/engine communications, and provides a queue for message passing using a common communication method that is agnostic to whether the engines are implemented in hardware or software. A plurality of hardware engines are supported as masters of the shared memory. The architectures provide superior throughput performance, flexibility in software/hardware co-design, scalability of both functionality and performance, and support a very simple abstracted parallel programming model for parallel processing.

Abstract: A method of controlling concurrent users of a distributed resource on a network is disclosed. In one aspect, there are one or more local lock managers executing on corresponding hosts and cooperating as a distributed lock manager. The resource is limited to a maximum number of concurrent users. A user identification for each user is associated with one host. In response to a request associated with a particular user associated with a first host, a lock is requested from a first local lock manager process executing on the first host. A related method of handling a request for a count-limited resource includes receiving a request from a client process for the computer resource. If it is determined that the request exceeds a maximum count for the resource, then it is determined whether a current time is within a retry time period of the client's first request.

Abstract: Included are embodiments for a method for servicing memory read requests. At least one embodiment of a method includes receiving read requests from the I/O device; testing predetermined fields from the read requests to predict a type of read request; and when the type of request is predicted to be a data read request, then route the read request to a first queue. Additionally, some embodiments include when the type of request is predicted to be a control read request, then route the read request to a second queue, wherein the second queue has a higher priority than the first queue; determining which of the first queue and second queue to read; retrieving at least one of the read requests from the determined queue; and processing the retrieved read request.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Abstract: An image forming apparatus includes a plurality of hardware resources provided to carry out image formation. A plurality of application programs perform respective processing of the plurality of hardware resources related to the image formation. A storage device stores rewritable shared data which is used by the application programs in common. A shared-data control unit suspends one of a write-lock request or a read-lock request that is received from one of the application programs when acquisition and/or updating of the shared data is inhibited, and after the acquisition and/or updating of the shared data is allowed, inhibits the acquisition and/or updating of the shared data by other application programs in accordance with the suspended request for the one of the plurality of application programs.

Abstract: Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.

Abstract: Techniques for data storage using disk drives. To conserve power and reduce heat generation so that higher packaging density is possible, only some of the disk drives in an array may be powered on at any one time. Disk accesses may then be scheduled so that appropriate drives are powered on and off at appropriate times. In addition, various levels of storage services may be provided depending, for example, upon how accessible the drives are to individual clients and upon a level of data redundancy provided. Another advantage includes off-loading of tasks to a controller or processor included within the disk drives themselves. For example, the disk drives themselves may compute error detection or error correction representations and perform data integrity checks based on those representations. Failure simulation may also be performed to verify the ability to recover lost data and the disk drives may be used to convert the data into general formats that may be expected to be more easily read in the future.

Abstract: A technique for efficiently boosting the priority of a preemptable data reader in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no longer capable of referencing the data elements. Upon the reader being subject to preemption or blocking, it is determined whether the reader is in a read-side critical section referencing any of the shared data elements. If it is, the reader's priority is boosted in order to expedite completion of the critical section. The reader's priority is subsequently decreased after the critical section has completed. In this way, delays in grace period processing due to reader preemption within the critical section, which can result in an out-of-memory condition, can be minimized efficiently with minimal processing overhead.

Abstract: One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.

Abstract: A memory buffer for an FB-DIMM having a first input/output interface for communicating with a memory controller at a first payload data rate and a second input/output interface for communicating with memory packages at a second payload data rate, wherein a relation of the first payload data rate to the second payload data is greater than 10.

Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.

Abstract: This computer system includes a first storage system and a second storage system. The first storage system has a data transfer unit for transferring the data stored in the first volume to the second volume of the second storage system. The second storage system has a snapshot creation unit for creating a snapshot of the second volume in a third volume based on a snapshot creation command. When the snapshot creation unit receives the snapshot creation command while transferring the data from the first volume to the second volume with the data transfer unit, it delays the creation of the snapshot of the second volume in the third volume until the transfer of the data from the first volume to the second volume is complete.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: An image processing apparatus which is equipped with card slots can cope with plural kinds of memory cards acting as media, and a recording apparatus does not occur a malfunction in its card reader due to a lack of a current to be supplied to the medium even when the plural media are respectively inserted in the card reader. To do so, when the media are initially inserted in the plural card slots, the slot in which the medium is first inserted is set to be available, and the remaining slots are set to be unavailable. Besides, power is not supplied to the slots which have been set to be unavailable.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: The storage and reproducing apparatus includes a signal processing block, a memory, a reproduction block, an operation block, and a control block. The signal processing block converts a sound signal entered, into a digital signal. The memory stores a digital signal outputted form the signal processing block and a management data of the digital data. The reproduction block at least converts a digital signal read out from the memory, into a hearable sound for reproduction output. The operation block is provided on an apparatus main body and includes a rotary operation block provided on the apparatus main body in such a manner that the rotary operation block can be rotated around a rotation center and shifted along plane which almost orthogonally intersects the rotation center. The control block, according to an input from the operation block, writes a digital signal and a management data into the memory and reads out a digital signal and a management data stored in the memory.

Abstract: It is possible to control the data transfer between a proxy server apparatus and an application server that is connected to the proxy server apparatus. A value added service control command is added to an request message and/or the response data. In accordance with the value added service control command included in the request message, a first proxy server 1a controls whether it relays this request message directly to a destination and it relays this request message to the destination after transferring this request message to an application server 7 and applying the value added service. Further, based on the value added service control command which is included in the response data, the first proxy server 1a controls whether it relays this response data directly to a destination or it relays this response data to the destination after transferring this response data to the application server 7 and applying the value added service.

Abstract: A modified read-ahead (i.e., jump) command, contains a sequential access parameter SAP, JUMPm(X,Y:SAP), for instructing a disc drive to jump to block Y after having read block X. If the SAP parameter has a value indicating that a host, such as a PC, designed to recognize the SAP parameter, deliberately signals a disc drive to jump to a lower address (e.g., Y<X), a disc drive designed in accordance with the present invention will comply. A disc drive not designed to recognize the modified read-ahead command may ignore the SAP parameter. A host not designed to recognize the modified read-ahead command is not capable of setting the SAP parameter.

Abstract: In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.

Abstract: It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.

Abstract: Provided is an apparatus and method for operating a flash memory according to a priority order, in which a fast response is insured. The apparatus includes a time calculation unit which calculates an operation execution time required to perform a first operation, a remaining time calculation unit which calculates a remaining time until completion of the first operation based on the calculated operation execution time if a second operation having a higher priority than that of the first operation is requested during performing of the first operation, and an operation processing unit which compares the calculated remaining time with an operation suspension time requested to suspend the first operation and determines whether to suspend the first operation in accordance with a result of the comparison.