Abstract: Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.

Abstract: A transactional memory processing system provides for the integration of transactional memory concepts at the compiler-level into a higher-level traditional transaction processing system. Atomic blocks at the compiler-level can be specified as atomic block transactions and include the features of atomicity and isolation. Actions within this atomic block transaction include the enlistment of resource managers from a repository. The repository can now include a pre-programmed memory resource manager to manage the transactional memory. As in traditional transactions, a commit protocol can be used to determine if the actions are valid and can be exposed outside of the transaction. Unlike traditional transactions, however, the transaction is not necessarily doomed if all of the actions are not validated. Rather, memory conflicts can cause a rollback and re-execution of the atomic block transaction, which can be repeated as long as necessary, until the memory resource manger votes to commit.

Abstract: A method and an apparatus of memory access request priority queue arbitration comprises sorting the requests into plurality of different priority levels firstly. The priority queues of different priority levels are arranged respectively according to the following steps: counting the cycles and latencies of each access request; counting the total cycles; comparing the latencies of each access request and total cycles respectively, if the total cycles is larger than the latency of a request, then arranging one more the same request in the priority queue, else executing the priority queue in order.

Abstract: A multi function device includes a main board configured to control functions corresponding to a model of the multi function device and a sub board configured to be connected with the main board. The sub board carries out peripheral control corresponding to the model of the multi function device. Main board first identification information indicative of a category of the main board is obtained, and main board second identification information intrinsic to each model of the multi function device is also obtained. Then, the model of the multi function device is identified based on the main board first identification information and the main board second identification information when the multi function device is powered on. Further, function information corresponding to the identified model is obtained. The main board and the sub board of the multi function device are controlled based on the function information so as to function correctly.

Abstract: The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link.

Abstract: A method and apparatus for managing snapshots of a file system using messages. A snapshot is a restorable version of a file system created at a predetermined point in time. A message is a persistent data structure supported by a file server. A message may include one or more snapshots, attributes for the message, and/or access control information for the message. The attributes and access control information are applied to all snapshots in the message. The attributes in the message enable users to perform automatic event-based management of the snapshots in the message. The access control information in the message provides granular access control to the snapshots in the message.

Abstract: Access to a memory area by a first processor that executes a first processor program and a second processor that executes a second processor program is granted to one of the first processor and the second processor at a time. Access to the memory area by the first processor and the second processor are cyclically uniquely allocated (e.g., t?[(ad mod m)=o]) between the first and the second processor by the first and second processor programs.

Abstract: The invention relates to a functional system comprising a set of functions (F, F?) which are to access a collective resource (RSRC), the system including an interface (INT) arranged to implement an access scheme (AS) including at least one state (I) defined by an order of priority for an arbitration according to which the functions (F, F?) can access the collective resource (RSRC), the state (I) being characterized in that, for at least one set of at least two functions (F), the access possibilities in read mode (F_R) and the access possibilities in write mode (F_W) have different priority levels, the access possibilities in read mode having consecutive priority levels higher than the priority levels of the access possibilities in write mode.

Abstract: A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently. Additionally, the caching estimator process computes the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads. As a result, the caching estimator applies the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.

Abstract: Chronological identification information is composed of a plurality of cyclic numbers with priorities. For generating new chronological identification information, the chronological relation is compared in order from cyclic numbers with the highest priority to extract the newest chronological identification information in the chronological relation; when the newest chronological identification information in the chronological relation is extracted, a cyclic number with a priority as a comparison target in the extraction of the extracted chronological identification information is determined to be a cyclic number with the priority in the newly generated chronological identification information.

Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area.

Abstract: An automated memory management or garbage collection routine uses a first garbage collection routine to perform garbage collection on new objects, and a second garbage collection routine to perform garbage collection on old objects. The two garbage collection routines are operated concurrently, with each routine separately marking objects to be reclaimed. The second routine may operate in a background mode by traversing a tree of objects from a copy of memory, while the first routine may operate on actual memory.

Abstract: A method, system and computer program product for communicating requests to multiple destinations in a business transaction are disclosed. A mass request is communicated to a processing center, the mass request including an identification portion and a content portion. The identification portion is used to obtain a parent attribute common to requests to all destinations. The content portion is parsed to generate multiple content strings corresponding to the multiple destinations. The parent attribute and each content string is combined to generate an individual request to a respective destination.

Abstract: A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.

Abstract: A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item.

Abstract: Network servers in a cluster share the same network protocol address for incoming client requests, and in a data link layer protocol a reply of a client to a request from a server is returned to this same server. For example: (1) ports of the servers are clustered into one single network channel used for incoming and outgoing requests to and from the servers; or (2) ports of the servers are clustered into one single network channel used for incoming requests to the servers and a separate port of each of the servers is used for outgoing requests from each of the servers; or (3) logical ports of the servers are clustered into one network channel used for requests to the servers and a separate logical port of each of the servers is used for outgoing requests from each of the servers.

Abstract: A system, apparatus and method of enhancing priority boosting of scheduled threads are provided. If, while being executed by a second CPU, a second thread determines that it has to wait for a lock on a shared resource held by a first thread that is scheduled to be executed by a first CPU, the second thread may boost the priority of the first thread by passing its priority to the first thread if its priority is higher than the first thread's priority. Further, to enhance the priority boost of the first thread, the second thread may reschedule the first thread to be processed by the second CPU. By having been rescheduled on the second CPU, the second thread may be dispatched for execution right thereafter.

Abstract: Arbitration for a processor block core is described. Master devices are associated with a processor block core embedded in a host integrated circuit (“IC”). The master devices are coupled to core logic of the host IC via a crossbar switch and a bridge, which are part of the processor block core. The crossbar switch includes an arbiter. An arbitration protocol is selected from among a plurality of arbitration protocols for use by the arbiter. Pending transactions having are polled for access to the bridge for arbitration using the arbitration protocol selected.

Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.

Abstract: A device and a method to efficiently process the symbols coded in OFDM according to the various protocols available. This is achieved through a device to process OFDM-based symbols comprising a base band input data and a base band output data, and comprising at least two programmable execution units connected to at least one working memory, this device being characterized in that, the programmable execution units (EU) are connected to the memory (M-1, M-2, M3, . . .

Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: One embodiment of the present invention provides a system that performs thread migration within an array of computing nodes, wherein computing nodes in the array contain central processing units (CPUs) and/or memories. During operation, the system identifies CPUs within the array of computing nodes that are available to accept a given thread. For each available CPU, the system computes an average communication distance between the CPU and memories which are accessed by the given thread. Next, the system determines whether to move the given thread to an available CPU based on the average communication distance for the available CPU.

Abstract: Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

Abstract: A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

Abstract: A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

Abstract: A memory bandwidth control device for improving efficiency of data transfer between an external device and a memory. A memory is used for temporarily storing and outputting data to be communicated with external devices being connected via input/output ports, and an I/O buffer dynamically assigns memory bandwidth to external devices requesting data transfer when receiving the data transfer requests from the external devices to the memory. When compared to assigning fixed memory bandwidth, efficiency of data transfer to the memory can be significantly improved without wasting memory bandwidth.

Abstract: A technique for realtime-safe detection of a grace period for deferring the destruction of a shared data element until pre-existing references to the data element have been removed. A per-processor read/write lock is established for each of one or more processors. When reading a shared data element at a processor, the processor's read/write lock is acquired for reading, the shared data element is referenced, and the read/write lock that was acquired for reading is released. When starting a new grace period, all of the read/write locks are acquired for writing, a new grace period is started, and all of the read/write locks are released.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Abstract: A data storage resource is identifiable by physical addresses, and optionally by a virtual address. A policy defines which resources are accessible and which resources are not accessible. A request to access a resource is allowed if access to the resource is permitted by the policy, and if carrying out the access will not cause virtual addresses to be assigned to resources to which the policy disallows access. Since resources to which access is disallowed do not have virtual addresses, certain types of access requests that identify a resource by a virtual address can be allowed without consulting the policy.

Abstract: A microcontroller system includes at least one processor and at least one storage unit for storing data received from or to be sent to the processor. At least two read clients are provided in the processor for retrieving data from the storage unit, and at least one write client is provided in the processor for writing data in the storage unit. The system further includes a memory device provided in the storage unit for storing data, and an arbitration device provided in the storage unit for enabling access to the memory device by the read and the write client. The read clients each have a dedicated read address line connected to the arbitration device for sending a read address of read data to be retrieved from the memory device, and a shared read data bus connected to the memory device for receiving the read data from the read address.

Abstract: An information processing apparatus for processing an access request to access a recording medium from an application includes the following elements. A setting unit sets a priority unique to the access request from the application or permission information indicating whether or not processing on the access request from the application is permitted. A queue controller stores the access request provided with the priority or the permission information in a queue. An access request processor processes the access request stored in the queue according to the priority or the permission information.

Abstract: A hardware implemented transactional memory system includes a mechanism to allow multiple processors to access the same memory system. A set of timestamps are stored that each correspond to a region of memory. A time stamp is updated when any memory in its associated region is updated. For each memory transaction, the time at which the transaction begins is recorded. Write operations that are part of a transaction are performed by writing the data to temporary memory. When a transaction is to be recorded, the hardware automatically commits the transaction by determining whether the timestamps associated with data read for the transaction are all prior to the start time for the transaction. In this manner, the software need not check the data for all other processes or otherwise manage collision of data with respect to different processes. The software need only identify which reads and writes are part of a transaction.

Abstract: An interactive client-server authentication system and method are based on Random Partial Pattern Recognition algorithm (RPPR). In RPPR, an ordered set of data fields is stored for a client to be authenticated in secure memory. An authentication server presents a clue to the client via a communication medium, such positions in the ordered set of a random subset of data fields from the ordered set. The client enters input data in multiple fields according to the clue, and the server accepts the input data from the client via a data communication medium. The input data corresponds to the field contents for the data fields at the identified positions of the random subset of data fields. The server then determines whether the input data matches the field contents of corresponding data fields in a random subset.

Abstract: Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients.

Abstract: An I/O decoupling system comprising an I/O accelerator coupled between a host interface and a channel interface, wherein the I/O accelerator comprises a host manager, a buffer manager a function manager, and a disk buffer. The host manager is coupled to the host interface to receive a request from a connected host computer. The function manager in response to receiving the request allocates the disk buffer and determines a threshold offset for the buffer while coordinating the movement of data to the disk buffer through the channel interface coupled to the disk buffer.

Abstract: A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.

Abstract: A first queue receives transactions from a transaction source in first-in/first-out (FIFO) order regardless of priority. A second queue receives lower priority transactions from the first queue as compared to the higher priority transactions remaining in the first queue. A priority check module controls the forwarding schedule of transactions from the first and second queues in accordance with the associated priorities of the stored transactions. Should an address conflict arise between transactions in the first and second queues, the priority check module stalls forwarding from the first queue while promoting forwarding from the second queue during the conflict condition.

Abstract: A method and apparatus for processing a file system operation at a database server is provided. A request to perform a file system operation on a resource stored in a database is received at a database system. The request may be implemented using the NFS protocol. The request may include state identification data that identifies state information associated with the request. State information associated with the request is retrieved within the database system based on the state identification data. State information is information that describes the operational state of the requestor for a particular file. The request is then processed based, at least in part, on the state identification. File system operations may be processed a database management system to access any data, such as a file, relational data, and object-relational data.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.

Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.

Abstract: Enabling secure and efficient marshaling, utilization, and releasing of handles in either of an operating system or runtime environment includes wrapping a handle with a counter to tabulate a number of threads using currently using the handle. Thus, handle administration is implemented to circumvent potential security risks, avoid correctness problems, and foster more efficient handle releasing.

Abstract: An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

Abstract: A prioritized address decoder has been disclosed. One embodiment of the prioritized address decoder includes a first comparator to compare a destination device address of data with a first address range associated with a first device and a second comparator coupled to the first comparator to compare the destination device address with a second address range associated with a second device, wherein the data is sent to the second device in response to a first output of the first comparator and a second output of the second comparator.

Abstract: A digital system with an improved transaction ordering policy is disclosed. Individual occurrences of requests for access to common system resources specify whether or not the request is ordered. In some embodiments, the invention includes a memory that holds data, a controller, and at least two processors that generate requests to access the memory data. Each access request includes an indication of whether or not this request is to be performed in a sequential order among other access requests and, if so, an indication of the order. The controller receives the access requests from each processor, determines a performance order for the requests, and provides the access requests to the memory in the performance order. The performance order conforms to the specified order when the access requests so indicate.

Abstract: A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating that one of the destinations is available to accept a forward message; simultaneously sending a forward message to each available destination; simultaneously receiving, after a predetermined period of time, a plurality of reverse messages from the destinations, each reverse message corresponding to one of the forward messages simultaneously sent to an available destination; and serially sending the reverse messages to the source.

Abstract: A system and method is disclosed for prioritizing requests received from multiple requesters for presentation to a shared resource. The system includes logic that implements multiple priority schemes. This logic may be programmably configured to associate each of the requesters with any of the priority schemes. The priority scheme that is associated with the requester controls how that requester submits requests to the shared resource. The requests that have been submitted by any of the requesters in this manner are then processed in a predetermined order. This order is established using an absolute priority assigned to each of the requesters. This order may further be determined by assigning one or more requesters a priority that is relative to another requester. The absolute and relative priority assignments are programmable.

Abstract: A semiconductor memory device includes a memory cell core having a plurality of memory cells; a data input/output circuit unit, which sets an input/output data width in response to input/output control signals and inputs/outputs data signals through at least some of a plurality of input/output pads; a pipelined circuit unit, which is connected to the data input/output circuit unit through input/output lines and transmits the data signals between the memory cell core and the data input/output circuit unit in synchronization with predetermined clock signals through an input/output path selected in response to pipeline enable signals; and a plurality of selection units, which are connected to the input/output lines through external common data lines and connect some of the input/output lines to the data input/output circuit unit in response to selection control signals.

Abstract: A dynamic memory refresh controller includes a first in first out (FIFO) memory, a scheduler, a refresh control unit, and a signal generator. The FIFO memory stores and manages requests from a master device. The scheduler reorders the requests from the master device based on priorities assigned to the master device or provides information about following requests. The refresh control unit determines a refresh timing of the dynamic memory based on the existence of the following requests and an idle state of banks constituting the dynamic memory. Accordingly, the dynamic memory refresh controller may maximize a refresh trigger interval by changing the management order of the requests from the master device based on the priority of the response latency.

Abstract: A method of and system for protecting a disk drive or other data storage includes mounting a virtual storage that combines a full access temporary storage and a READ-only portion of a main storage, wherein the READ-only portion represents a protected area of the main storage; generating a bitmap for blocks of the virtual storage; redirecting virtual storage write requests to the temporary storage; marking, in the bitmap, blocks of the virtual storage corresponding to blocks of the temporary storage that are being written to; redirecting, to the READ-only portion, read requests for unmarked blocks; redirecting, to the temporary storage, read requests for marked blocks; upon an acceptance of a state of the virtual storage, merging the temporary storage with unmarked blocks of the READ-only portion of the main storage, to form an integral storage; and upon a rejection of a state of the virtual storage, terminating the redirecting. Optionally, data in the temporary storage can be archived.