Abstract: A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, which is an Intel or similar Complex Instruction Set Computer architecture, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: An embodiment of the invention provides an apparatus and a method of dynamically controlling the number of busy waiters in for a synchronization object. The apparatus and method perform the steps of increasing a number of allowed busy waiters if there is a waiter in a sleep state and there are no current busy waiters when a requester releases the synchronization object, and decreasing the number of allowed busy waiters if a busy waiter moves from a busy waiting state to the sleep state.

Abstract: A memory controller is provided for dealing with change in the form of use or operation state of a system. The memory controller includes bus interfaces, a memory controller core unit, and a memory interface. The memory controller core unit has a command controller. The bus interface units and command controller exchange commands via a bus.

Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.

Abstract: A storage interfacing method and apparatus for a mobile terminal are disclosed. The storage interfacing method utilizes a plurality of storage devices. The method includes identifying the storage devices, detecting an occurrence of an access request event to one of the identified storage devices, determining whether the access-requested storage device is an access-selected storage device, and performing, if the access-requested storage device is an access-selected storage device, a data transfer operation associated with the access request event on the access-selected storage device without access initialization and access-selection. The apparatus includes a first storage device supporting a MultiMediaCard (MMC) interface, a second storage device compatible with the MMC interface, and a control unit for controlling the first and second storage devices, according to the MMC interface, through control and data buses shared by the first and second storage devices.

Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifies the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.

Abstract: The invention provides a method and system for managing data access. The method includes receiving a request for accessing a file, determining a type of the received request that corresponds to an access pattern based on history of many files, marking the request based on the type of request to identify the request as a candidate to be part of a sequential scan for accessing files in a sequential order, and processing the request based on the marking to throttle access of the file in the case of a potential ongoing erroneously requested sequential scan.

Abstract: A first-in-first-out (FIFO) queue optimized to reduce latency in dequeuing data items from the FIFO. In one implementation, a FIFO queue additionally includes buffers connected to the output of the FIFO queue and bypass logic. The buffers act as the final stages of the FIFO queue. The bypass logic causes input data items to bypass the FIFO and to go straight to the buffers when the buffers are able to receive data items and the FIFO queue is empty. In a second implementation, arbitration logic is coupled to the queue. The arbitration logic controls a multiplexer to output a predetermined number of data items from a number of final stages of the queue. In this second implementation, the arbitration logic gives higher priority to data items in later stages of the queue.

Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.

Abstract: The invention concerns a scheduler for sharing a resource comprising a storage unit for storing user deadlines, FIFO storage units, associated each with a first increment value (d(j)) and, for some of them (c(j, i), with a second increment value (d(i)), for storing user-identifiers. The scheduler comprises a management unit selecting one of the FIFO storage units to serve the user designated as next to serve for the resource, recycling his user-identifier, and a recycling decision unit for redirecting, in accordance with conditions, which include a comparison between the second increment value of the FIFO where the user is going and the first increment value from where the user is coming.

Abstract: A method for detecting race conditions involving heap memory access including a plurality of threads being tracked. At runtime a plurality of APIs utilized to create and destroy thread synchronization objects are intercepted, and each synchronization object created via the APIs is tracked. A bit field is created that contains a unique bit for each synchronization object. Heap memory allocations and deallocations are intercepted and tracked. The heap memory access is intercepted, and at that time, the ID of the accessing thread is compared with the last thread ID associated with that memory block when it was last accessed. If the thread IDs do not match, then the current thread synchronization object bit field is compared with the last synchronization object bit field associated with thread memory block. Provided the bit fields are different, a race condition warning is reported that is displayable to the user having the call chains.

Abstract: A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

Abstract: A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item.

Abstract: A device, including a first storage unit configured to store a first plurality of files and a first management data corresponding to the first files; a connector configured to connect to an external storage device, the external storage being configured to store a second plurality of files and second management data corresponding to the second files; a controller configured to generate new management data by merging the first management data and the second management data, and to store the new management data in a memory; and a display unit configured to display contents of the first and second plurality of files based on the new management data without indicating to the user where the respective files are stored.

Abstract: A remote copy method for copying data within a first storage apparatus to a second storage apparatus via a network, includes transmitting data from the first storage apparatus in units of first buffer sets each formed by a plurality of first recording exclusive buffers within the first storage apparatus, and receiving the data by the second storage apparatus in units of second buffer sets each formed by a plurality of second recording exclusive buffers within the second storage apparatus, so as to maintain a sequence guarantee with respect to the data that is copied.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A storage control apparatus capable of rapidly carrying out data processing according to requests from upper order apparatus, and capable of rapidly returning the results of processing to the upper order apparatus is provided. A computer system comprised of upper order apparatus and storage control apparatus is disclosed. The upper order apparatus accesses a virtual volume. A pool volume is allocated to the virtual volume. The pool volume is provided with a storage region of storage discs. The pool volume classifies data sent from the upper order apparatus for every type into text data, block data, and large sized data. The storage control apparatus then recognizes the types of data and stores the data on respective volumes.

Abstract: Embodiments of the present invention provide a resource management mechanism to monitor the availability of resources, detect the cause of a rejection, distinguish between different types of rejections, and manage the different types accordingly. For example, a queue manager in accordance with embodiments of the invention may be able to classify rejected requests, for example, as either a “long reject” or a “short reject” based on the cause of the rejection and the amount of time the rejection conditions are expected to remain valid. A short reject request may be rescheduled in an appropriate service queue, while a long reject request may be suspended in a reject queue. Other features are described and claimed.

Abstract: A network device for monitoring a memory partitioned by an identifier can include at least one port configured to receive at least one packet. The at least one packet includes an identifier relating to priority of the at least one packet. The network device can also include a buffer memory having at least one buffer configured to store the at least one packet, and a counter configured to modify a counter value therein when the buffer memory is accessed with respect to the at least one data packet, wherein the counter corresponds to the identifier with respect to the at least one packet.

Abstract: A method of and system for protecting a disk drive or other data storage includes mounting a virtual storage that combines a READ-only portion of a volume of the main storage and a full access temporary storage located on the same data storage, wherein the READ-only portion represents a protected area of the volume of the main storage; generating a bitmap for blocks of the virtual storage; redirecting virtual storage write requests to the temporary storage; marking, in the bitmap, blocks of the virtual storage corresponding to blocks of the temporary storage that are being written to; redirecting, to the READ-only portion, read requests for unmarked blocks; redirecting, to the temporary storage, read requests for marked blocks; upon an acceptance of a state of the virtual storage, merging the temporary storage with unmarked blocks of the READ-only portion of the volume of the main storage, to form an integral storage; and upon a rejection of a state of the virtual storage, terminating the redirecting.

Abstract: A storage system of this invention maintains consistency of the stored contents between volumes even when a plurality of remote copying operations are executed asynchronously. A plurality of primary storage control devices and a plurality of secondary storage control devices are connected by a plurality of paths, and remote copying is performed asynchronously between respective first volumes and second volumes. Write data transferred from the primary storage control device to the secondary storage control device is held in a write data storage portion. Update order information, including write times and sequential numbers, is managed by update order information management portions. An update control portion collects update order information from each update order information management portion, determines the time at which update of each second volume is possible, and notifies each-update portion.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.

Abstract: A bus arbiter receives requests of initiators, and internally includes a page hit/miss determining unit with permissible determining function, a bank open/close determining unit with permissible determining function, and an LRU unit with permissible determining function. Regarding the priority of the request arbitration on the requests, the bank priority on the SDRAM is determined in the order of page hit, bank open, and LRU. Furthermore, each determining unit internally includes a permissible time determining unit, and processes, at top priority, the request of the initiator which the corresponding permissible time is below the count threshold value in the priority processing of the determining unit.

Abstract: A system and method of accessing memory within an information handling system are disclosed. In one form, a method of accessing memory can include detecting a first operating value of a first memory access node accessible to a first processor, and initiating operation of the first memory access node to a first data rate value. The method can also include initiating operation of a second memory access node to a second data rate value. In one form, the second data rate value can be different from the first data rate value. The method can also include enabling a first application access to either the first memory access node or the second memory access node via an operating system enabled by the processor.

Abstract: A system and method for providing security for an Internet server. The system comprises: a logical security system for processing login and password data received from a client device during a server session in order to authenticate a user; and a physical security system for processing Internet protocol (IP) address information of the client device in order to authenticate the client device for the duration of the server session.

Abstract: A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.

Abstract: In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Abstract: A SDRAM controller prioritizes memory access requests to maximize efficient use of the bandwidth of the memory data bus, and also gives different priorities to access requests received on its different inputs. The SDRAM controller has multiple inputs, at least one of which allows connections to multiple bus master devices. The SDRAM controller forms a queue of bus access requests, based amongst other things on a relative priority given to the input on which a request is received. When a request is received on an input which allows connections to multiple bus master devices, the SDRAM controller forms the queue of bus access requests, based amongst other things on a relative priority given to the bus master device which made the request.

Abstract: A method and system for providing quality of service to a plurality of hosts accessing a common resource is described. According to one embodiment, a plurality of IO requests is received from clients executing as software entities on one of the hosts. An IO request queue for each client is separately managed, and an issue queue is populated based on contents of the IO request queues. When a host issue queue is not full, a new IO request is entered into the host issue queue and is issued to the common resource. A current average latency observed at the host is calculated, and an adjusted window size is calculated at least in part based on the current average latency. The window size of the issue queue is adjusted according to the calculated window size.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.

Abstract: In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value may then be used in determining an appropriate cache line for eviction. Other embodiments are described and claimed.

Abstract: A conflict avoidance system is provided. The conflict avoidance system comprises a first data store provided at a first geographic location and a second data store at a second geographic location, where the first and second data stores are replications of one another. The conflict avoidance system also comprises a conflict avoidance module operable to receive a data store request from applications, wherein the conflict avoidance module communicates update data store requests to the first data store and communicates create data store requests and delete data store requests to the second data store.

Abstract: An embedded system comprises a storage device, a main memory, and an operating system (OS). The storage device stores executable files, data files, and at least one dependency tag of an application which have been installed on the embedded system. The dependency tag records relationships between the application and related data files utilized by the application under various execution statuses. The OS comprises a module which, when requested to execute the application, locates the related data files of the application according to the dependency tag, loads the executable file and the related data files to the main memory, and execute the executable file.

Abstract: A method allocating firmware objects between different types of memory in a product model based on a frequency of access of each firmware object in trace data. The allocated firmware objects and trace data are used to simulate the performance of the product model. Memory access statistics obtained during the simulation may be used to analyze product model performance in the frequency and time domains.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: Some embodiments of the present invention provide a system that manages a performance of a computer system. During operation, a current expert policy in a set of expert policies is executed, wherein the expert policy manages one or more aspects of the performance of the computer system. Next, a set of performance parameters of the computer system is monitored during execution of the current expert policy. Then, a next expert policy in the set of expert policies is dynamically selected to manage the performance of the computer system, wherein the next expert policy is selected based on the monitored set of performance parameters to improve an operational metric of the computer system.

Abstract: A protection register array in which the lock status of the protection register is stored outside of the array. An initial verify function is used to read lock status.

Abstract: Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value.

Abstract: Described is a storage system and method for reducing power consumption in a storage system by shortening seek distances associated with input/output (I/O) requests to a physical disk drive. A sweep direction is set. An offset of a new I/O request is evaluated to determine whether to send the new I/O request to the physical disk drive. The new I/O request is sent to the physical disk drive if the offset is consistent with the sweep direction. Otherwise, sending the new I/O request to the disk drive is deferred until the sweep direction is set to a reverse direction.

Abstract: Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.

Abstract: A circuit arrangement and method detect external requests to access a memory array in a hardware simulation accelerator during performance of a simulation on a simulation model and access the memory array without halting the simulation in response to detecting the external request. Such functionality may be provided, for example, by detecting such external requests in response to processing a predetermined instruction in an instruction stream associated with the simulation model, where the predetermined instruction is configured to ensure a predetermined period of inactivity for the memory array. By doing so, the memory array can be accessed from outside of the hardware simulation accelerator during the processing of a simulation, and without requiring that the simulation be halted, thus reducing overhead and improving simulation efficiency.

Abstract: The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In line with the invention, the memory controller has a command scheduler which prioritizes the transmission of memory bank commands on the basis of a static priority allocation for commands and a dynamic priority allocation for channels.

Abstract: Managing physical memory for one or more processes with both a minimum and a maximum amount of physical memory. Memory sets are created, each specifying a number of credits. The total number of credits specified by all memory sets are equal to the total number of pages in physical memory. One or more processes are bound to a memory set. All of the processes bound to a memory set are collectively referred to as the workload of the memory set. Each physical page is accounted for to ensure that each workload can utilize at least the number of physical pages equaling the number of credits in its memory set. Additionally, a workload is permitted to use physical pages that are being explicitly shared by workloads of other memory sets. Accordingly, a workload with both a minimum and a maximum amount of physical memory is specified by its memory set.

Abstract: The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

Abstract: A method, and corresponding system and software, is described for writing data to a plurality of queues, each portion of the data being written to a corresponding one of the queues. The method includes, without requiring concurrent locking of more than one queue, determining if a space is available in each queue for writing a corresponding portion of the data, and if available, reserving the spaces in the queues. The method includes writing each portion of the data to a corresponding one of the queues.

Abstract: Circuits, methods, and apparatus for FIFO memories made up of multiple local memory arrays. These embodiments limit the number and length of interconnect lines that are necessary to join two or more local memory arrays into a single, larger functional unit. One exemplary embodiment of the present invention provides a FIFO made up of a number of FIFO sub-blocks connected in series. Each FIFO sub-block includes local read and write address counters such that read and write addresses are not bused between the FIFO sub-blocks.

Abstract: A device, including a first storage unit configured to store a first plurality of files and a first management data corresponding to the first files; a connector configured to connect to an external storage device, the external storage being configured to store a second plurality of files and second management data corresponding to the second files; a controller configured to generate new management data by merging the first management data and the second management data, and to store the new management data in a memory; and a display unit configured to display contents of the first and second plurality of files based on the new management data without indicating to the user where the respective files are stored.

Abstract: A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.