Abstract: A method and apparatus for providing very large logical volumes (Meta Device) in a storage system is provided. The storage system includes host controllers and disk controllers which communicate through a shared memory. I/O requests are received by the host controller and placed into request queues. The request queues are associated with logical devices. A number of request queues in the host controller are concatenated together to produce the larger logical volume. The large logical volume appears to the host as a single addressable logical unit. I/O requests to the large logical volume are analyzed by the host controller to determine which logical devices are actually needed to service the request. The host controller then makes the appropriate queue entries. Processing of the requests then occurs in the same fashion as if the request had been to a non-Meta Device. This allows the disk controllers and memory to operate without modification.

Abstract: The method of the present invention provides a procedure for testing shared-memory multi-processor (SMMP) performance by formulating and modifying a given memory contention matrix (MCM), which is generated by collecting traces of memory addresses accessed by so-called subcalls in an SMMPCC. A subcall pair contending for at least one shared memory access address enters a "1" at the respective matrix element. For subcall pairs not sharing any memory address a ".O slashed." is entered.

Abstract: A virtual linear frame buffer addressing method and apparatus efficiently convert a linear address supplied by an application programming (API) into an X, Y address used in a rectangular memory addressing arrangement. The virtual linear frame buffer addressing logic allows rectangular memory addressing to coexist in an environment that requires the use of linear memory addressing by creating a table of address ranges, byte stride values and physical address offset descriptors. The address ranges and byte stride values are associated with particular sections of frame buffer memory. An offset descriptor is associated with each section of physical memory. The address ranges, byte stride values and offset descriptors are placed into a table. When a linear address is received from an API, the address range is determined. The lower bound of the address range is the base address. The base address is subtracted from the linear address resulting in a local linear address.

Abstract: A new virtual memory system is disclosed having a virtual address space including a gap of inaccessible virtual addresses within the virtual address space. A new virtual memory allocation routine is disclosed providing a starting address of accessible virtual addresses allocated to a currently executing process in a response to a request. The accessible virtual addresses are virtually contiguous, and include no addresses from within the gap of inaccessible virtual addresses. A new virtual memory deallocation routine is further disclosed providing deallocation of ranges of virtual addresses which may or may not include addresses within the inaccessible gap.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping "fill" requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the "victim" data in that CPUs cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the `ships crossing in the night` problem is avoided.

Abstract: A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.

Abstract: A multiprocessor system has a transmitting processor and a receiving processor. In response to a transmission request, the transmitting processor implements means for selecting one of two communication buffers of a shared memory in accordance with a given rule; write inhibit means for changing the selected communication buffer to a write-disabled state in order to inhibit writing of the selected communication buffer by other processors; data writing means for copying data from a local memory to the selected communication buffer; write-completion notifying means for notifying a receiving processor of completion of writing; and transmission-end discriminating means for discriminating end of transmission processing.

Abstract: A method and apparatus for receiving and transmitting network frames via an internetworking device, in which a first portion of a total number of buffers is allocated among port-dedicated buffer pools, and a second portion is placed in a common pool accessible by any of the network ports. A frame is received at a first port, and a list of buffers accessible only by that port is referenced to identify buffers not already in use. A second list of buffers in the common pool is referenced to identify unused buffers for use if insufficient unused buffer space is available in the port-dedicated buffer pool. Frame data is then stored in the identified buffer(s). Upon retransmission, the buffer(s) used to store the. transmitted frame is released to the port-dedicated and/or common buffer pool(s).

Abstract: A method and system for increasing system memory bandwidth within a symmetric multiprocessor data-processing system are disclosed. The symmetric multiprocessor data-processing system includes several processing units. With conventional systems, all these processing units are typically coupled to a system memory via an interconnect. In order to increase the bandwidth of the system memory, the system memory is first divided into multiple partial system memories, wherein an aggregate of contents within all of these partial system memories equals to the contents of the system memory. Then, each of the processing units is individually associated with one of the partial system memories, such that the bandwidth of the system memory within the symmetric multiprocessor data-processing system is increased.

Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.

Abstract: Data is written to and read from a shared pipe by applications of multiple systems. At least one shared pipe is located within an external shared memory coupled to one or more central processing complexes. Each of the central processing complexes has one or more operating system images, which controls execution of one or more piping applications. At least one piping application corresponding to at least one operating system image writes data to a shared pipe located in the external shared memory and at least one other application corresponding to one or more other operating system images reads data from the same shared pipe, thereby providing cross-system data piping.

Abstract: A memory system and management method for optimized dynamic memory allocation are disclosed. A memory manager requests a large area of memory from an operating system, and from the viewpoint of the operating system, that memory is fixed. That fixed memory area is then divided up into an integral number of classes, e.g. by the memory manager. Each memory class includes same-size blocks of memory linked together by pointers. The memory block sizes are different for each class, and the sizes of the different class memory blocks are selected to conform to the CPU and memory access bus hardware (e.g. align with a bus bit width) as well as to accommodate the various sizes of data expected to be processed for a particular application. The memory manager maintains a separate, linked list of unused blocks for each class. Each memory block is zeroed initially and after release by a process previously assigned to it. When a block of memory is assigned to a particular process, a flag is set to indicate that it is in use.

Abstract: A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory.

Abstract: Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are "Owned" and "Unowned." The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Abstract: The problem of extending modern operating systems to run efficiently on large-scale shared memory multiprocessors without a large implementation effort is solved by a unique type of virtual machine monitor. Virtual machines are used to run multiple commodity operating systems on a scalable multiprocessor. To reduce the memory overheads associated with running multiple operating systems, virtual machines transparently share major data structures such as the operating system code and the file system buffer cache. We use the distributed system support of modem operating systems to export a partial single system image to the users. Two techniques, copy-on-write disks and the use of a special network device, enable transparent resource sharing without requiring the cooperation of the operating systems. This solution addresses many of the challenges facing the system software for these machines.

Abstract: A terminal printer can simultaneously receive print data from a plurality of host devices. The terminal printer has one reception buffer memory to which reception buffers are allocated on the basis of number information of the connected host devices, and a buffer management memory which manages the reception buffer memory. The buffer management memory is configured by region which respectively store terminal addresses of the host devices using the reception buffers, and regions which respectively store serial numbers of lastly received packets in correspondence with the reception buffers. When a packet is received, the terminal address of the host device included in the packet is compared with the terminal addresses stored in the buffer management memory. Subsequently, the packet is stored into the reception buffer of the reception buffer memory which is designated by the coincident terminal address.

Abstract: A computer network comprises a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controllers includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. In addition to providing redundancy features, the plurality of RAID controllers operable in accordance with the methods of the present invention enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Under the methods of the present invention, each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives.

Abstract: In a computer system, a memory is allocated to a plurality of ports. The ports are arranged in a spatial ordering. A plurality of various sized data items are temporally ordered in each of the plurality of ports. Each data item includes a time-stamp to indicate the temporal ordering of the plurality of data items. The plurality of data items are atomically accessed by a plurality of threads using space and time coordinates. The space and time coordinates uniquely identify each of the plurality of data items.

Abstract: Data is written to and read from a shared pipe by applications of multiple systems. At least one shared pipe is located within an external shared memory coupled to one or more central processing complexes. Each of the central processing complexes has one or more operating system images, which controls execution of one or more piping applications. At least one piping application corresponding to at least one operating system image writes data to a shared pipe located in the external shared memory and at least one other application corresponding to one or more other operating system images reads data from the same shared pipe, thereby providing cross-system data piping.

Abstract: A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing receive frame data received from a media access controller into the random access memory. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller operating in a separate clock domain to access the status information and the corresponding data frame as a single data unit. Moreover, the disclosed embodiment stores the status information at the beginning of the stored data unit, enabling a controller reading the buffer memory to immediately determine the status of the corresponding stored data frame.

Abstract: A multi-processor system having a shared program memory includes: a plurality of processors; a plurality of local memories which are respectively dedicated to the processors; a global memory which can be accessed by all of the processors; a program memory for storing a program which may be read and executed by each of the processors; a system bus for transferring data between the processors and the global memory, or between the processors and the program memory; and a memory switch for connecting the system bus to the program memory after a system reset, and to the global memory after allocating an identification number of each of the processors. Accordingly, it is easy to implement a multi-processor system in a restricted space area (for example, in a VME system).

Abstract: A method of allocating memory in a multithreaded (parallel) computing environment in which threads running in parallel within a process are associated with one of a number of memory pools of a system memory. The method includes the steps of establishing memory pools in the system memory, mapping each thread to one of the memory pools; and, for each thread, dynamically allocating user memory blocks from the associated memory pool. The method allows any existing memory management malloc package to be converted to a multithreaded version so that multithreaded processes are run with greater efficiency.

Abstract: An updating and reference management system with an area management unit and a timing unit for a shared memory. Processes access the shared memory in an identical time frame, determined by the timing unit, such that update or reference requests by the processes for the shared memory are held by the area management unit in each time interval between control signals generated by the timing unit. The update or reference requests are executed at the time of each control signal. Processing objects manage the update or reference requests for respective portions of the shared memory. The managing objects for the shared memory also pre-process potentially conflicting update requests to the same portions of the shared memory such that the shared memory is updated with different data, determined to be appropriate by the respective managing object.

Abstract: Two or more operating systems to share a same physical memory while operating simultaneously within a hybrid computer system, without requiring modifications to the program code of the operating systems or application programs. One embodiment of the present invention contains circuitry that is located between the operating systems and the physical memory within the hybrid computer system. In operation, these circuits receive a memory request for one of the operating systems together with the specific memory address requested and a signal indicating which operating system originated the memory access request. The circuit determines which operating system the memory access request is performed on behalf of. If the memory request is performed on behalf of predetermined first operating system, the received memory address is translated and sent to the physical memory of the computer system. This translation of the physical address is transparent to the first operating system.

Abstract: A distributed file system with dedicated nodes capable of being connected to workstations at their bus. The system uses a complementary client-side and server-side file caching method that increases parallelism by issuing multiple server requests to keep the hardware devices busy simultaneously. Most of the node memory is used for file caching and input/output (I/O) device buffering using dynamic memory organization, reservation and allocation methods for competing memory-intensive activities.

Abstract: Disclosed are a method and processor external to an automated data storage library for partitioning the data storage library into multiple virtual libraries for access by a plurality of hosts, each host having a host port, the data storage library having a plurality of data storage drives, a plurality of storage slots, a library controller, the library controller identifying each of the data storage drives and the storage slots, a library port coupled to the library controller, and at least one accessing robot controlled by the library controller, comprising the steps of, at a node intermediate the library port and host ports, inquiring of the host ports to identify the number of host ports; inquiring, via the library port, of the library controller to determine the data storage drive identifiers and the total number of the storage slots; identifying by employing the data storage drive identifiers, the data storage drives associated with each host port; and sequentially creating virtual libraries, assigning t

Abstract: A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

Abstract: A method and apparatus for memory allocation in a multi-processor system is accomplished by mapping portions of a shared memory to a first and second processor. The mapping is performed such that either of the processors' portions can be enlarged or reduced based on the memory that is located between the portions allocated to the processors. When a processor requests additional memory and there is sufficient free memory between the processors' respective portions, the appropriate amount of the free memory is allocated to the requesting processor.

Abstract: A portable computing device is described with a file system designed for providing improved data transfer methodology. The file system is implemented as a "Delta Block" File System (DBFS) comprising a file system designed specifically for the purpose of minimal delta calculation and minimum data transfer, particularly for portable storage devices which use solid state storage. The design of the DBFS minimizes the work required to compute changes to files and, hence, allows improved data transfer. Any new, removed, or modified blocks are transferred as changes. A simple checksum, CRC (cyclic redundancy checking), or similar comparison can be used to test a block for changes. Because block modifications are isolated to the proximity of the data change, only these blocks will be involved in a transfer. Furthermore, because the delta calculation is at the block level, it can be performed without knowledge of the data itself, thereby allowing any type of data to be compared and transferred.

Abstract: The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus.

Abstract: A data processor is adapted, in particular with respect to the microcode, in such a way that the execution of standard commands of the processor which are loaded in a user memory area and request reading or writing access to the content of memory cells is inhibited. In the operating system memory area there is a memory area access table, in which there is stored the address area authorized per user memory area for the commands there. Finally, there is an additional program routine which is called up by a command loaded in a user memory area and requesting reading or writing access to a memory cell, and checks by means of the memory area access table (before execution) whether the requested access to a memory cell lies in the authorized address area. If it does not lie in the authorized address area, the additional program routine inhibits the execution of the command.

Abstract: A method and a system are provided for managing fixed size memory blocks in a graphic imaging system. A system memory includes at least one queue containing a linked list of fixed size memory blocks and a page pool of variable size memory blocks. A system memory manager allocates memory blocks from the system memory in response to requests. Upon a request for a memory block of a particular fixed size, the system memory manager allocates a memory block of the fixed size from a queue containing memory blocks of the fixed size if the queue has memory blocks available. If the queue does not have memory blocks available, the system memory manager creates an extension to the queue containing memory blocks of the fixed size. The extension is created from a page pool. The extension is linked to the queue, and a memory block of the fixed size is then allocated from the queue.

Abstract: Processor apparatuses share data, used in common for a plurality of systems, in a global memory in a share system. The global memory is divided into constant units and the individual division units are managed by using identifiers which are definitely determined as viewed from the processor apparatuses and the share system. When an inter-system exclusive state conditioning unit of a processor apparatus designates a desired area on an address space in the processor apparatus by using an identifier to obtain a locked resource, an update state confirming unit checks whether data in a corresponding unit in the share system is updated, and when the data is updated, a data transferring unit transfers the data in the corresponding unit in the share system to the address space. Accordingly, a program operating on each computer system can easily access the data shared by the systems without being aware of the presence of the share system.

Abstract: A shared storage configuration system for use in a computer system includes a plurality of processing modules. Each of the processing modules includes at least a main storage unit, a central processing unit and a connecting unit for connection to a system bus. The shared storage system also includes a plurality of shared storage modules. Each of the shared storage modules includes a shared storage unit and a connection unit for connection to the system bus. A space inherent in the processing modules is accessible by physical addresses of said central processing unit of each of the processing modules. A shared storage space is accessible by the physical addresses of said central processing unit of each of the processing modules.

Abstract: Method and apparatus for a computer system to efficiently operate with multiple instruction processors and input/output subsystem in a symmetrical multi-processing environment. The computer system uses a new storage controller having a high performance interconnect scheme that scales in system performance as additional common storage controller modules are added. The interconnect scheme has the cost advantage of a bus connected system while achieving the performance characteristics of a crossbar connected system.

Abstract: Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

Abstract: A plurality of channel data groups and a coupling data group are supplied to a data input port of a data buffering apparatus so as to be temporarily stored in a buffering memory having a first memory area assigned to a non-coupled channel data group, a second memory area assigned to a coupled channel data group and a third memory area assigned to the coupling data group, and the data buffering apparatus outputs the channel data group from the first memory area or the channel data group and the coupling data group from the second and third memory areas before the next channel data group arrives at the data input port so as to decrease the memory areas of the buffer memory.

Abstract: A RAID storage system which attempts to balance the I/O workload between multiple redundant array controllers is presented. The RAID storage system of the invention utilizes a plurality of redundant array controllers which require static ownership of storage devices for WRITE access requests to the same redundancy parity group. Accordingly, a plurality of storage devices are provided in the system, each of which is owned by one of the redundant array controllers. Each storage device is coupled to both its owner controller and at least one other array controller. Each array controller coupled to a storage device has the ability to read and write data from and to the storage device. Each array controller has a processing queue from which pending read and write access requests are removed and then processed one at a time by the controller. A host computer is provided for dispatching read and write access requests to the redundant array controllers.

Abstract: Microkernel memory references, traditionally required to refer to memory by exact physical address, are transformed so as to be able to map the references to addresses in multiple memory nodes. As a result, each node's address space may be compiled to by multiple microkernels. Reverse mapping responsive to coherency requests facilitates cache coherency.

Abstract: A computer system includes a memory requester that interfaces with a memory module that includes memory portions. A remapping table that maps each of the defective memory portions to a respective non-defective memory portion in the memory module is created and then stored. Also, a usage table that maps each of a subset of the defective memory portions to a respective non-defective memory portion is created and stored. The defective memory portions of the subset are selected based on which defective memory portions have been most recently used, i.e., requested. In response to receiving from the memory requester a request for access to a requested memory portion of the memory module, a determination is made whether the requested memory portion is one of the defective memory portions mapped in the usage table or remapping table.

Abstract: A data transfer apparatus for DMA-transferring stream data between a memory and each of n ports.

Abstract: A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction.

Abstract: A computer system having a processor and at least one peripheral has a programmable shared memory system and method that selectively dedicates a first potion of memory to use by the processor and allocates a second portion of memory to shared use by the processor and any peripherals in the system. The programmable memory architecture is implemented using a dual bus architecture having a first-bus connected to the processor and a second bus coupled to the processor by a system controller and to the peripherals by a peripheral controller. The programmable memory architecture additionally has a configuration controller coupled to each configurable memory bank in the system. Each configuration controller is additionally coupled to both the first and second buses. Under programmed control, the each configuration controller couples the associated memory to either the first or second bus, responsive to configuration information stored in the system controller.

Abstract: A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number. The location in the cache of an item that includes a first key is determined by supplying the first key to a lockless-lookup engine which then provides a lookup output that is alternatively a lookup entry number or an indication that the item is not stored in the cache. The lookup entry number is alternatively a first or second entry number, wherein the first entry number points to a first entry in which the item is stored and the second entry number points to a second entry in which the item is not stored. If the lookup output is the lookup entry number, then it is verified that the lookup entry number is the first entry number.

Abstract: A method of transferring messages between a plurality of processes that are communicating with a data storage system, wherein the plurality of processes access the data storage system by using I/O services. the method includes the steps of configuring the data storage system to provide a shared data storage area for the plurality of processes, wherein each of the processes is permitted to access the shared data storage region; when a sending process sends a new message that is intended for a recipient process, sending that new message to the data storage system; storing that new message in the shared data storage region; in response to an action initiated by the intended recipient process, retrieving that new message from the shared data storage region; and further in response to the action initiated by the intended recipient process, sending the retrieved message to the intended recipient process, wherein the sending and intended recipient processes are among the plurality of processes.

Abstract: A serial data interface device is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers, etc. The interface includes first and second ports capable of receiving and transmitting information to respective electronic devices, and first and second storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first and second ports and are coupled to another electronic device. Included in each storage device is a main memory that is coupled to at least one of the electronic devices and at least one of the ports. A control memory that is coupled to the main memory is also included, along with a main memory arbiter that is coupled to the control memory and the main memory. Further included is a buffer allocation control that is coupled to the at least one electronic device and at least one of the ports.

Abstract: Multiple banks associated with a multiple set associative cache are stored in a single chip, reducing the number of SRAMs required. Certain status information for the second level (L2) cache is stored with the status information of the first level cache. This enhances the speed of operations by avoiding a status look-up and modification in the L2 cache during a write operation. In addition, the L2 cache tag address and status bits are stored in a portion of one bank of the L2 data RAMs, further reducing the number of SRAMs required. Finally, the present invention also provides local read-write storage for use by the processor by reserving a number of L2 cache lines.

Abstract: To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

Abstract: A memory in a computer system includes a visible portion and a hidden portion. The visible portion of the memory is addressable by a processor and the operating system operating within the computer system. Addressability by either the processor or the operating system is excluded to the hidden portion of the memory. The hidden portion of the memory is used for storing data transmitted by either the processor or the operating system. A communications area, located in the visible portion of memory receives requests for data access from either the processor or the operating system. A hidden server which addresses both the visible portion of memory and the hidden portion of memory receives requests for data access from the communications area and initiates data access from the hidden memory.