Abstract: A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a number of windows, each window being associated with a number of physical blocks. The redundant reserved region includes a dynamic-link area, a window-information area, a dynamic-link information area, and an boot-information area; wherein the dynamic-link area includes a plurality of dynamic allocation blocks, each being allocatable to any window. The window-information area is used to store a specific window-information set that is dedicated to a certain window within a specific range of data storage space. The dynamic-link information area is used to record the status of the allocation of the dynamic allocation blocks to the windows.

Abstract: An address access control system dynamically forms a plurality of address ranges in a predefined unified address structure during operation of a computer system. A plurality of memory clients is operatively connected to the unified address structure. A plurality of capabilities is also provided with respect to memory clients accessing address ranges. A memory controller is operatively connected to the plurality of memory clients and to the unified address structure. The memory controller dynamically structures an association of a respective range of the plurality of ranges with at least one respective capability of a plurality of capabilities for at least one memory client of the plurality of memory clients.

Abstract: The present invention is directed to methods and systems for allocating bandwidth (or other shared resource) among multiple masters. According to an aspect of the present invention, an arbiter assigns a bucket to each CPU (or other device) where each bucket holds the credits for that CPU. Each bucket has a predetermined fill rate and a drain rate. Depending on the priority given to a particular CPU, the corresponding bucket will drain (or fill) at a particular rate. For example, CPUs with a higher priority will drain at a slower rate. For each clock tick (or other period of time) that a CPU is stalled, a number of credits is accrued. The bucket with the highest number of credits has priority and will be given access to the shared resource (e.g., DRAM, SDRAM, SRAM, EPROM, etc.).

Abstract: A data block format for streaming information includes a first data block size field and a second data block size field, each of the fields indicating the size of the data block. A payload field is bounded by the first data block sized field and the second data size in the data block format.

Abstract: The present invention is directed to a multi-port memory device responsive to two systems. The device includes an array of memory cells each represented by a unique row and column address. The memory device has first and second input/output ports and an input/output control circuit, responsive to the first and second input/output ports, for writing data into and reading data of the array. The device further includes a first signal decoder responsive to the first system for producing first signals for accessing a cell within said array. The device also includes a second signal decoder responsive to the second system for producing second signals for accessing a cell within the array. A control circuit is responsive to the first and second systems for identifying which of the systems is entitled to access to the array in the event both systems seek access to the same address at the same time.

Abstract: A memory manager, method and computer system that allows use of Extended Upper Memory Block (XUMB) memory space by system BIOS to store runtime code and data. In an exemplary memory manager, BIOS Power-On-Self-Test (POST) code sets up or allocates 1 the XUMB memory space at TP_SETUP_WAD (0D3h). The BIOS code finds space for the XUMB memory space in an extended memory space. The BIOS code then zeroes out the XUMB memory space and stores the address of the XUMB memory space in a variable. When different components of the BIOS code need to reserve memory in the XUMB memory space, they call a predetermined calling function. The calling function reserves memory for each of the different components in the XUMB memory space and allocates pointers to the specific addresses that may be used by these components. The BIOS components then copy their own data into these memory locations of the XUMB memory space.

Abstract: A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Abstract: A computer system having a host computer is connected to a disk drive for providing a key to enable a feature controlled by the disk drive. The disk drive validates the key using private validation means which are accessed by a disk drive microprocessor. The validation means include drive-dependent identification means which are used to derive a seed for generating an internal key to validate the key provided by the host computer. An exemplary feature enabled by the key validation is an expansion area of the disk drive which is enabled to provide extended user data storage without requiring internal physical access by the user.

Abstract: The present invention provides an ATAPI command receiving method in which the CPU 72 can quickly correspond to other processings without expending much time for capturing data, as well as it can be prevented that data which are being captured by the CPU should be destroyed. In this ATAPI command receiving method, when an ATAPI protocol control LSI 71 comprising a shared register storage area 711 (including a data FIFO 7112 for containing command packets) for receiving a command from the host computer via an ATA bus 2, and a buffer memory 712 which can be used as a RAM of a CPU 72 receives a command, shared register values (including a command packet value) are stored at a storage destination address in the buffer memory 712 which is designated by the CPU 72, when the data storage permission is given by the CPU 72.

Abstract: A method and apparatus is provided for measuring and optimizing the orientation of data access of an electronic storage device according to data access characteristics. Monitoring storage access activity in an area of storage space is performed to gather data pertaining to one or more storage access characteristics. Measuring is performed of the characteristics of the storage access activity of at least two individual portions of the storage space. The portions are then combined in a manner to more judiciously utilize storage space. Depending on their homogeneity of access characteristics, the individual portions may then be left alone, merged with other similar portions, or further subdivided into sub-portions, which may be further merged, divided or left alone. At each merger or division determinations can then be made of whether the characteristics of storage access activity of one individual portion or sub-portion are similar to that of another portion according to predetermined criteria.

Abstract: An apparatus for allocating data usage in an embedded dynamic random access memory (DRAM) device is disclosed. The apparatus for allocating data usages within an embedded dynamic random access memory (DRAM) device comprises a control analysis circuit, a data/command flow circuit, and a partition management control. The control analysis circuit generates an allocation signal in response to processing performances of a processor. Coupled to an embedded DRAM device, the data/command flow circuit controls data flow from the processor to the embedded DRAM device. The partition management control, coupled to the control analysis circuit, partitions the embedded DRAM device into a first partition and a second partition. The data stored in the first partition are different from the data stored in the second partition according to their respective usage. The allocation percentages of the first and second partitions are dynamically allocated by the allocation signal from the control analysis circuit.

Abstract: A multi-processor system includes a global bus (14) having associated therewith a global address space with a plurality of processor nodes (10) associated therewith. Each of the processor nodes (10) has a CPU (20) associated therewith which interfaces with a local bus. The local bus has a local address space associated therewith. A dual port SRAM (DPSRAM)(34) is provided for interfacing between the global bus (14) and the local bus (30). Each DPSRAM (34) for each processor core (10) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node (10), it is only necessary to address the designated DPSRAM (34) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU (20) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM (34).

Abstract: An optimizing tool optimizes a computer system's page space by basing the page size on the amount of real memory in the computer system. The optimization tool determines the amount of real memory in the computer system. The amount of memory is multiplied by a multiplier to determine an optimal amount of page space to allocate. In one embodiment the multiplier used is two (2) so that the amount of page space is double the amount of real memory. The optimal page space is compared with the amount of page space currently allocated in the computer system. If more page space is needed, the optimization tool determines where on the computer system's disk space the additional page space should be added. In a UNIX embodiment, the optimization tool determines whether a non-root volume group exists on the system. A non-root group without a paging space is examined for a new paging space addition. If a non-root group is found, the paging space needed is added to the non-root group.

Abstract: Systems and methods are described for multiple block sequential memory management. A method includes: partitioning a block of memory into a plurality of shared memory segments; and providing a processor with accessibility to each of the plurality of shared memory segments. An apparatus includes: a computer system; a block of memory including a plurality of shared memory segments; and a processor.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: A method and implementing computer system is provided for the creation of large numbers of threads in a computer system. An exemplary embodiment supports up to sixteen segments in memory of thread private data for each process or application program running on the system. Each segment contains support for 2K threads. These segments are identified in process' user structure which is located in the process private data segment of memory allowing cleanup collection on a per-segment basis. The thread's private data is composed of two parts, viz. its private kernel thread stack (96K) and uthread data structure. The uthread contains the individual data fields that are referenced only by the thread, including the register save area for the thread.

Abstract: A computer system and corresponding method for supporting a compressed main memory includes a processor, a processor cache in signal communication with the processor, a memory controller in signal communication with the processor cache, a compression translation table entry register in signal communication with the processor cache and the memory controller, a compression translation table directory in signal communication with the compression translation table entry register, and a compressed main memory in signal communication with the memory controller wherein the memory controller manages the compressed main memory by storing entries of the compression translation table directory into the processor cache from the compression translation table entry register; where the corresponding method includes receiving a real address for a processor cache miss, finding a compression translation table address for the cache miss within the processor cache, if the cache miss is a cache write miss: decompressing the memor

Abstract: A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.

Abstract: A distributed computer system is disclosed that allows shared memory resources to be synchronized so that accurate and uncorrupted memory contents are shared by the computer systems within the distribute computer system. The distributed computer system includes a plurality of devices, at least one memory resource shared by the plurality of devices, and a memory controller, coupled to the plurality of devices and to the shared memory resources. The memory controller synchronizes the access of shared data stored within the memory resources by the plurality devices and overrides synchronization among the plurality of devices upon notice that a prior synchronization event has occurred or the memory resource is not to be shared by other devices.

Abstract: A memory access architecture and technique employs multiple independent buffers that are configured to store items from memory sequentially. The memory is logically partitioned, and each independent buffer is associated with a corresponding memory partition. The partitioning is cyclically sequential, based on the total number of buffers, K, and the size of the buffers, N. The first N memory locations are allocated to the first partition; the next N memory locations to the second partition; and so on until the Kth partition. The next N memory locations, after the Kth partition, are allocated to the first partition; the next N locations are allocated to the second partition; and so on. When an item is accessed from memory, the buffer corresponding to the item's memory location is loaded from memory, and a prefetch of the next sequential partition commences to load the next buffer.

Abstract: Disclosed is a method and hard disk configuration for accommodating different sizes of applications during an automatic re-provisioning of an appliance server. The disk drive of the appliance server is partitioned with a system partition, a network operating system (NOS) partition, a float partition, and an images partition. The float partition is utilized to provide additional space to the NOS partition and the images partition, when required. A re-provisioning utility is provided, which initiates both a create image utility and an apply image utility, whereby an image file of a current application and associated operating system is created and a stored image file of a second application is installed on the appliance server. When the apply image utility is initiated, the NOS partition is dynamically extended into the float partition server if the second application requires more space than is provided in the NOS partition.

Abstract: A processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that stores configuration settings. The configuration settings include a plurality of subsystem memory range settings defining memory zones. The access transaction also includes access information. A multi-memory zone access checking circuit, coupled to the configuration storage, checks the access transaction using at least one of the configuration settings and the access information. The multi-memory zone access checking circuit generates an access grant signal if the access transaction is valid.

Abstract: A method, system and computer program product for sharing an Integrated Device Electronics (IDE) drive among server blades in a dense server environment. By logically partitioning the IDE drive, where each logical partition is associated with a particular server blade, the IDE disk may be shared among multiple server blades in the dense server environment.

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract: An LU decomposition is carried out on a block E and H. Then, a block B is updated using an upper triangular portion of the block E, and a block D is updated using a lower triangular portion of the block E. At this time, in an LU decomposition, blocks F and I have been updated. Then, using the blocks B, D, F, and H, blocks A, C, G, and I are updated, an upper triangular portion of the block E is updated, and finally, the blocks D and F are updated. Then, the second updating process is performed on the block E. Using the result of the process, the blocks B and H are updated. Finally, the block E is updated, and the pivot interchanging process is completed, thereby terminating the process. These processes on the blocks are performed in a plurality of divided threads in parallel.

Abstract: A security-enhanced network storage device. Apparatus and methods disclosed which allow network-connected client systems or groups of such systems to access data storage devices over the network in a highly secure fashion. Systems not having the appropriate permission are excluded from access. Characteristics of such a network attached storage device include the following: (1) Clients can only access the data they have been given permission to access, based on a combination of access control lists and physical system interconnects. (2) Client data access permissions in representative embodiments are stored and managed on the security-enhanced network attached storage device and are not accessible by clients, thereby improving data security. (4) Client access permissions can be checked on a per-IP-packet basis, so that all data transfers can be validated before they occurs, thus also, improving data security.

Abstract: A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.

Abstract: An embedded microprocessor two level security system in flash memory. The memory includes an address input and a memory space of addressable locations having a restricted area and a user area. Addressing one of a the addressable locations therein results in the output of information therefrom in response to the receipt of an associated address on the address input. A logic device is provided for determining if a received address on the address input corresponds to an attempt to access an addressable location in the restricted space for output of information therefrom as the result of execution of a program instruction from the user area by an external processor.

Abstract: Memory sharing techniques include providing a first device and one or more additional devices. Each device has a memory and is configured to be connected to a network. A portion of the first device memory is allocated, and may be divided into two or more first device memory segments. Each first device memory segment corresponds to a device, and at least one of the first device memory segments corresponds to an additional device. A portion of the additional device memory is allocated, and may be divided into two or more additional device memory segments. Each additional device memory segment corresponds to a device, and at least one additional device memory segment corresponds to the first device. A first device data segment is provided to the additional device, and a first device data validity indication is derived at the additional device.

Abstract: A formalized method for part of the design decisions, related to memory, involved while designing an essentially digital device is presented. The method shows how to traverse through and how to limit the search space being examined while solving these memory related design decisions. The method focuses on power consumption of said essentially digital device. A method for determining an optimized memory organization of an essentially digital device, wherein data reuse possibilities are explored, is described.

Abstract: A method, system and program for controlling access to memory areas within a computer are provided. The invention comprises placing a first Bind Work Queue Element (WQE) at the head of a work queue, wherein the first Bind WQE defines parameters associated with a first Memory Window. A set of Work Requests is then placed on the work queue, behind the first Bind WQE wherein the work requests invoke operations that access the first Memory Window. A second Bind WQE is then placed on the work queue, behind the first set of Work Requests. This second Bind WQE defines parameters associated with a second Memory Window. A second set of Work Requests is placed on the work queue behind the second Bind WQE and invoke operations that access the second memory window. The Memory Windows can be associated with a common Memory Region and have different addresses and lengths or different access rights. In another embodiment, the first and second Memory Windows can be associated with different Memory Regions.

Abstract: A method and apparatus including a plurality of data processing units. A plurality of memory banks having a shared address space are coupled to the processors by a crossbar coupling to enable reading and writing data between the processors and memory banks. A unidirectional network couples the memory banks and the processors to enable cache coherency messages to be transmitted from the memory to the processors. A plurality of semaphore registers are implemented within the shared address space of the memory banks wherein the semaphore registers are accessible by the processors through the crossbar coupling.

Abstract: A high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades is disclosed. The system comprises multiple processing elements, each processing element capable of accessing memory at processing element memory addresses; and multiple memory modules each having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space. The system further includes a memory element interface in communication with each of the memory elements permitting alteration of the defined address space for the memory element. An address mapper is interconnected between each of the processing elements and at least one of the memory elements. The address mapper is capable of mapping a processing element memory address to a global memory address within a defined address space.

Abstract: The present invention is related to methods and systems for providing different stripe sizes for different zones for at least a first of a plurality of mirrored drives to improve data rates. The first drive has a plurality of zones. In one embodiment, a first stripe size is selected for a first zone, and a second stripe size is selected for a second zone. The said second stripe size is different than said first stripe size.

Abstract: A method, system, and computer program product for enforcing logical partitioning of a shared device to which multiple partitions within a data processing system have access is provided. In one embodiment, a firmware portion of the data processing system receives a request from a requesting device, such as a processor assigned to one of a plurality of partitions within the data processing system, to access (i.e., read from or write to) a portion of the shared device, such as an NVRAM. The request includes a virtual address corresponding to the portion of the shared device for which access is desired. If the virtual address is within a range of addresses for which the requesting device is authorized to access, the firmware provides access to the requested portion of the shared device to the requesting device. If the virtual address is not within a range of addresses for which the requesting device is authorized to access, the firmware denies the request.

Abstract: An open format storage subsystem and method are provided. The storage subsystem and method include at least one host endnode, at least one processing unit endnode, and at least one storage endnode. These endnodes are partitioned according to partition tables assigned to the ports of the endnodes and partition keys assigned to queue pairs of the ports. Based on these partition keys, partitions in the storage subsystem are designated. In this way, certain endnodes may be designated as being able to communicate with only certain other ones of the endnodes. Because of the partitioning mechanism of the present invention, an open format storage subsystem is formulated such that the types of endnodes in the storage subsystem are not limited to vendor specific units. This enhances the ability to add and remove units from the storage subsystem by removing the limitations typically found in closed storage subsystems.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: The invention is directed to a system for managing storage of an object in a storage system having a plurality of different storage media divided into different partitions, which includes a storage processor for determining whether a particular storage partition has reached a predetermined capacity threshold; a data migration processor for identifying within the particular storage partition an object to be moved and for identifying a target destination partition for the particular object in response to the capacity determination, the migration processor identifying the target destination partition based on one or more selected from the group consisting of (a) media type of the particular storage partition, and (b) information identifying related objects in the target destination partition; and a transfer processor for transferring data representing the particular object to the target destination partition.

Abstract: A method and apparatus for combining cost effectiveness of data signal ports sharing a common memory storage device with reliable data signal communication of data signal ports each having a dedicated memory storage device. In one embodiment, data signals are received at a number of data signal ports of a data signal communication platform. A data signal bandwidth capability of a memory storage device of the data communication platform is determined. Once the data signal bandwidth capability of the memory storage device is determined, the memory storage device is segmented to improve utilization of the data signal bandwidth capability. As a result, cost effectiveness of data signal ports sharing a common memory storage device and reliability of data signal communication of data signal ports each having a dedicated memory storage device is combined.

Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: There is provided a method for representing unvalues in an unvalue-unaware memory of a computer processing system. The method includes the step of selecting arbitrary bit combinations to represent the unvalues, upon startup of the system. Upon performing a read operation from the memory, a read value is interpreted as an unvalue, when the read value matches at least one of the bit combinations. Upon performing a write operation to the memory, a value-unvalue-collision exception is raised, when a valid value is written to the memory and the valid value matches at least one of the bit combinations.

Abstract: A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to an MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether an MSR address is within a valid range.

Abstract: Methods and apparatus for the efficient allocation of shared memory in a multi-threaded computer system are disclosed. In accordance with one embodiment of the present invention, a computer-implemented method for allocating memory shared by multiple threads in a multi-threaded computing system includes partitioning the shared memory into a plurality of blocks, and grouping the multiple threads into at least a first group and a second group. A selected block is allocated to a selected thread which may attempt to allocate an object in the selected block. The allocation of the selected block to the selected thread is based at least partially upon whether the selected thread is a part of the first group or the second group. In one embodiment, grouping the multiple threads into the first group and the second group includes identifying a particular thread and determining whether the particular thread is a fast allocating thread.

Abstract: The wireless communication apparatus has a flash memory in which a plurality of sectors are formed to make partitions so that at least two of the sectors are allocated for storing the positional record information. The positional-record information is stored in one of the at least two allocated sectors, whereas at least one of the remaining sectors are controlled so as to be used as an empty sector storing no information. When positional-record information for updating is given, the information is updated and stored in at least one of the remaining sectors, that is, in the aforementioned empty sector. After updating and storing of the information is completed, the information stored in the sector storing the pre-update positional-record information is eliminated.

Abstract: A symmetric multiprocessor (SMP) of hierarchical connection realizing an inter-partition shared memory has at the gateway of an inter-node connection switch from each node, a translator for translating an address of an access command for an area shared between partitions, between a real address used in a partition and a shared area address used in common between partitions. Thereby, the address of a local area of each partition is freely set, and cache coherent control of a shared area is conducted at high speed by using a snoop command of the hierarchical connection SMP. Fault containment between partitions is realized by checking conformity between the address of the access command issued from another partition and the shared area configuration. Nodes included in other partitions may be reset from each partition. In addition, the configuration information of the shared area between partitions may be dynamically modified.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: A method for a user process to specify a policy for allocating pages of physical memory on the nodes of a multinode multiprocessor computer system. Through means such as a system call, an application program can specify to the operating system that physical pages of memory for an application-specified portion of virtual address space are to be physically allocated upon a specified set of nodes, subject to the additional selection criteria that the pages are to be allocated at first reference upon: 1) the node upon which the reference first occurs; 2) the node which has the most free memory, or 3) that the pages should be evenly distributed across the indicated set of nodes. In effect, the operating system remembers the specified allocation policy and node set from which the physical pages can be subsequently allocated as established by a system call. Subsequent use of the virtual address space for which the allocation policy is defined results in the memory being allocated accordingly.

Abstract: A computer system having bus controller operating code stored in a non operating system managed, extended portion of system memory. In one example, the operating code is executed by a bus controller for a computer bus conforming to the Universal Serial Bus (USB) specification. In one example, the bus controller operating code is stored in a portion of system memory that is located above the top system memory address reported to the operating system, thereby hiding the stored code from the operating system. In one example, the bus controller operating code is constructed during the startup of the computer system with a code construction routine. Storing bus controller operating code in a non operating system managed, extended portion of system memory provides a computer system greater flexibility in system memory usage.

Abstract: A method for transmitting a data of a disk recording medium including: a first step of reading file management information for managing a data recorded in a file structure in a disk recording medium; a second of storing the read file management information in a storing unit different to the recording medium; and a third step of reading and transmitting a corresponding file management information as stored in the storing unit when the file management information is requested. By doing that, the file management information that is frequently requested to be transferred, such as a file system data managing a data in a file structure recorded in a disk recording medium such as a CD-ROM, is stored in a specific storing area so as to be quickly read and transmitted to a connected instrument such as a personal computer, without performing a tracking servo operation to drive a sled motor. Thus, the transfer rate of the optical disk driver such as the CD-ROM can be highly improved.