Abstract: In a data storage subsystem providing data storage to host processors, a process of configuration defines a subset of the data storage that each host may access. A vector specification is a convenient mechanism for specifying a set of storage volumes that a host may access. For example, for each host processor, there is stored in memory of the data storage subsystem a list of contiguous ranges or vectors of the storage volumes that the host may access. To determine whether or not a specified logical volume number is included in the vector, a mudulus of the stride of the vector is computed from the difference between the address of the specified logical volume and the beginning address of the vector, and the modulus is compared to zero. To provide a mapping between logical unit numbers specified by the host and the logical volumes, a contiguous range of logical unit numbers may also be specified for each contiguous range or vector of storage volumes.

Abstract: A circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.

Abstract: A storage control apparatus is coupled to a central processing unit (CPU) and a storage unit to control input/output of data between the CPU and the storage unit. The storage control apparatus has at least two processors coupled to the CPU and the storage unit, a cashe memory (CM) unit for temporarily storing data of the storage unit, a shared memory (SM) unit for storing information concerning control of the CM unit and the storage unit, and a selector coupled to the at least two processors, the CM unit and the SM unit through access paths to selectively apply access requests from the at least two processors to the CM unit and the SM unit.

Abstract: A method, system, and computer program product for testing enforcement of logical partitioning in a data processing system is provided. In one embodiment, a call to an interface routine of a logical partitioning enforcement software unit is generated and sent to the logical partitioning enforcement software unit. A reply is received from the logical partitioning enforcement software unit and compared with an anticipated reply. Responsive to a discrepancy between the reply and the anticipated reply, a user is notified of a problem, thus allowing the user to take appropriate actions to correct the problem.

Abstract: A system and method for more flexibly managing flash memory devices, such that these devices can be more efficiently used to store data as flash disks. The present invention provides an improvement over background art methods by enabling erase units of different sizes to be erased. Preferably, the present invention is also operative with flash memory devices which are capable of erasing the memory in a plurality of different erase unit sizes, and more preferably, is able to select the most efficient erase unit size for erasing. The present invention is able to optionally and more preferably use a plurality of different decision rules in order to select the most efficient method for erasing and/or reading/writing data to the flash memory device. Most preferably, the present invention is able to detect the capabilities of the flash memory device, in order to be automatically operative with a plurality of different types of flash memory technologies.

Abstract: A method of performing multiple operations on a flash memory device is described. This is made possible through the implementation of multiple partitions within the flash memory. The partitions are used to store data, application code, and system code. Low level functions within the system code process the data and handle preemption functions within the flash memory.

Abstract: A drive apparatus wherein a plurality of media each including a memory element can be successively accessed to continuously write and/or read out data into and/or from the media includes a loading device for loading a plurality of storage media such that data are individually written into and/or read out from the storage media, an accessing circuit for accessing the storage media loaded in the loading circuit to write and/or read out the data into and from the storage media, and a controller for controlling, when the plurality of storage media are loaded in the loading circuit, the accessing circuit to continuously perform writing into and/or reading out from the plurality of storage media loaded in the loading circuit.

Abstract: A system includes shared Small Computer System Interface (SCSI) storage devices for processing clients coupled by a fiber channel interface. The storage devices include storage blocks, and locks controlling their use by clients. Clients issue actions to the storage devices for performing operations on the locks. A client may exclude other clients from using storage blocks using a state element to acquire the lock for shared or exclusive use. If the client modified the data, a version counter in the lock is updated when the lock is released. If an activity bit is set, the version counter is updated upon both reading and writing. Other clients can forcibly release a lock owned by a failed client by monitoring its version counter. Expiration timers associated with the locks allow acquired locks to be released by timing out. A serverless global file system (GFS) manages use of the shared storage resources, and allows remapping of the locks to the storage blocks, for example, based on activity of the locks.

Abstract: In a memory rewriting apparatus, it is confirmed first that a check program is present at a head address of a storage area in a flash ROM of a microcomputer in an ECU for storing an application program, when it is determined by a boot program in the flash ROM that the application program is to be executed. The processing proceeds to the application program after the execution of the check program. Thus, it will not occur that the processing jumps to the application program when the application program is not present. As a result, erroneous operation of the ECU due to an erroneous execution of the program can be prevented.

Abstract: A method for performing garbage collection of memory objects in a memory heap, the method includes the steps of partitioning the heap into old and new generations. There follows the step of applying an on-the-fly garbage collection to memory objects in the young generation, whilst running simultaneously a program thread.

Abstract: Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.

Abstract: When a write access is received from an upper apparatus, a cache control unit develops write data into a data buffer area in a memory, notifies the upper apparatus of a normal end, and thereafter, writes the write data developed into the data buffer area onto a storing medium. An access kind discriminating unit analyzes whether the write access from the host is a sequential access or a random access. A buffer construction control unit selects a data buffer construction of the optimum number of sections in accordance with an access kind and executes the caching operation.

Abstract: A location-centric library host manages cartridge movement according to functional storage addresses and functional I/O addresses. In reality, the library has multiple data storage cartridge receiving slots, which include physical I/O slots and physical storage slots. In contrast with the physical I/O slots and physical storage slots, functional I/O addresses and functional storage addresses are virtual locations used by the host in managing cartridge locations. Thus, host knowledge of cartridge locations is limited to their functional addresses. The library includes a library map that correlates functional addresses with physical addresses. The library automatically empties new cartridges from the physical I/O slots into physical storage slots, using various steps. First, the library hardware automatically recognizes external placement of cartridges into the physical I/O slots.

Abstract: A method and apparatus for sharing memory in a multiprocessor computing system. More specifically, this invention provides a number of system buses with each bus being connected to a respective memory controller which controls a corresponding partition of the memory. Any one of the processors can use any one of the system buses to send real addresses to the connected memory controller which then converts the real addresses into physical addresses corresponding to the partition of memory that is controlled by the receiving memory controller. The processors can be dynamically assigned to different partitions of the memory by via a switching mechanism.

Abstract: A computer system has a host computer coupled to a disk drive having a host interface subsystem. The host interface subsystem includes a user partition, a drive management partition, and a disk-drive-selected application partition. The user partition stores data for execution by the host computer. The drive management partition stores data for execution by the disk drive. The disk-drive-selected application partition stores data for execution by the host computer in response to a drive-determined condition. The host interface subsystem further includes a user command interface that processes commands for storing data in the user partition, a first drive command interface that processes commands for storing data in the disk drive management partition according to a first disk-drive command protocol, and a second drive command interface that processes commands enabling data storage in the application partition according to a second disk-drive command protocol.

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.

Abstract: For reasons of flexibility, efficiency and costs, more and more processes are monitored with the aid of software-controlled electronic devices. As a rule, these are electronic devices that are controlled with the aid of microprocessors. The invention presented herein is aimed at increasing the reliability of these systems and, simultaneously, reduce the expenditure for developing these systems. A processor-monitoring unit is provided for this, which ensures a robust partitioning. This processor monitoring unit controls access to the memory and makes sure that the times for processing program segments and modules are observed.

Abstract: A multistream data packet transfer apparatus and method receives data for at least one stream of multistream data from multiple fragments of memory, over a bus from a first processor. The first processor stores multistream data in the fragmented memory. An interface controller, such as any suitable logic and /or software, evaluates the received data to determine which received data is usable data for a second processor. A data packer removes unusable data and packs the usable data in fixed sized units to form a data packet for the second processor. The data packer packs data received from different fragments of memory as a single packet for use by a DSP requesting the information.

Abstract: The present invention discloses a method and apparatus for viewing and modifying the cache when accessing and processing audio file data from a server. By modifying the cache during transmission of the audio file data such that the cache is never completely depleted of the data, superior sound quality is achieved and without significant gaps in transmission.

Abstract: In a shared memory system, a plurality of requesters issue requests for particular memory addresses over a system bus. Requests, if denied, are later reissued after a controlled reissue delay. The reissue delay for a particular request is controllably varied in response to the number of requests being issued by requesters other than that which issued the request. Typically, the number of requests issued by other requesters for a common memory address as the particular request is tracked, and the reissue delay is controllably increased as the number of such requests increases. As such, the frequency that requests for highly contended memory addresses (which are more likely to be denied) is decreased relative to requests for less contended addresses, thereby freeing bandwidth on the system bus for requests that are more likely to be granted.

Abstract: A method, system, and computer program product for reducing false sharing in a distributed computing environment, and in particular to a multi-processor data processing system. A method is proposed to define a virtual address range, within the system memory available to the processors, which will have a finer granularity than the default page size. These smaller sections, called “sub-pages,” allow more efficient memory management. For example, a 64 Kilobyte range may be defined to have a 512 byte granularity rather than 4 Kilobytes, with each 512-byte sub-page capable of being separately managed.

Abstract: The present invention provides an apparatus, method and computer program product for privatizing operating system data. With the apparatus, method and computer program product of the present invention, a block of memory is allocated and divided into identical, smaller, properly aligned storage areas, each dedicated to a single processor in a multiprocessor system. The storage areas are allocated either initially when the system is initialized or on an as needed basis. Each sub-allocation request is made to use storage at the same location relative to the start of that processor's storage space. Because each processor's storage is isomorphic to all other processors, only one allocation record for all processors is needed, thereby reducing the overhead of the data privatization scheme. By allocating memory in this manner, cache line contention is minimized.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: A multiprocessing system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote node's memory. A cluster protection mechanism is employed within a system interface of the remote node. The system interface, which is coupled between the global interconnect network and a local bus of the remote node, includes a memory management unit, referred to as a cluster MMU, including a plurality of entries which are selectable on a page basis. Depending upon the particular address of a received global transaction, an entry within the memory management unit is retrieved. The entry includes various fields which may be used to protect against accesses by unauthorized nodes, and to specify the local physical address to be conveyed upon the local bus.

Abstract: The present invention provides fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions. The entire system may be executed as a single coherence domain regardless of partitioning, and the general memory access and cache coherency traffic are distinguished. All memory access is intercepted and processed by the memory controller. Before data is read from or written to memory, the address is verified and the executed operation is aborted if the address is outside the memory regions assigned to the processor in use. Inter cache requests are allowed to pass, though concurrently the accessed memory address is verified in the same manner as the memory requests.

Abstract: A method for routing an input/output request for a particular logical volume. In a preferred embodiment, partitions are assigned to logical volumes, wherein an arbitrary number of partitions can be assigned to a logical volume and the partitions can be of an arbitrary size. Each logical volume is divided into a plurality of zones, wherein the zones for a particular logical volume are substantially equal in size. A zone table is created whose entries contain data about one or two partitions that correspond to that zone. Responsive to receiving an input/output request directed to a logical volume, the zone table entries for a first and a last sector listed in the input/output request are used to determine to which partitions in the logical volume the input/output request should be routed.

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).

Abstract: An apparatus, program product, and method perform address translation on a process-local, rather than system-wide, basis in a single-level store virtual memory management system using a plurality of process-local address translation data structures that are individually associated with particular software processes executing on a computer. By performing address translation on a process-by-process basis, many of the security concerns associated with system-wide address translation, e.g., attempting to access a virtual address for memory that has not been allocated for the associated process, are significantly reduced from the standpoint of accessing an address translation data structure, since it can be presumed that all of the information in a process-local address translation data structure was previously authorized for the process when added to the data structure.

Abstract: A disk controller system includes a microprocessor, a hard disk controller, a disk channel path, a host communications path, and an interface coupled to each of the microprocessor, hard disk controller, disk channel path and host communications path. A unified non-volatile memory is coupled to the interface that has a plurality of memory spaces. A memory space is allocated for each of the microprocessor, hard disk controller, disk channel path and host communications path. Each memory space is separated from another memory space by a programmable memory space boundary. The microprocessor, hard disk controller and the unified memory are all fabricated on a single substrate.

Abstract: A memory allocator provides a cache blocks private to each thread of a multi-threaded application, and thereby minimizes performance losses associated with mutual exclusion (MUTEX) contention, MUTEX locking and/or coalescence operations. The memory allocator maintains thread local cache slots in a linked list of arrays. Upon a memory allocation request from a thread, blocks of the memory, which ordinarily require MUTEX locking, are cached in the local thread cache slot allocated to the requesting thread, and the request is satisfied from the cache slot allocated to the requesting thread. Each cache slot is private to the thread to which it is assigned, and thus does not require MUTEX locking. Further, the cache slots do not require defragmentation thereof, and thus require no coalescence operations. Thus, the performance of the multi-threaded application program is optimized.

Abstract: A data storage library utilizes library-local features to regulate access to shared read/write drives among multiple hosts, and thereby avoid the need for arbitrating host software. The library includes multiple data storage media, multiple data storage media slots, multiple read/write drives, and a library controller. The slots are originally partitioned into multiple logical libraries. Normally, the library shares the read/write drives among all hosts. However, when a host submits a request to unload a cartridge from a read/write drive, the library only honors that request if the host has access rights to the logical library from where the cartridge was originally loaded. Similarly, for each slot, the controller prevents a requesting host from loading a cartridge from that storage slot unless the requesting host has access rights to the logical library that includes that storage slot.

Abstract: A memory pool control circuit according to the invention is provided with a CAM (content addressable memory: associative memory) 11. It further has a monitoring module 12, an area unlocking module 13, a local accessing module 14, an area locking module 15, a search control machine 16, and a timer 17. A plurality of tasks (processes) are operating on a processor 18, and one memory 19 is commonly used by the plurality of tasks (processes). When a task (process) has secured a memory space (called a block here), free areas therein are managed by a group of pointers. A block is divided into a plurality of fixed length fields. A group of flags match the memory space (block) in one-to-one correspondence. The flag group indicate whether or not individual fields are being used, i.e. the flag group indicates whether each individual field is being used or unused (free).

Abstract: A storage controller has at least one physical data port for a data network including host processors. The storage controller is programmed to provide a plurality of virtual ports for access to storage, and a virtual switch for routing storage access requests from the physical port to the virtual ports. The virtual ports and the virtual switch are defined by software. The virtual ports appear to the hosts as physical ports in the data network. For example, in a Fiber-Channel network, the virtual ports have World Wide Names (WWNs) and are assigned temporary addresses (S_Ds), and the virtual switch provides a name server identifying the WWNs and S_IDs of the virtual ports. For convenient partitioning of storage among host processors, one or more virtual ports are assigned to each host, and a set of storage volumes are made accessible from each virtual port. A host can access storage at a virtual port only if the virtual port has been assigned to the host.

Abstract: A method for scheduling functions for execution immediately or later in time by the scheduling processor or another processor of a shared memory multiprocessor computer system such as a NUMA machine. Associated with each of the multiple processors is a data structure for scheduling the execution of specified functions by the processor. These multiple data structures with associated locks allow for simultaneous access by processors to their data structures and thereby avoid the bottleneck inherent in the prior approach of providing only a single, global data structure for all processors. In addition, the method allows any processor to call a scheduling function to add a specified function to the data structure of any of the processors. Processor loads are balanced by moving scheduled specified functions from one processor to another. Scheduled functions can also be moved from one processor to another to allow a processor to be taken offline for service.

Abstract: In a virtual machine (VM) environment, a virtual machine ID (VMID) uniquely associated with a preferred virtual guest (222) is sent to a storage controller (108) along with requests to RESERVE or RELEASE a direct access storage device (DASD) (128). The VMID is used by the storage controller (108) along with a path group ID (PGID) to determine the scope of the RESERVE or RELEASE. Thus, preferred virtual guests (216) of a single host processor (112) may share the DASD while both preserving data integrity and operating with the performance benefits of Input/Output (I/O) Assist. Sharing is similarly provided for tape devices with requests to ASSIGN or UNASSIGN.

Abstract: In a computer that has hardware processor, and a memory, the invention provides a virtual machine monitor (VMM) and a virtual machine (VM) that has at least one virtual processor and is operatively connected to the VMM for running a sequence of VM instructions, which are either directly executable or non-directly executable. The VMM includes both a binary translation sub-system and a direct execution sub-system, as well as a sub-system that determines if VM instructions must be executed using binary translation, or if they can be executed using direct execution. Shadow descriptor tables in the VMM, corresponding to VM descriptor tables, segment tracking and memory tracing are used as factors in the decision of which execution mode to activate. The invention is particularly well-adapted for virtualizing computers in which the hardware processor has an Intel x86 architecture.

Abstract: A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unit 113 sets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

Abstract: The present invention relates to a method, apparatus and system for managing virtual memory, in which a co-processor (224) is adapted to use virtual memory with a host processor (202). A host memory (203) is coupled to the host processor (202) to implement the virtual memory. The co-processor (224) includes a virtual-physical memory mapping device (915) for interrogating a virtual memory table and for mapping one or more virtual memory addresses (880) requested by the co-processor (224) into corresponding physical addresses (873) in the host memory (203). The virtual memory table is stored in two or more non-contiguously addressable regions of the host memory (203), and is preferably a page table. The memory mapping device (915) further includes a multiple-entry translation lookaside buffer (889) for caching virtual-to-physical address mappings (872), where entries in the buffer (889) are replaced on a least recently used replacement basis.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention coordinate distribution of shared memory to threads of control executing in a program by using a cooperative synchronization protocol. The protocol serializes access to memory by competing threads requesting assignment of memory space, while allowing competing threads that have already been assigned memory space, to share access to the memory. A designated area of memory assigns the memory to requesting threads. The protocol is an application level entity and therefore does access the operating system to serialize the memory allocation process.

Abstract: A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer (10) having a plurality of processor regions and a plurality of memory pages (16). Each processor region includes one or more processors (12). Each processor (12) includes a cache (18), and each memory page (16) includes one or more cache lines (20) for coupling to the cache (18) of processors (12) within the plurality of processor regions using the memory page (16). Each memory page (16) includes a set of protection bits (82) associated with each processor region in the plurality of processor regions. The set of protection bits (82) includes an acquire protection bit (84) for each processor region in the plurality of processor regions. The acquire protection bit (84) determines whether the associated processor is enabled to perform acquire operations on the memory page (16).

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. A grouping of partitions, a community, shares memory. Memory may be private to a particular partition or may be shared by partitions within a community.

Abstract: A network-based storage system comprises one or more block-level storage servers that connect to, and provide disk storage for, one or more host computers (“hosts”) over logical network connections (preferably TCP/IP sockets). In one embodiment, each host can maintain one or more socket connections to each storage server, over which multiple I/O operations may be performed concurrently in a non-blocking manner. The physical storage of a storage server may optionally be divided into multiple partitions, each of which may be independently assigned to a particular host or to a group of hosts. Host driver software presents these partitions to user-level processes as one or more local disk drives. When a host initially connects to a storage server in one embodiment, the storage server initially authenticates the host, and then notifies the host of the ports that may be used to establish data connections and of the partitions assigned to that host.

Abstract: To erase data stored in a flash memory at high speed with simple processing and to improve operation environment, a file stored in the flash memory is managed by small blocks smaller than a rewriting unit, and small blocks are linked to each other so that a file having a size of plural blocks can be constructed. When a file erase command is inputted, an ineffective code is written in an area indicative of effectiveness/ineffectiveness of each block which constructs the file subjected to erasing. Writing an ineffective code is easily realized, without erasing the flash memory, by changing at least one bit of the effective code from “1” to “0”. When the set time comes, blocks storing ineffective codes are organized.

Abstract: Curious caching improves upon cache snooping by allowing a snooping cache to insert data from snooped bus operations that is not currently in the cache and independent of any prior accesses to the associated memory location. In addition, curious caching allows software to specify which data producing bus operations, e.g., reads and writes, result in data being inserted into the cache. This is implemented by specifying “memory regions of curiosity” and insertion and replacement policy actions for those regions. In column caching, the replacement of data can be restricted to particular regions of the cache. By also making the replacement address-dependent, column caching allows different regions of memory to be mapped to different regions of the cache. In a set-associative cache, a replacement policy specifies the particular column(s) of the set-associative cache in which a page of data can be stored.

Abstract: Access to stored information by a user is controlled by comparing an actual geographic position and/or an actual date/time with a geographic region and/or a date/time interval within which access to the stored information is authorized. The actual geographic position where the stored information is located, and the actual date/time can be determined, for example, based on signals received at a receiver supplying reliable position and time information, such as a GPS receiver. Access to the stored information is authorized if the actual geographic position and/or date/time falls within the authorized geographic region and/or date/time interval. The position and date/time information supplied by the receiver may be cryptographically signed and encrypted.

Abstract: An apparatus and method for allocating a memory in a cache aware manner are provided. An operating system can be configured to partition a system memory into regions. The operating system can then allocate corresponding portions within each region to various programs that include the operating system and applications. The portions within each region of the system memory can map into designated portions of a cache. The size of a portion of memory allocated for a program can be determined according to the needs of the program.

Abstract: A disc drive apparatus that communicates with and provides data storage for a host computer wherein the disc drive is adapted to provide improved audio and visual data transfer operations. The disc drive determines whether the data transfer operation is related to audio/visual data and, if so, limits the number of retry attempts available during the data read or write command. Since audio visual data is more time critical than reliability critical, limiting retry attempts does not significantly impact presentation to the user. The disc drive also enables the transfer of relatively large blocks of data that can be transferred during a single command. Limiting the retry attempts and transferring more data during a single command significantly increases audio/visual data transfer throughput between the host computer and the disc drive.

Abstract: A symmetrical processing system includes a number of processor units sharing a memory element. At least a portion of the memory element is partitioned so that separate memory partitions are made exclusively available to some if not all the processor units.

Abstract: Data coherency in a multiprocessor system is improved and data latency minimized through the use of data mapping “fill” requests from any one of the multiprocessor CPUs such that the information requested is acquired through the crossbar switch from the same memory module to which the “victim” data in that CPU's cache must be rewritten. With such an arrangement rewrite latency periods for victim data within the crossbar switch is minimized and the 'ships crossing in the night' problem is avoided.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Memory may be reconfigured into or out of a partition or community under software control. In general, memory may be in one of three states: private, shared, or unowned. Memory is private if it is “owned” by a single system partition.