Abstract: Memory pool management may be provided by allocating storage blocks and handles in different parts of a larger memory pool. Two variable size sub-pools may be provided within the memory pool: a storage block sub-pool and a handle sub-pool. Each sub-pool has a variable size and may be allowed to grow until their combined size reaches the size of the memory pool. Both sub-pools may be allowed to grow into the same unused memory space. When a memory request is received from a program, the storage block sub-pool and handle sub-pool may be enlarged to accommodate the request. A storage block and a handle may be allocated to the program from the storage block and handle sub-pools, respectively.

Abstract: A data block format for streaming information includes a first data block size field and a second data block size field, each of the fields indicating the size of the data block. A payload field is bounded by the first data block sized field and the second data size in the data block format.

Abstract: A data processor includes the normal mode providing narrow access space of CPU and the advance mode providing wide access space. Even in the normal mode, the transfer control section assures data transfer control exceeding the address range for access from CPU. Even when programs are generated exceeding the limit of program capacity for the access range of CPU in the normal mode, if the programs exceeding such limit are stored in the non-access area of ROM 6 in the normal mode, the transfer control section accesses such programs and transfers these programs to RAM. Thereby CPU in the normal mode can use such programs transferred to RAM by making access thereto. Accordingly, limit of program capacity can be alleviated, while maintaining good program execution efficiency in the rather small access space of CPU in the data processor.

Abstract: Code and data are cloned in a multiprocessor system in order to permit each processor to run concurrently a separate invocation of a program. Each processor uses the same address translation for shared access to the program code in a shared memory, and a different address translation for access to a respective private read-write data region in the shared memory. Initialization of a private data region is performed by copying data from a shared read-only memory region, such as the program region, to the private data region. Some static constructors may access a shared read-write data area that should not be reinitialized by the clone processor. In this case, a working copy of a data region is made, the address translation is remapped for access to the working copy, the static constructors are run, and then the mapping is returned for normal access to the shared data.

Abstract: Data collection agents are assigned to storage area network nodes in a storage area network resource management system, such that the bandwidth and cost of data collection are equitably distributed among data collection agents. Data collection overlaps and load imbalances are eliminated across the data collection agents, creating approximately equal partitions of bandwidth and data collection for each data collection agent. Graph partitioning is used to accomplish load balancing. The assignment of data collection agents to storage area network nodes equitably distributes the bandwidth and processing costs among the data collection agents and ensures a load balance. In addition, the present system provides mutually exclusive sets of data collection agents to storage area network nodes that can be used in the event of failure of a data collection agent or storage area network node.

Abstract: Systems for managing responses to requests from a plurality of clients for access to a set of resources and for providing a storage area network (SAN) that more efficiently responds to client load changes by migrating data blocks while providing continuous data access. In one embodiment, the systems comprise a plurality of equivalent servers wherein the set of resources is partitioned across this plurality of servers. Each equivalent server has a load monitor process that is capable of communicating with the other load monitor processes for generating a measure of the client load on the server system and the client load on each of the respective servers. The system further comprises a resource distribution process that is responsive to the measured system load and is capable of repartitioning the set of resources to thereby redistribute the client load.

Abstract: The invention relates to a handheld portable card or disc (22) interface to a crash secure virtual hard disc (24) accessed through the card or disc with software storage capability, and a system (20) therefore. It virtually allows a user to log in on any computer (28) or terminal for retrieving own computer files from the hard disc (22) through the world wide web or Intranet and the like.

Abstract: Systems and methods for preventing conflicts in a media library system, wherein multiple hosts may attempt to access the same element (e.g., cartridge slot) at the same time. A plurality of pools are defined, each of which is associated with a corresponding subset of the hosts and a corresponding subset of the elements in the library. It is assumed that all of the hosts associated with a given pool have compatible software applications or some other means for preventing or resolving conflicts among them. Each host is then allowed to access only the subset of the elements in the library that are associated with the same pool as the host so no conflicting access commands are transmitted to the media library.

Abstract: A method and apparatus for providing a computer system having a plurality of logical partitions with a virtual operator panel is disclosed. The method and apparatus include displaying a plurality of operator panels on a single console corresponding to each of the logical partitions, and providing a buffer for each logical partition. The status codes from each of the logical partitions are then written directly to the corresponding buffer. To display the status codes of one of the logical partitions, the status code from the buffer corresponding the logical partition is read and sent to the corresponding operator panel for display.

Abstract: A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.

Abstract: A storage provisioning policy is created by specifying storage heuristics for storage attributes using storage heuristic metadata. Storage attributes characterize a storage device and storage heuristic metadata describe how to specify a storage heuristic. Using the storage heuristic metadata, storage heuristics are defined to express a rule or constraint as a function of a storage attribute. In addition, the storage provisioning policy may also specify mapping rules for exporting the storage to a consumer of the storage, such as the server or server cluster.

Abstract: The memory management technology controls, as described herein, access to and monitors availability of common memory resources. In particular, this hardware-based, memory-management technology manages memory access requests to a common memory shared by multiple requesting entities. This includes prioritizing and arbitrating such requests. It further includes minimizing latency of such requests. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

Abstract: A combination of data processing systems that are connected to a common peripheral bus, such as a PCI bus. The processor(s) of each system or blade may communicate with the peripheral bus through an intermediate bus controller. The bus controller may include facilities, such as registers that define a starting address, suitable for defining a window in the blade's system memory that is available or visible to other processors (or masters) on the bus. One or more of the bus controllers may be configured to read information that uniquely identifies each system or blade. The bus controller may use this identification information to define the window in the blade's system memory that is visible to other processors. In an embodiment where each blade is connected to a PCI bus through a CompactPCI® connector, the identification information may be read from the geographic address (GA) pins on the system's J2 connector.

Abstract: Processing video data with a combination of one or more operations, such as special effects, on a general-purpose computer may be improved by enabling one or more operations to access and process multiple samples of video data from other operations that introduce latencies for each request for data. Operations that introduce latencies include, for example, hardware for decompression and compression, network interfaces, and file systems. Because a computer program to implement the operations may be executed on several different general-purpose platforms, exact specifications of available hardware are not known in advance. For each operation, a computer program determines the available system memory and an amount of data that can be processed by each operation used in a composition or portion of a composition while sharing the available memory with other operations. Available system memory is allocated among the operations being used.

Abstract: A Virtual Disk Storage (VDS) System for providing multiple virtual data storage devices for use in a computer system which contains a central processing unit (CPU). The VDS System includes a memory system for storing information and a VDS Controller which is in communication with the memory system and the CPU. The VDS Controller partitions the memory system into multiple virtual data storage devices, and then restricts the computer system from communicating with certain of these virtual data storage devices. The VDS Controller thus selectively isolates at least one of the virtual data storage devices from communicating with the computer system, in order to prevent corruption of information stored in at least one virtual data storage device.

Abstract: A system, computer program product and method for reallocating memory space for storing a partitioned cache. A server may be configured to receive requests to access a particular logical drive. One or more logical drives may be coupled to an adapter. A plurality of adapters may be coupled to the server. Each logical drive may be associated with one or more stacks where each stack may comprise one or more cache entries for storing information. The one or more stacks associated with a logical drive may be logically grouped into a logically grouped stack associated with that logical drive. Each of the logically grouped stacks of the one or more logical drives coupled to an adapter may be logically grouped into a logically grouped stack associated with that adapter. By logically grouping stacks, memory supporting a partitioned cache may adaptively be reallocated in response to multiple criteria thereby improving the performance of the cache.

Abstract: A method, system, and computer program product for testing enforcement of logical partitioning in a data processing system are provided. In one embodiment, a call to an interface routine of a logical partitioning enforcement software unit is generated and sent to the logical partitioning enforcement software unit. Generating a call to an interface routine may include, for example, pseudo-randomly selecting one of a valid interface routine and an invalid interface routine and generating a call to the selected interface routine. A reply is received from the logical partitioning enforcement software unit and compared with an anticipated reply. Responsive to a discrepancy between the reply and the anticipated reply, a user is notified of a problem, thus allowing the user to take appropriate actions to correct the problem.

Abstract: Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first memory controller and a first cache coupled to the first memory controller, the first memory controller including first interface for coupling with second auxiliary processor including second memory controller and associated second cache and second interface for coupling with first auxiliary processor, first memory controller including logic for treating the caches as single memory; a bus coupling first primary processor and first auxiliary processor; and interconnection channel separate from the bus coupling first interface of first memory controlled and second interface of second memory controller. Interconnection may be an out-of-band channel permitting device-to-device sharing of associated cache memories without requiring data transfer over the bus. Method and computer program product are also provided.

Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.

Abstract: A programmable correlator for a communication system includes an input queue coupled with an analog-to-digital converter (ADC). The input queue includes a random access memory (RAM) wherein sampled data streams from the ADC are written into the RAM. The input queue has two banks of memory of width 2M. A flexible complex correlator is operable on M samples. The correlator is coupled to read M complex samples out of 2M samples from the input queue. A pseudo-noise (PN) crossbar unit operates to rotate a generated PN code to match a rotation of the input queue data in the complex correlator.

Abstract: A method and system for managing data in a data processing system are disclosed. Initially, data is stored in a first portion of the main memory of the system. Responsive to storing the data in the first portion of main memory, information is then stored in a second portion of the main memory. The information stored in the second portion of main memory is indicative of the data stored in the first portion. In an embodiment in which the data processing system is implemented as a multi-node system such as a NUMA system, the first portion of the main memory is in the main memory of a first node of system and the second portion of the main memory is in the main memory of a second node of the system. In one embodiment, storing information in the second portion of the main memory is achieved by storing a copy of the data in the second portion. If a fault in the first portion of the main memory is detected, the information in the second main memory portion is retrieved and stored to a persistent storage device.

Abstract: Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.

Abstract: A file memory stores data corresponding to identifiers of an allocated area in an identifier space. A first memory stores a basis position of the allocated area in the identifier space. A second memory stores a weight of the storage apparatus as a performance degree. A first decision unit decides a space width to divisionally allocate the identifier space with another storage apparatus by using the weight and a weight of another storage apparatus. Another storage apparatus allocates a neighboring area of the allocated area in the identifier space. A second decision unit decides the allocated area of an area between the basis position and a basis position of the neighboring area in the identifier space by using the space width.

Abstract: A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

Abstract: A method and apparatus for storing entries in at least two separate storage areas of a non-volatile memory in a communications terminal, wherein the storage areas have fixed area boundaries, such that a dynamic redial list in the communications terminal is increased in a highly cost-effective fashion.

Abstract: A method, computer system, and computer program are claimed for selecting rows from first and second tables each having rows containing values in columns. In at least the first table, the rows are divided into partitions at least one of which is populated by one or more rows.

Abstract: The present invention relates to a communication device using three-step communication buffers which temporarily stores received data or data to be transmitted between a serial communication device and a central processing unit. To prevent an error resulted from that the serial communication device and the central processing unit simultaneously access to the communication buffer, the access to the communication buffer is allowed at different edges of the system clock signal, thereby having a time difference of the access.

Abstract: A computer-implemented system (90) is provided that supports a high degree of separation between processing elements. The computer-implemented system (90) comprises a plurality of cells (92) residing on the computer-implemented system, where each cell (92) includes a domain of execution (94) and at least one processing element (96); a separation specification (99) that governs communication between the processing elements (96); and a kernel (98) of an operating system that facilitates execution of the processing elements (96) and administers the communication between the processing elements (96) in accordance with the separation specification (99), such that one processing element (96) can influence the operation of another processing element (96) only as set forth by the separation specification (99). In particular, the separation specification provides memory allocation, remote procedure calls and exception handling mechanisms.

Abstract: A method, system, and product are described for creating and managing affinity between memory and processors in logical partitions in a data processing system. The data processing system includes multiple processors. A memory affinity data structure is established. The memory affinity data structure identifies ones of the processors that have a close affinity with each one of multiple regions of the system memory. A memory affinity parameter is established and is utilized to determine whether memory affinity is required for each one of the logical partitions. In response to a determination that memory affinity is required for one of the logical partitions, the memory affinity data structure is utilized by a partition manager for the logical partition to allocate an optimal amount of memory that has a close affinity to ones of the processors that are assigned to the logical partition.

Abstract: Disclosed herein is a method for controlling a storage device controller connected to a storage device provided with a plurality of storage volumes for storing data respectively and an information processing apparatus for requesting an input/output of data so as to receive an input/output request from the information processing apparatus and execute an input/output processing of the data for each of the plurality of storage volumes. The method brings one (primary) of the plurality of storage volumes into correspondence with another (secondary) in which a copy of data is to be written when the data is written in the primary volume so as to form a pair group consisting of a plurality of pairs, each having such a primary volume and such a secondary volume.

Abstract: The disclosed embodiments relate to a device for generating physical addresses in a multi-processor computer system. The computer system may be adapted to support multiple physical memory partitions. Agent IDs for each of a plurality of processors may be used to correspond with a partition offset, which may be used to define a separate physical memory partition for each processor. The partition offset may be used with a virtual address to form a physical address.

Abstract: An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.

Abstract: The present invention relates to a system and a method of memory management of data consistency relating to a main memory (4) accessible by at least two processors (1, 2), as well as an associated multiprocessor network. The management system comprises an assembly for management of shared access of the processors to a common area (9) of the main memory, referred to as the exchanges area, at least one copy module (12, 13) intended for performing a data copy between at least one first processor comprising at least one cache memory and the exchanges area and at least one transfer module (12, 13) intended for performing a transfer of data between the exchanges area and at least one second processor. Triggering means controlled by the second processors trigger the copy modules and transfer modules when the first processors submit requests involving transfers of data between the first and second processors.

Abstract: A method and system for allocating and storing data to a cache memory in each processor in a multiprocessor computer system. Data structures in main memory are partitioned into substructures that are classified as either exclusive substructures or sharing substructures. The exclusive substructures are cached exclusively by a specified processor, and the sharing substructures are cached by specified groups of processors in the multiprocessor computer.

Abstract: A system and method of logically partitioning shared memory structures between computer domains is disclosed. In one embodiment, each domain is assigned a unique address space identifier. The unique address space identifier preferably has tag extension and index extension bits. This permits the tag and index bits of a conventional local domain address to be extended with tag extension and index extension bits. Data entries in the shared memory structure may be accessed using an extended index value. Hits may be determined using an extended tag value.

Abstract: The present invention provides an apparatus, method and computer program product for privatizing operating system data. With the apparatus, method and computer program product of the present invention, a block of memory is allocated and divided into identical, smaller, properly aligned storage areas, each dedicated to a single processor in a multiprocessor system. The storage areas are allocated either initially when the system is initialized or on an as needed basis. Each sub-allocation request is made to use storage at the same location relative to the start of that processor's storage space. Because each processor's storage is isomorphic to all other processors, only one allocation record for all processors is needed, thereby reducing the overhead of the data privatization scheme. By allocating memory in this manner, cache line contention is minimized.

Abstract: Memory sharing techniques include providing a first device and one or more additional devices. Each device has a memory and is configured to be connected to a network. A portion of the first device memory is allocated, and may be divided into two or more first device memory segments. Each first device memory segment corresponds to a device, and at least one of the first device memory segments corresponds to an additional device. A portion of the additional device memory is allocated, and may be divided into two or more additional device memory segments. Each additional device memory segment corresponds to a device, and at least one additional device memory segment corresponds to the first device. A first device data segment is provided to the additional device, and a first device data validity indication is derived at the additional device.

Abstract: A data recorder mounting a plurality of modules for collecting data, the data recorder storing the collected data in a data storage means, the data recorder including data transfer control means for transferring data collected by the modules to the data storage means, module identification data storage means, in which module identification data for identifying any particular one of the modules is stored in an order in which the modules are to be accessed, and output control means for outputting the module identification data in order to the modules from the module identification data storage means in response to data transfer by the data transfer control means, the data recorder capable of accessing one of the modules corresponding to module identification data output to the module by the output control means from the module identification data storage means.

Abstract: A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and maintaining security over the distribution mechanism. In one embodiment, this invention is used by a data processing system including a system processor connected to a plurality of operating system instances that are allocated individual system functions. Using logical partitioning, each operating system instance's access is limited to its own partition. Address buses to system functions are manipulated to make the functions appear at appropriate memory locations expected by the operating system instances. Accordingly, an inverter can be inserted on the address bus to change the address to a given distance in memory safe from operating system accessibility, for example, a page boundary.

Abstract: A method for providing a memory scheme in computer architectures in an efficient and cost effective manner. A processor is configured with access to dual-L2 caches, preferably configured to cache program instructions and data in one cache and shared data in another cache. In one embodiment of the present invention, one L2 cache is accessible to networking interface devices. Optionally, the cache accessible by the networking interface devices is configured as networking buffers, providing cache for packet data being sent within a network. By use of this invention, the packet forwarding speeds in a conventional computer architecture may be increased.

Abstract: Fiber channel connection magnetic disk device and controller which have a plurality of fiber-channel specification supporting port controllers, comprising: a port controller for managing the relationship between an identifier allocated to each host and a logical volume accessible from the host having the identifier; and a local access right management table memory for storing the management state of a logical volume accessible from an indicated host, the port controller being capable of rejecting an access from hosts other than the indicated host.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: An LU decomposition is carried out on a block E and H. Then, a block B is updated using an upper triangular portion of the block E, and a block D is updated using a lower triangular portion of the block E. At this time, in an LU decomposition, blocks F and I have been updated. Then, using the blocks B, D, F, and H, blocks A, C, G, and I are updated, an upper triangular portion of the block E is updated, and finally, the blocks D and F are updated. Then, the second updating process is performed on the block E. Using the result of the process, the blocks B and H are updated. Finally, the block E is updated, and the pivot interchanging process is completed, thereby terminating the process. These processes on the blocks are performed in a plurality of divided threads in parallel.

Abstract: The present invention discloses a technique for sharing data between at least two operating systems. In accordance with the present invention, a volume is provided in a data storage device. The provided volume is a portion of memory within the data storage device. The provided volume is accessible by a source operating system residing on a source computer and a target operating system residing on a target computer. Data is generated within the provided volume using the source operating system. The generated data is in a format that is readable by the target operating system.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: A method to partition a data storage and retrieval system into one or more logical libraries, where that data storage and retrieval system includes a library controller, one or more data storage drives and one or more control ports. A data storage and retrieval system which includes a computer useable medium having computer readable program code disposed therein to implement Applicants' method to partition the data storage and retrieval system into one or more logical libraries. A computer program product usable with a programmable computer processor having computer readable program code embodied therein for partitioning Applicants' data storage and retrieval system into one or more logical libraries.

Abstract: A virtual storage and computing device includes an array control processor, a virtual device blueprint and a transceiver. Shared and cache memory are linked to the array control processor. The array control processor uses a wireless link to request additional resources from at least one component selected from the group of disk controllers, disk drives, cache memory, shared memory and channel adapters to assemble a virtual device described by the virtual device blueprint. The shared memory and the cache memory have hardwired and/or wireless links to the array control processor. The array control processor receives the virtual device blueprint from a host computer that is linked to the array control processor using a channel adapter or via a wireless link between a host computer and the array control processor.

Abstract: A method and system for the parallel implementation of protocol engines based on memory partitioning. The method comprises the steps of partitioning a shared memory space into multiple mon-overlapping regions; and for each of the regions, using a respective one protocol engine to handle references to the region, independently of the other protocol engines. Preferably, the memory is partitioned into the non-overlapping regions either by using address interleaving or by using address range registers to identify address ranges for said regions. Also, preferably the protocol engines operate independent of each other and handle accesses to the memory regions in parallel.

Abstract: The present invention is a shared buffer architecture that dynamically allocates buffer size to each of multiple sources depending on buffer pool utilization, estimated per-connection offered load, and the total number of connection established within a given class of service. When the buffer pool is almost empty, each source is allocated a large buffer space, proportional to its estimated offered load. When the buffer pool is more full each source is allocated a reduced buffer space, while maintaining the proportional weighting relationship. The invention keeps track of the amount of input per source and dynamically allocates a proportionate amount of buffer space in the buffer memory for that source. The dynamic allocation is made as a function of the fullness of the memory allocation for all sources. Additionally, thresholds are modulated dynamically as the number of established connections within a given class modulates, providing a predictive aspect to the system, with respect to congestion control.