Least Recently Used (lru) Patents (Class 711/160)
  • Patent number: 10387398
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and which has associated physical disk storage. Thereafter, the page flusher identifies pages that were last modified outside a pre-defined time window. The page flusher then flushes the identified modified pages to the physical disk storage.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: August 20, 2019
    Assignee: SAP SE
    Inventors: Dirk Thomsen, Werner Thesing
  • Patent number: 10380072
    Abstract: An information management system can manage the removal of data block entries in a deduplicated data store using working copies of the data block entries residing in a local data store of a secondary storage computing device. The system can use the working copies to identify data blocks for removal. Once the deduplication database is updated with the changes to the working copies (e.g., using a transaction based update scheme), the system can query the deduplication database for the database entries identified for removal. Once identified, the system can remove the database entries identified for pruning and/or the corresponding deduplication data blocks from secondary storage.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: August 13, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Deepak Raghunath Attarde, Manoj Kumar Vijayan
  • Patent number: 10360111
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and having associated physical disk storage by a resource flush thread using a queue. Thereafter, pages are identified that have been loaded into the memory of the database system and which have been modified. These identified pages are to be flushed to the physical disk storage. Each page is assigned with a different ordered physical page number. These identified pages are added to the queue. Subsequently, asynchronous write I/O is triggered causing the identified pages to be flushed to the physical disk storage and stored in the physical disk storage according to their assigned physical page numbers such that, if at least one predetermined performance condition is met, a subset of the identified pages in the queue are flushed to physical disk storage.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 23, 2019
    Assignee: SAP SE
    Inventor: Dirk Thomsen
  • Patent number: 10324798
    Abstract: In one aspect, a method includes reading metadata for a logical unit (LU) to restore, restoring active read areas to the LU identified in the metadata and exposing the LU to a host after restoring the active read areas of the LU. In another aspect, an apparatus includes electronic hardware circuitry configured to reading metadata for a LU to restore, restoring active read areas to the LU identified in the metadata and exposing the LU to a host after restoring the active read areas of the LU. In a further aspect, an article includes a non-transitory computer-readable medium that stores computer-executable instructions. The instructions cause a machine to read metadata for a LU to restore, restore active read areas to the LU identified in the metadata and expose the LU to a host after restoring the active read areas of the LU.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 18, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Assaf Natanzon, Anestis Panidis
  • Patent number: 10310946
    Abstract: Execution of a page flusher is initiated in an in-memory database system in which pages are loaded into memory and having associated physical disk storage. Thereafter, pages are identified that have been loaded into the memory of the database system and which have been modified. These identified pages are to be flushed to the physical disk storage. Each page is assigned with a different ordered physical page number. Asynchronous write I/O is later triggered causing the identified pages to be flushed to the physical disk storage and stored in the physical disk storage according to their assigned physical page numbers.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 4, 2019
    Assignee: SAP SE
    Inventor: Dirk Thomsen
  • Patent number: 10235405
    Abstract: A distributed storage system may store data object instances in persistent storage and may store keymap information for those data object instances in a distributed hash table on multiple computing nodes. Each data object instance may include a composite key containing a user key. The keymap information for each data object instance may map the user key to a locator and the locator to the data object instance. A request to store or retrieve keymap information for a data object instance may be routed to a particular computing node based on a consistent hashing scheme in which a hash function is applied to a portion of the composite key of the data object instance. Thus, related entries may be clustered on the same computing nodes. The portion of the key to which the hash function is applied may include a pre-determined number of bits or be identified using a delimiter.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 19, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Jason G. McHugh, Praveen Kumar Gattu, Michael A. Ten-Pow, Derek Ernest Denny-Brown, II
  • Patent number: 10228394
    Abstract: A measurement system is provided that performs a qualified store algorithm. When performing the algorithm, the measurement system stores in memory digital data samples acquired during a time window while a qualification signal is valid, a preselected number of digital data samples acquired prior to and adjacent in time to the time window, and a preselected number of digital data samples acquired subsequent to and adjacent in time to the time window.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: March 12, 2019
    Assignee: Keysight Technologies, Inc.
    Inventor: Allen Montijo
  • Patent number: 10223256
    Abstract: A distributed parallel processing database that processes data in a Java environment allocates memory both on a Java heap and off a Java heap. The distributed parallel processing database includes multiple servers. Each server executes a Java virtual machine (JVM) in which data allocated to the server is processed. When a JVM of a server starts, the JVM can specify an off-heap memory size, based on a JVM start parameter. The server can designate memory of the specified size that is off JVM memory heap as off-heap memory. The off-heap memory is different from heap memory in the Java environment, and is managed by a garbage collector that is outside of the Java environment. The server can process data designated as off-heap memory eligible in the off-heap memory. The off-heap memory can improve database operations that create a large number of similar-sized objects in memory by reducing Java memory management overhead.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 5, 2019
    Assignee: Pivotal Software, Inc.
    Inventors: Darrel Scott Schneider, Hitesh Khamesra, Asif Hussain Shahid, Jagannathan Ramnarayanan, Sudhir Menon, Kirk Van Lund, Lynn Gallinat
  • Patent number: 10068168
    Abstract: An IC card has a data storage, a table storage and a processing unit. The data storage stores data. The table storage stores a data element table including profile information including, in association with each other: a profile identifier for identifying a profile that is a group (set) of data elements to be stored in the data storage, at the time of issuance; the data elements included in the profile; and data region identifiers indicating data regions that are reserved in the data storage to store the data elements. The processing unit stores, in the data region indicated by the data region identifier corresponding to the data elements, the data elements corresponding to the profile identifier, from the data element table stored in the table storage, in response to a processing request that includes the profile identifier and requests issuance processing.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yusuke Tsuda
  • Patent number: 10051057
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device identifies slice error(s) associated with first storage unit(s) (SU(s)) of a first storage set that distributedly store a set of encoded data slices (EDSs) and second SU(s) of a second storage set. The computing device determines usage priority level(s) of the first SU(s) or the second SU(s) based on the slice error(s) and produces a selected storage set from the first SU(s) and the second SU(s) based on a more favorable usage priority level of the usage priority level(s) and facilitates execution of data access to at least the decode threshold number of EDSs based on the selected storage set.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Thomas D. Cocagne, Jason K. Resch, Greg R. Dhuse
  • Patent number: 9942324
    Abstract: A method implemented by a network element (NE) in a network, comprising composing a first network storage entity by mapping a plurality of logical storage units to a plurality of physical storage units in a physical storage system according to a first storage metric associated with the plurality of physical storage units, arranging the plurality of logical storage units sequentially to form a logical circular buffer, and designating a current logical storage unit for writing data and an upcoming logical storage unit for writing data after the current storage unit is fully written, and rebalancing the physical storage system while the physical storage system is actively performing network storage operations by relocating at least one of the logical storage units to a different physical storage unit according to a second storage metric associated with the plurality of physical storage units.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 10, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Masood Mortazavi, Chi Young Ku, Guangyu Shi, Stephen Morgan
  • Patent number: 9928173
    Abstract: Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A processor executes a TM transaction, that includes the following. Executing a memory data access instruction that accesses an operand at an operand memory address. Based on either a prefix instruction associated with the memory data access instruction, or an operand tag associated with the operand of the memory data access instruction, determining whether a cache entry having the operand is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction. Based on determining that the cache entry is to be marked for monitoring for cache coherency conflicts while the processor is executing the transaction, marking the cache entry for monitoring for conflicts.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9817874
    Abstract: Disclosed herein are system, method, and computer program product embodiments for providing a spatio-temporal index for high-update workloads and query processing. An embodiment operates by a first thread retrieving an update record from a first queue, the update record comprising a location component and a temporal component indicating a location of one of a plurality of mobile devices at a specified time, and updating a columnar-store database with the update record. The embodiment further operates by a second thread identifying a spatial grid of a spatial temporal index within a memory corresponding to the location component of the update record, and updating a temporal index of the spatial grid based on the temporal component of the update record.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: November 14, 2017
    Assignee: SAP SE
    Inventors: Suprio Ray, Rolando Blanco, Anil Kumar Goel
  • Patent number: 9792227
    Abstract: Inventive aspects include a heterogeneous unified memory section, which includes an extended unified memory space across a plurality of physical heterogeneous memory modules. A cold page reclamation logic section can receive and prioritize cold pages from a system memory. The cold pages can include a first subset of memory pages having a first type of memory data and a second subset of memory pages having a second type of memory data. For example, the cold pages can include anon-type memory pages and file-type memory pages. A dynamic tuning logic section can manage space allocation within the extended unified memory space. An intelligent page sort logic section can distribute the cold pages among different pools of physical heterogeneous memory modules based on varying characteristics of the pools, and based on the assigned priorities.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yang Seok Ki, Sheng Qiu
  • Patent number: 9720847
    Abstract: A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: August 1, 2017
    Assignee: NXP USA, INC.
    Inventors: Thang Q. Nguyen, John D. Coddington, Sanjay R. Deshpande
  • Patent number: 9696932
    Abstract: Guaranteeing space availability for thin devices includes reserving space without committing, or fully pre-allocating, the space to specific thin device ranges. Space may be held in reserve for a particular set of thin devices and consumed as needed by those thin devices. The system guards user-critical devices from running out of space, for example due to a “rogue device” scenario in which one device allocates an excessive amount of space. The system uses a reservation entity, to which a thin device may subscribe, which reserves space for the thin device without allocating that space before it is need to service an I/O request.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: July 4, 2017
    Assignee: EMC IP Holding Company LLC
    Inventors: Igor Fradkin, Alexandr Veprinsky, John Fitzgerald, Magnus E. Bjornsson
  • Patent number: 9471364
    Abstract: Embodiments of the present invention provide a virtual machine specification adjustment method and apparatus, where the virtual machine specification adjustment method includes: acquiring running status information of a virtual machine; determining, according to the running status information of the virtual machine, whether the virtual machine is a to-be-adjusted virtual machine; and if the virtual machine is a to-be-adjusted virtual machine, adjusting a specification of the to-be-adjusted virtual machine by using a resource in a reserved resource pool. By using the technical solutions of the present invention, efficiency of virtual machine specification adjustment is improved, thereby increasing a resource utilization rate of a data center.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: October 18, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Lijun Yan
  • Patent number: 9323318
    Abstract: One or more techniques and/or systems are provided for dynamically applying power policies to a computing environment. For example, a computing environment may comprise one or more activity components (e.g., a display driver, an audio driver, an application, etc.) that may provide status information used to identify a scenario (e.g., a video game scenario, a full screen video playback scenario, etc.) that is activated for the computing environment. A power policy assigned to a currently identified scenario may be applied to the computing environment to dynamically improve performance and/or power conservation, for example. Activity components, scenarios, and/or power policies may be maintained in an extensible manner such that activity components, scenarios, and/or power polices may be added, removed, and/or modified by merely updating corresponding data structures, such as tables or registry keys, as opposing to updating power management software code.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 26, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Abhishek Sagar, Tristan Anthony Brown
  • Patent number: 9262336
    Abstract: Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Nevin Hyuseinova, Qiong Cai
  • Patent number: 9235506
    Abstract: A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 12, 2016
    Assignee: Nimble Storage, Inc.
    Inventors: Umesh Maheshwari, Varun Mehta
  • Patent number: 9223722
    Abstract: Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 29, 2015
    Assignee: VMware, Inc.
    Inventors: Carl A. Waldspurger, Rajesh Venkatasubramanian, Alexander Thomas Garthwaite, Yury Baskakov, Puneet Zaroo
  • Patent number: 9223693
    Abstract: A flash memory system having unequal number of memory die and method for operation are disclosed. The memory system includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die and associated different physical capacity per control line.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 29, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Alan Welsh Sinclair, Nicholas James Thomas, Barry Wright
  • Patent number: 9195582
    Abstract: A data storage method applied to a flash memory storage device is provided. The method includes: identifying a first tag pointing to a storage unit storing a first data, the first data being a newly updated data; locating the storage unit storing the first data according to the first tag; storing a second data to another storage unit; pointing the first tag to the another storage unit storing the second data. A relationship between the first tag and the storage unit storing the first data is first built. The second data is stored to another storage unit different from the storage unit pointed by the first tag, and a relationship between the first tag and the another storage unit storage the second data is rebuilt. Therefore, data is efficiently stored by using a plurality of storage units to prolong a lifespan of the flash memory.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: November 24, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Rui-qing Wang, Da-teng Li, Wei Wu
  • Patent number: 9164950
    Abstract: A method, system, and computer program product for displaying components assigned to events produced by resources, includes: registering a new resource by generating a label to which is associated a system specific device identifier used by the new resource within a computing environment; storing in a mapping table the generated label identifying the registered new resource together with an associated system specific device identifier; and updating the mapping table by associating to the label any other system specific device identifier used by the new resource within the computing environment; receiving events produced by resources when being executed within the computing environment, each event being associated with a list of labels for the resources relevant for the generation of the event; and maintaining a tag cloud including different tags, the different tags including labels for the resources associated with the received events to be displayed as components.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: October 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Oliver Augenstein, Joerg Erdmenger, Hans-Ulrich Oldengott, Thomas Prause, Martin Raitza
  • Patent number: 9152572
    Abstract: Some implementations disclosed herein provide techniques and arrangements for an specialized logic engine that includes translation lookaside buffer to support multiple threads executing on multiple cores. The translation lookaside buffer enables the specialized logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores. For example, an acceleration compute engine may receive one or more instructions from a thread executed by a processing core. The acceleration compute engine may retrieve, based on an address space identifier associated with the one or more instructions, a physical address associated with the one or more instructions from the translation lookaside buffer to execute the one or more instructions using the physical address.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 6, 2015
    Assignee: Intel Corporation
    Inventors: Ronny Ronen, Boris Ginzburg, Eliezer Weissmann, Karthikeyan Vaithianathan
  • Patent number: 9081623
    Abstract: Disclosed are various embodiments for a resource allocation application. Usage data for application program interfaces is aggregated over time. Limits for an allocation of resources for each of the application program interfaces are calculated as a function of the usage data. Limits are recalculated as new application program interfaces are added.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 14, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Joseph Magerramov, Ganesh Subramaniam
  • Patent number: 9032168
    Abstract: Memory management methods and systems for mobile devices are provided. A memory usage of a memory is monitored by a built-in memory management component of an OS of the device and a user-oriented memory management component. It is determined whether the memory usage of the memory is greater than a first threshold or a second threshold, wherein the second threshold is greater than the first threshold. When the memory usage of the memory is greater than the first threshold, a multi-level memory management is performed by the user-oriented memory management component. When the memory usage of the memory is greater than the second threshold, a primitive memory management is performed by the built-in memory management component.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 12, 2015
    Assignee: HTC Corporation
    Inventors: Wen-Yen Chang, Chih-Tsung Wu, Kao-Pin Chen, Ting-Lun Chen
  • Patent number: 9021185
    Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: April 28, 2015
    Inventor: Amir Ban
  • Patent number: 9015419
    Abstract: Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi
  • Patent number: 9009401
    Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventor: Noriaki Asamoto
  • Patent number: 9009403
    Abstract: A control unit of a least recently used (LRU) mechanism for a ternary content addressable memory (TCAM) stores counts indicating a time sequence with resources in entries of the TCAM. The control unit receives an access request with a mask defining related resources. The TCAM is searched to find partial matches based on the mask. The control unit increases the counts for entries corresponding to partial matches, preserving an order of the counts. If the control unit also finds an exact match, its count is updated to be greater than the other increased counts. After each access request, the control unit searches the TCAM to find the entry having the lowest count, and writes the resource of that entry to an LRU register. In this manner, the system software can instantly identify the LRU entry by reading the value in the LRU register.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventor: Noriaki Asamoto
  • Patent number: 8996759
    Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoiju Chung
  • Publication number: 20150089170
    Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Inventors: Yi-Shin Tung, He-Yuan Lin, Jia-Wei Lin, Hung-Wei Yang
  • Patent number: 8990524
    Abstract: A plurality of subgroups with a least recently used (LRU) list of data elements associated with count variables. The LRU lists have a top entry to store a most recently used data element and a bottom entry to store a least recently used data element. If a data element is accessed, then increase the value of the count variable and move the accessed data element to the top entry of the LRU list of the subgroup associated with the data element. If the value of the count variable of the accessed data element of the top entry is greater than a value of a count variable of a data element of a bottom entry of a LRU list of a subgroup with a higher priority, then swap the data element of the bottom entry with the accessed data element of the top entry.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 24, 2015
    Assignee: Hewlett-Packard Development Company, LP.
    Inventor: Mykel John Kramer
  • Patent number: 8990504
    Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Patent number: 8990525
    Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Yoshida, Tatsunori Kanai, Masaya Tarui, Yutaka Yamada
  • Patent number: 8984240
    Abstract: Page faults during partition migration from a source computing system to a destination computing system are reduced by assigning each page used by a process as being hot or cold according to their frequency of use by the process. During a live partition migration, the cold or coldest (least frequently used) pages are copied to the destination server first, followed copying the warmer (less frequently used) and concluded by copying the hottest (most frequently used) pages. After all dirtied pages have been refreshed, cutover from the instance on the source server to the destination server is made. By transferring the warm and hot pages last (or later) in the migration process, the number of dirtied pages is reduced, thereby reducing page faults subsequent to the cutover.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Adekunle Bello, Brian W. Hart
  • Patent number: 8977818
    Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 10, 2015
    Assignee: Apple Inc.
    Inventors: James Wang, Zongjian Chen, James B. Keller, Timothy J. Millet
  • Patent number: 8977808
    Abstract: The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: March 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Zhenlei Shen
  • Publication number: 20150052319
    Abstract: Memory management methods and systems for page-out mechanism are provided. A page-out mechanism is performed via an OS (Operating System) based on a parameter of the page-out mechanism, wherein the page-out mechanism moves data from a memory to a storage unit. A usage of a page-out partition in the storage unit is monitored. The parameter of the page-out mechanism is dynamically set according to the usage of the page-out partition, wherein when the usage is increased, the parameter of the page-out mechanism is decreased, and when the usage is decreased, the parameter of the page-out mechanism is increased.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: HTC Corporation
    Inventors: Abhishek SAXENA, Chien-Lung CHOU, Chun-Hao FAN, Wei-Chun CHEN, Chia-Wei CHEN
  • Patent number: 8959286
    Abstract: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Men-Chow Chiang, Hong L. Hua, Mysore S. Srinivas
  • Patent number: 8930630
    Abstract: The present disclosure relates to a cache memory controller for controlling a set-associative cache memory, in which two or more blocks are arranged in the same set, the cache memory controller including a content modification status monitoring unit for monitoring whether some of the blocks arranged in the same set of the cache memory have been modified in contents, and a cache block replacing unit for replacing a block, which has not been modified in contents, if some of the blocks arranged in the same set have been modified in contents.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 6, 2015
    Assignee: Sejong University Industry Academy Cooperation Foundation
    Inventor: Gi Ho Park
  • Patent number: 8914381
    Abstract: In one embodiment, the correlation filter can use one of several data structure to track each migration unit and reject successive accesses within a period of time to each migration unit. In one embodiment, the correlation filter uses a space efficient data structure, such as a hash indexed correlation array to store the address of referenced migration units, and to filter accesses to a single migration unit that are correlated accesses resulting from multiple accesses to the same migration unit during a sequential I/O stream. In one embodiment, the correlation array contains a global timeout, which resets each element to a default value, clearing all store migration unit address values from the correlation array. In one embodiment, each element of the migration array can time-out separately.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: David A. Majnemer, Wenguang Wang
  • Publication number: 20140365738
    Abstract: Systems and methods for memory page offloading in multi-processor computer systems. An example method may comprise: detecting, by a computer system, a memory pressure condition on a first node; invalidating a page table entry for a memory page residing on the first node; copying the memory page to a second node; and updating the page table entry for the memory page to reference the second node.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Applicant: Red Hat Israel, Ltd.
    Inventors: Ronen Hod, Michael Tsirkin
  • Patent number: 8909880
    Abstract: Method, apparatus, and systems employing novel delayed dictionary update schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Ilan Pardo, Ido Y. Soffair, Dror Reif, Debendra Das Sharma, Akshay G. Pethe
  • Patent number: 8904099
    Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: December 2, 2014
    Assignee: Netlist, Inc.
    Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Patent number: 8904033
    Abstract: Media content is downloaded on a media device. Portions of the media content are buffered successively during the download in a buffer on the device. During the buffering, the buffered portions are read for playback. In the buffer, a non-write buffer region trails behind a current playback read position. Upon the buffering reaching an end of the buffer, the buffering of media content is continued between a buffer beginning and the non-write buffer region.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: December 2, 2014
    Assignee: Adobe Systems Incorporated
    Inventor: Samuli Tapio Kekki
  • Patent number: 8904098
    Abstract: Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: December 2, 2014
    Assignee: Netlist, Inc.
    Inventors: Mike Hossein Amidi, Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
  • Publication number: 20140351532
    Abstract: Destage grouping of tracks is restricted to a bottom portion of a least recently used (LRU) list without grouping the tracks at a most recently used end of the LRU list to avoid the destaging conflicts. The destage grouping of tracks is destaged from the bottom portion of the LRU list.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Michael T. BENHASE, Lokesh M. GUPTA, Matthew J. KALOS
  • Patent number: 8892805
    Abstract: A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 18, 2014
    Assignee: Silicon Graphics International Corp.
    Inventor: Thomas Edward McGee