Least Recently Used (lru) Patents (Class 711/160)
  • Patent number: 8176288
    Abstract: An integrated memory controller (IMC) preferably sits on the main CPU bus or a high speed system peripheral bus and couples to system memory. The IMC may use a lossless data compression and decompression scheme for improved performance. The IMC may also include microcode for specific decompression of particular data formats such as digital video and digital audio. Compressed data may be decompressed in the IMC and stored into system memory or saved in the system memory in compressed format. Internal memory mapping may allow for formal definition spaces which may define the format of the data and the data type to be read or written. Software overrides may be placed in applications software in systems that desire to control data decompression at the software application level.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: May 8, 2012
    Assignee: Mossman Holdings LLC
    Inventor: Thomas A. Dye
  • Patent number: 8171220
    Abstract: Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple cores, which has cache memory elements coupled with the multiple processors or cores. The cache memory device may track usage of cache lines by using a number of bits. For example, a controller of the cache memory may manipulate bits as part of a pseudo least recently used (LRU) system. Some of the bits may be in a centralized area of the cache. Other bits of the pseudo LRU system may be distributed across the cache. Distributing the bits across the cache may enable the system to conserve additional power by turning off the distributed bits.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Anil Krishna
  • Patent number: 8145859
    Abstract: Techniques for managing memory usage of a processing system by spilling data from a memory to a persistent store based upon an evict policy are provided. A triggering event is detected. In response to the triggering event and based on the evict policy, it is determined whether data from the memory of the processing system is to be spilled to the persistent storage. The determination is made by comparing a level of free memory of the processing system with a threshold specified by the evict policy. The data is evicted from the memory.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: March 27, 2012
    Assignee: Oracle International Corporation
    Inventors: Hoyong Park, Namit Jain, Anand Srinivasan, Shailendra Mishra
  • Patent number: 8140757
    Abstract: A compression device recognizes patterns of data and compressing the data, and sends the compressed data to a decompression device that identifies a cached version of the data to decompress the data. Both the compression device and the decompression device cache the data in packets they receive. Each device has a disk, on which each device writes the data in the same order. The compression device looks for repetitions of any block of data between multiple packets or datagrams that are transmitted across the network. The compression device encodes the repeated blocks of data by replacing them with a pointer to a location on disk. The decompression device receives the pointer and replaces the pointer with the contents of the data block that it reads from its disk.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: March 20, 2012
    Assignee: Juniper Networks, Inc.
    Inventors: Amit P. Singh, Balraj Singh, Vanco Burzevski
  • Patent number: 8131683
    Abstract: Methods and systems are provided for retaining and managing global records of an organization. In one implementation, a method is provided for retaining global records of an organization. The method may include storing, in a memory device, at least one arrangement of data items classified according to a hierarchical classification structure providing a normalization scheme for classifying the data items, the data items comprising global data of an organization and a retention schedule corresponding to the global data. Additionally, the method may include retaining the data items according to the retention schedule, wherein the retention schedule comprises a plurality of retention rules including a global retention rule defining a first duration for retaining the data items consistent with a set of predetermined requirements, and at least one exception rule for retaining at least one data item for a second duration.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 6, 2012
    Assignee: UBS AG
    Inventor: Anna C. Fridrich
  • Patent number: 8112589
    Abstract: To ensure efficient access to a memory whose writing process is slow. There is provided a storage device for caching data read from a main memory and data to be written in the main memory, comprises a cache memory having a plurality of cache segments, one or more cache segments holding data matching with data in the main memory being set in a protected state to protect the cache segments from a rewrite state, an upper limit of a number of the one or more cache segments being a predetermined reference number; and a cache controller that, in accordance with a write cache miss, allocates a cache segment selected from those cache segments which are not in the protected state to cache write data and writes the write data in the selected cache segment.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nobuyuki Harada, Takeo Nakada
  • Patent number: 8078826
    Abstract: An embodiment of the invention provides a method for effective memory clustering to minimize page faults and optimize memory utilization. More specifically, the method monitors data access requests to secondary storage and identifies data addresses in secondary storage having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein a cross-sectional partition is created (sliced) from the multi-dimensional cluster. The method receives a request for a data object in secondary storage and identifies a data address corresponding to the requested data object. The data address is mapped to the multi-dimensional cluster and/or the memory page; and, the memory page is transferred to a data cache in primary storage.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: December 13, 2011
    Assignee: International Business Machines Corporation
    Inventor: Maharaj Mukherjee
  • Patent number: 8065496
    Abstract: To reduce the number of bits required for LRU control when the number of target entries is large, and achieve complete LRU control. Each time an entry is used, an ID of the used entry is stored to configure LRU information so that storage data 0 stored in the leftmost position indicates an ID of an entry with the oldest last use time (that is, LRU entry), for example as shown in FIG. 1(1). An LRU control apparatus according to a first embodiment of the present invention refers to the LRU information, and selects an entry corresponding to the storage data 0 (for example, entry 1) from the LRU information as a candidate for the LRU control, based on the storage data 0 as the ID of the entry with the oldest last use time.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Okawa, Hiroyuki Kojima, Masaki Ukai
  • Patent number: 8065497
    Abstract: A data management method, a controller and a storage apparatus thereof are provided. The method is adapted for a storage apparatus having a plurality of blocks. Parts of the blocks are linked to configure a plurality of mother and child blocks (M&C block). The data management method includes: (a) checking whether a mother and child block currently to be written with data is the same of a mother and child block which has been most lately written with data; (b) when it is determined that the mother and child block currently to be written with data is not the same of the mother and child block which has been most lately written with data, saving a transient data of the mother and child block currently to be written with data to a mother and child block transient relationship table.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh
  • Patent number: 8060689
    Abstract: A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 15, 2011
    Assignee: Pitney Bowes Inc.
    Inventors: Wesley A. Kirschner, Gary S. Jacobson, John A. Hurd, G. Thomas Atthens, Steven J. Pauly, Richard C. Day, Jr.
  • Patent number: 8060797
    Abstract: A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
  • Publication number: 20110276770
    Abstract: A method is disclosed for analysing a computing device including a non-volatile storage medium in which a set of snapshots is stored. Each snapshot comprises at least one most recently used, MRU, key for an application, at least one MRU key having a plurality of elements. The method comprises comparing a first MRU key from a first snapshot for a first time and a corresponding second MRU key for a second snapshot for a second time temporally following said first time. If the second MRU key has a second element identified as less recently used than a first element of the second MRU key and the second element of the first MRU key is identified as not being less recently used than the first element of the first MRU key, the first element is labelled as having been newly modified between the first and second times.
    Type: Application
    Filed: January 19, 2010
    Publication date: November 10, 2011
    Applicant: UNIVERSITY COLLEGE DUBLIN, NATIONAL UNIVERSITY OF IRELAND, DUBLIN
    Inventors: Yuandong Zhu, Pavel Gladyshev
  • Publication number: 20110276760
    Abstract: Techniques relating to a processor that supports a non-committing store instruction that is executable during a scouting thread to provide data to a subsequently executed load instruction. The processor may include a memory access unit configured to perform an instance of the non-committing store instruction by storing a value in an entry of a store buffer without committing the instance of the non-committing store instruction. In response to subsequently receiving an instance of a load instruction of the scouting thread that specifies a load from the memory address, the memory access unit is configured to perform the instance of the load instruction by retrieving the value. The memory access unit may retrieve the value from the store buffer or from a cache of the processor.
    Type: Application
    Filed: May 6, 2010
    Publication date: November 10, 2011
    Inventor: Yuan C. Chou
  • Patent number: 8051267
    Abstract: One embodiment of the present invention provides a system that uses versioned pointers to facilitate reusing memory without having to reclaim the objects solely through garbage collection. The system operates by first receiving a request to allocate an object. Next, the system obtains the object from a pool of free objects, and sets an allocated/free flag within the object to indicate that the object is allocated. The system also increments a version number within the object, and also encodes the version number into a pointer for the object. The system then returns the pointer, which includes the encoded version number. In this way, subsequent accesses to the object through the pointer can compare the version number encoded in the pointer with the version number within the object to determine whether the object has been reused since the pointer was generated.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: November 1, 2011
    Assignee: Oracle America, Inc.
    Inventor: David R. Chase
  • Patent number: 7996366
    Abstract: Aspects for identifying stale contents in a file system include processing a set of attributes of each file in the file system. These aspects further also include determining access times at the directory level, recursively, from all the files in lower-level directories. The aspects further include identifying the highest-level stale directories in the file system.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: August 9, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventor: Carl T. Smith
  • Patent number: 7984243
    Abstract: A cache memory according to the present invention includes a W flag setting unit that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order and a replace unit that selects a cache entry for replacement based on the modified order data and replaces the cache entry.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: July 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Hazuki Kawai, Ryuta Nakanishi, Tetsuya Tanaka, Shuji Miyasaka
  • Patent number: 7970985
    Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: June 28, 2011
    Assignee: SanDisk Corporation
    Inventors: Carlos J. Gonzalez, Alan Douglas Bryce, Sergey Anatolievich Gorobets, Alan David Bennett
  • Patent number: 7970989
    Abstract: A hard disk cache includes entries to be written to a disk, and also includes ordering information describing the order that they should be written to the disk. Data may be written from the cache to the disk in the order specified by the ordering information. In some situations, data may be written out of order. Further, in some situations, clean data from the cache may be combined with dirty data from the cache when performing a cache flush.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventor: Jeanna N. Matthews
  • Patent number: 7962708
    Abstract: Resolving retention policy conflicts is disclosed. An indication is received that two or more retention policies apply to an item of content. A merged retention policy that is based at least in part on the respective requirements of the two or more retention policies is generated automatically for the item of content.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: June 14, 2011
    Assignee: EMC Corporation
    Inventors: Roger W. Kilday, John-David Dorman, David Humby, Fiona Schrader, Dan Bailey
  • Patent number: 7962807
    Abstract: It is an object to provide a semiconductor storage apparatus managing system for implementing a semiconductor storage apparatus which can be actually utilized in place of a hard disk apparatus. A semiconductor storage apparatus managing system SY for managing an apparatus lifetime of a semiconductor storage apparatus 10 having a semiconductor memory area 15 for storing data and a defective block substituting area 16 for substituting a defective block in the semiconductor memory area 15,includes a storage apparatus side controller 12 for detecting the number of consumed blocks in the defective block substituting area 16 and a host side controller 31 for predicting the apparatus lifetime of the semiconductor storage apparatus 10 based on a result of the detection and giving a notice of a result of the prediction.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: June 14, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Jinichi Nakamura
  • Patent number: 7953953
    Abstract: A method and apparatus for reducing a page replacement time in a system using a demand paging technique are provided. The apparatus includes a memory management unit which transmits a signal indicating that a page fault occurs, a device driver which reads a page having the page fault from a nonvolatile memory, and a page fault handler that searches and secures a space for storing the page having the page fault in a memory. The searching and securing of the space in the memory is performed within a limited time calculated beforehand and a part of data to be loaded to the memory of the system is stored in the nonvolatile memory.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-hyun In, Il-hoon Shin, Hyo-jun Kim
  • Publication number: 20110113205
    Abstract: A data storage device connectable to an electronic device and a remote storage serve, which comprises memory managing means configured to receive a request for a piece of information from the electronic device and if said piece of information is stored both in a local memory of the data storage device and in the remote server, retrieving the requested piece of information from the local memory to reduce latency.
    Type: Application
    Filed: October 5, 2010
    Publication date: May 12, 2011
    Applicant: TELEFONICA, S.A.
    Inventors: Javier Garcia Puga, Francisco Javier Perez Gonzalez, Juan J. Hierro Sureda, Nikolaos Tsouroulas, Luis M. Vaquero Gonzales, Luis Rodero Merino
  • Publication number: 20110107041
    Abstract: A method is for executing n data updates in an IC Card which has memory pages supporting m erase operations per page, with m<n. The method includes the step of allocating a cyclic elementary file including N records, each record associated to a memory page of the IC Card, and the cyclic elementary file indexing a less recently updated record which is erased before writing data to be updated.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 5, 2011
    Applicant: INCARD S.A.
    Inventors: Saverio DONATIELLO, Corrado Guidobaldi, Mariangela Rauccio
  • Patent number: 7937543
    Abstract: A method for automatically determining performance problems in a computer system due to a metric indicating a current memory peak load in the computer system is disclosed.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Bernard R Pierce, Elpida Tzortzatos, Dieter Wellerdiek
  • Patent number: 7925849
    Abstract: A bus arbiter receives requests of initiators, and internally includes a page hit/miss determining unit with permissible determining function, a bank open/close determining unit with permissible determining function, and an LRU unit with permissible determining function. Regarding the priority of the request arbitration on the requests, the bank priority on the SDRAM is determined in the order of page hit, bank open, and LRU. Furthermore, each determining unit internally includes a permissible time determining unit, and processes, at top priority, the request of the initiator which the corresponding permissible time is below the count threshold value in the priority processing of the determining unit.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: April 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuji Izumi
  • Patent number: 7870352
    Abstract: A system is described for managing memory, the system including, among other things, a memory with logic and a processor configured with the logic to receive an indication of an application state from a plurality of applications in memory and determine which of the plurality of applications to effect removal from the memory based on the received indication.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 11, 2011
    Inventor: Altan J. Stalker
  • Patent number: 7861041
    Abstract: A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: December 28, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James D Williams
  • Patent number: 7836257
    Abstract: A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corpation
    Inventors: Robert John Dorsey, Jason Alan Cox, Hien Minh Le, Richard Nicholas, Eric Francis Robinson, Thuong Quang Truong
  • Patent number: 7836230
    Abstract: Management of requests from a host to an external storage medium. An execution queue stores commands to be executed, and each command corresponds to a request from the host for data. A holding queue stores executed commands until receipt of an acknowledgment from the host that the host has, e.g., received the data corresponding to the command from the external storage medium. An outgoing queue stores acknowledged commands and has a maximum storage limit. A counter is provided, and a separate logic block increments the counter when a command is stored in the execution queue and decrements the counter when an acknowledged command is deleted from the outgoing queue. The separate logic disables execution of commands stored in the execution queue when the value of the counter equals the maximum storage limit of the outgoing queue.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: November 16, 2010
    Assignee: Marvell International Ltd.
    Inventors: William C. Wong, Huy Tu Nguyen, Kha Nguyen
  • Publication number: 20100257291
    Abstract: System and method for a four-slot asynchronous communication mechanism with increased throughput. The system may include a host system and a client device. The host may comprise a data structure with four (two pairs of) slots and first information indicating a status of read operations from the data structure by the host. The client may read the first information from the host. The client may read second information from a local memory. The second information may indicate a status of write operations to the data structure by the client. The client may determine a slot of the data structure to be written. The slot may be determined based on the first information and the second information and may be the slot which has not been written to more recently of the pair of slots which has not been read from most recently. The client may increment a value of a counter. The value of the counter may be useable to indicate which slot has been written to most recently.
    Type: Application
    Filed: April 3, 2009
    Publication date: October 7, 2010
    Inventors: Rodney W. Cummings, Eric L. Singer
  • Publication number: 20100211731
    Abstract: Methods, systems, and computer programs for managing storage in a computer system using a solid state drive (SSD) read cache memory are presented. The method includes receiving a read request, which causes a miss in a cache memory. After the cache miss, the method determines whether the data to satisfy the read request is available in the SSD memory. If the data is in SSD memory, the read request is served from the SSD memory. Otherwise, SSD memory tracking logic is invoked and the read request is served from a hard disk drive (HDD). Additionally, the SSD memory tracking logic monitors access requests to pages in memory, and if a predefined criteria is met for a certain page in memory, then the page is loaded in the SSD. The use of the SSD as a read cache improves memory performance for random data reads.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 19, 2010
    Applicant: Adaptec, Inc.
    Inventors: Steffen Mittendorff, Dieter Massa
  • Patent number: 7769970
    Abstract: A unified memory controller (UMC) is disclosed. The UMC may be used in a digital television (DTV) receiver. The UMC allows the DTV receiver to use a unified memory. The UMC accepts memory requests from various clients, and determines which requests should receive priority access to the unified memory.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 3, 2010
    Assignee: Zoran Corporation
    Inventors: Gerard Yeh, Ravi Manyam, Viet Nguyen
  • Publication number: 20100191925
    Abstract: A method, system, and computer program product for managing modified metadata in a storage controller cache pursuant to a recovery action by a processor in communication with a memory device is provided. A count of modified metadata tracks for a storage rank is compared against a predetermined criterion. If the predetermined criterion is met, a storage volume having the storage rank is designated with a metadata invalidation flag to defer metadata invalidation of the modified metadata tracks until after the recovery action is performed.
    Type: Application
    Filed: January 28, 2009
    Publication date: July 29, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence Carter BLOUNT, Lokesh Mohan GUPTA, Carol Santich MELLGREN, Kenneth Wayne TODD
  • Publication number: 20100169588
    Abstract: A method and system writes data to a memory device including writing data to varying types of physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. Depending on whether the quantity of valid data in the memory device meets a predetermined criteria, the data is written to a specific chaotic block, a general chaotic block, or a mapped block. The mapped block is assigned for writing data for the LBA range, the specific chaotic block is assigned for writing data for contiguous LBA ranges including the LBA range, and the general chaotic block is assigned for writing data for any LBA range. Lower fragmentation and write amplification ratios may result by using this method and system.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventor: Alan W. Sinclair
  • Publication number: 20100169542
    Abstract: A method and system writes data to a memory device including dynamic assignment of logical block addresses (LBAs) to physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. The method assigns the LBA range to a particular write block exclusively or non-exclusively, depending on the existence of previously assigned write blocks and the availability of unwritten blocks. A data structure may be utilized to record the recent usage of blocks for assigning non-exclusive write blocks. An intermediate storage area may be included that implements the dynamic assignment of LBA ranges to physical write blocks. Data in the intermediate storage area may be consolidated and written to the main storage area. Lower fragmentation and write amplification ratios may result by using this method and system.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventor: Alan W. Sinclair
  • Patent number: 7747812
    Abstract: A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 29, 2010
    Assignee: Pitney Bowes Inc.
    Inventors: Wesley A. Kirschner, Gary S. Jacobson, John A. Hurd, G. Thomas Athens, Steven J. Pauly, Richard C. Day, Jr.
  • Patent number: 7747821
    Abstract: A compression device recognizes patterns of data and compressing the data, and sends the compressed data to a decompression device that identifies a cached version of the data to decompress the data. In this way, the compression device need not resend high bandwidth traffic over the network. Both the compression device and the decompression device cache the data in packets they receive. Each device has a disk, on which each device writes the data in the same order. The compression device looks for repetitions of any block of data between multiple packets or datagrams that are transmitted across the network. The compression device encodes the repeated blocks of data by replacing them with a pointer to a location on disk. The decompression device receives the pointer and replaces the pointer with the contents of the data block that it reads from its disk.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: June 29, 2010
    Assignee: Juniper Networks, Inc.
    Inventors: Amit P. Singh, Balraj Singh, Vanco Burzevski
  • Patent number: 7743205
    Abstract: A system and method for use in an automated data storage cartridge library defines cartridges for use with an external host computer (“open” cartridges), and cartridges for use only internal to the library (“closed” cartridges). Cartridges may be “virtualized” by storing data from them on disk or closed cartridges, and then “realized” by writing data to physical cartridges. Virtual cartridges may be logically exported from one library to another. When new cartridges are introduced to the library, they may be designated with one of multiple designations or uses.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: June 22, 2010
    Assignee: Quantum Corporation
    Inventors: Barry Massey, Don Doerner, Stephen Moore, John Rockenfeller, Jeff Leuschner, Doug Burling, Roderick B. Wideman
  • Patent number: 7743211
    Abstract: A storage system 1 includes: plural protocol transformation units 10 that transform, to a protocol within the system, a read/write protocol of data exchanged with servers 3 or hard disk groups 2; plural cache control units 21 that include cache memory units 111 storing data read/written with the servers 3 or the hard disk groups 2 and which include the function of controlling the cache memory units 111; and an interconnection network 31 that connects the protocol transformation units 10 and the cache control units 21. In this storage system 1, the plural cache control units 21 are divided into plural control clusters 70, control of the cache memory units 111 is independent inside the control clusters, and a system management unit 60 that manages, as a single system, the plural protocol transformation units 10 and the plural control clusters 70 is connected to the interconnection network 30.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: June 22, 2010
    Inventors: Kazuhisa Fujimoto, Mutsumi Hosoya, Kentaro Shimada, Akira Yamamoto, Naoko Iwami, Yasutomo Yamamoto
  • Publication number: 20100153630
    Abstract: A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 17, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Keunsoo Yim, Jeongjoon Yoo, Jungkeun Park
  • Publication number: 20100122049
    Abstract: A system and method for managing an electronic storage volume is described. The method includes assigning a threshold to a constrained storage space to define a first state in which an amount of data stored in the constrained storage space exceeds the threshold and a second state in which the amount of data stored in the confined storage space does not exceed the threshold. The method also includes comparing the amount of data to be stored in the constrained storage space and the threshold, and performing a predefined action if the comparison indicates that the amount data to be in the confined storage space would cause a transition between the first state and the second state.
    Type: Application
    Filed: January 19, 2010
    Publication date: May 13, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruthie D. Lyle, Fonda Daniels, Andrew L. Schirmer
  • Patent number: 7669009
    Abstract: A method and apparatus for selecting and updating a replacement candidate in a cache is disclosed. In one embodiment, a cache miss may initiate the eviction of a present replacement candidate in a last-level cache. The cache miss may also initiate the selection of a future replacement candidate. Upon the selection of the future replacement candidate, the corresponding cache line may be invalidated in lower-level caches but remain resident in the last-level cache. The future replacement candidate may be updated by subsequent hits to the replacement candidate in the last-level cache prior to a subsequent cache miss.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventors: Sailesh Kottapalli, John H. Crawford
  • Publication number: 20090327625
    Abstract: Provided are a method, system, and article of manufacture for managing metadata for data blocks used in a deduplication system. File metadata is maintained for files having data blocks in a computer readable device. Data block metadata is maintained for each data block in the computer readable device. The data block metadata for one data block includes a data block reference and content identifier identifying content of the data block. The file metadata for each file includes the data block reference to each data block in the file. A determination is made of an unreferenced data block in the computer readable device that has become unreferenced. Indication is made that the data block metadata for the determined unreferenced data block as unreferenced metadata. The data block reference of the unreferenced metadata is maintained in the computer readable device in response to determining that a includes the data block indicated in the unreferenced metadata.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Glen Alan Jaquette, Gregory Tad Kishi
  • Patent number: 7640544
    Abstract: A multiprocessor, multi-program, stop-the-world garbage collection program is described. The system initially over partitions the root sources, and then iteratively employs static and dynamic work balancing. Garbage collection threads compete dynamically for the initial partitions. Work stealing double-ended queues, where contention is reduced, are described to provide dynamic load balancing among the threads. Contention is resolved by using atomic instructions. The heap is broken into a young and an old generation where parallel semi-space copying is used to collect the young generation and parallel mark-compacting the old generation. Speed and efficiency of collection is enhanced by use of card tables and linking objects, and overflow conditions are efficiently handled by linking using class pointers. A garbage collection termination employs a global status word.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: December 29, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Christine H. Flood, David L. Detlefs, Nir N. Shavit, Xiaolan Zhang, Ole Agesen
  • Publication number: 20090300397
    Abstract: The invention provides a method, apparatus and system for reducing power consumption involving data storage devices. One embodiment involves storing data in a first memory; in response to the first memory exceeding a first threshold, migrating the data from the first memory to a second memory; in response to the second memory exceeding a second threshold, then activating a third memory if the third memory is in active; and in response to the second memory exceeding a third threshold greater than the second threshold, migrating the data from the second memory to a third memory; wherein the second memory is sized and configured to store data targeted for the third memory to intelligently maintain a portion of the third memory in an inactive state.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 3, 2009
    Applicant: International Business Machines Corporation
    Inventors: Lu Nguyen, Mark J. Seaman
  • Publication number: 20090276588
    Abstract: Embodiments of the invention include first storage mediums having first storage characteristics for making up a first pool of capacity of a first tier of storage, and second storage mediums having second storage characteristics for making up a second pool of capacity of a second tier of storage. Free capacity of the first and second pools is shared between the first and second tiers of storage. When the first pool has an amount of free capacity available over a reserved amount of free capacity reserved for first tier data, a first quantity of second tier data is moved from the second tier to the first tier. In exemplary embodiments of the invention, the first and second storage mediums are contained within one or more thin provisioning storage systems, and data is moved between the first and second tiers by allocating thin provisioning chunks to the data being moved.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 5, 2009
    Inventor: Atsushi Murase
  • Patent number: 7600086
    Abstract: Provided is a method for managing retention of stored objects, comprising: receiving a modification request with respect to an attribute or archive policy for an object; determining whether an attribute modification protection flag or setting is set in response to the modification request requesting to modify the attribute for the object; allowing the modification of the attribute object in response to determining that the attribute modification protection flag or setting is not set; determining whether a protection retention mechanism or setting is set in response to the modification request requesting to modify the archive policy for the object; and allowing the modification of the archive policy for the object in response to determining that the protection retention mechanism or setting is not set.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: October 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Avishai Haim Hochberg, Toby Lyn Marek, David Maxwell Cannon, Howard Newton Martin, Donald Paul Warren, Jr., Mark Alan Haye, Alan L. Stuart
  • Patent number: 7596793
    Abstract: An autonomic event parser configured for association with a message adapter. An autonomic event parser can include a store of parsing rules, the parsing rules having a strategically specified order. Additionally, a pattern analyzer can be programmed to identify patterns of received messages and to recommend the strategically specified order of the parsing rules. Finally, a parsing rules manager can be communicatively coupled both to the pattern analyzer and the store of parsing rules, the parsing rules manager having a configuration for ordering the parsing rules in the store based upon the recommended order of the pattern analyzer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: Genady Grabarnik, Sheng Ma, Chang-shing Perng, Abdolreza Salahshour
  • Patent number: 7596672
    Abstract: A destination storage server, which may be a filer, mirrors a volume managed by a source storage server, which may also be a filer. According to an embodiment of the invention, changes made to the source volume are logged and persistently stored on a data container, such as a file, on the destination volume. The source storage server is coupled to clients that make data access requests to the volume. When an access request is made by a client, the request is written to a log on the source storage server. At the same time, the request is written to a data container on a volume managed by the destination storage server. Each source storage server coupled to the destination storage server has its own file on the volume.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: September 29, 2009
    Assignee: Network Appliance, Inc.
    Inventors: Abhijeet Gole, Nitin Muppalaneni, Mark Smith, Mike Federwisch
  • Patent number: 7594082
    Abstract: Resolving retention policy conflicts is disclosed. An indication is received that two or more retention policies apply to an item of content. A merged retention policy that is based at least in part on the respective requirements of the two or more retention policies is generated automatically for the item of content.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: September 22, 2009
    Assignee: EMC Corporation
    Inventors: Roger W. Kilday, John David Dorman, David Humby, Fiona Schrader, Dan Bailey