Abstract: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment, the register is located external to the memory and used by a processor and/or chip set to determine if an access request is needed.

Abstract: A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

Abstract: A method of storing a bit-pattern in each of a plurality of devices having respective memories is provided. The method comprises, for each device, determining a first memory location and storing the bit-pattern at the first memory location. The first memory locations at which the bit-pattern is stored are different in at least a plurality of the respective devices.

Abstract: An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A coupling facility is coupled to one or more other coupling facilities via one or more peer links. The coupling of the facilities enables various functions to be supported, including the duplexing of structures of the coupling facilities. Duplexing is performed on a structure basis, and thus, a coupling facility may include duplexed structures, as well as non-duplexed or simplexed structures.

Abstract: In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a processor. This sequence of operations, including instructions from the plurality of sets of operations, ensures that there is another operation in the pipeline if a cache miss on any given lookup operation in the mapping array results in a slower main memory access. In this way, the processor utilization is improved. While the sets of operations in the sequence of operations are independent of another other, there will be an overlap of a plurality of the main memory access operations due to the long time required for main memory access.

Abstract: In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in correspondence with a plurality of tasks. An address receiving unit receives, from a microprocessor, an address of a location in a main memory at which data to be accessed to execute one of the plurality of tasks is stored. A caching unit acquires, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and stores the acquired data block into a region in the cache memory corresponding to the task.

Abstract: A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Abstract: A method is provided of storing at least one functionally identical code segment in each of a plurality of devices which each have a memory. For each device, the method determines a first memory location and stores a first of the code segments in the memory at the first memory location. The first memory location is different in at least a plurality of the respective devices.

Abstract: Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer. A DMA controller may claim the interrupt and may prevent a processor from receiving and/or servicing the claimed interrupt. The DMA controller may further transfer a data block in response to the claimed interrupt.

Abstract: The present invention provides a central processing unit-containing large-scale integration (hereinafter, referred to as a “CPU-containing LSI”) in which software stored in an external memory is incorporated partially into a random access memory (hereinafter, referred to as “RAM”) and thereby the capacity of the RAM to be used can be held down, and an optical disk device including the same. In the CPU-containing LSI, the RAM includes a software storage region where software read in from the external memory on a module-by-module basis is stored, and an entry table in which entries are stored, with the entries each containing at least information as to a location and a size of a module stored in the software storage region. The CPU refers to the entry table to decide the location where a module to be read in from the external memory to the software storage region is to be stored, according to an incorporation-location search program.

Abstract: A tape mirror interface comprises an input terminal coupled to at least one input node and capable of receiving data transfer requests, a plurality of output terminals coupled to a plurality of tape storage devices, and a control element coupled to the input terminal and plurality of output terminals. The control element presents the plurality of tape storage devices as separate media devices and selectively controls data transfer in a synchronous mode and a split mode. In the synchronous mode, writes to a target tape storage media are mirrored to a mirrored tape storage media. In the split mode, writes are written to tape storage devices independently.

Abstract: A system and method for lock caching for compound atomic operations (i.e. a read or write operation to more than one 4-byte word) on shared memory is provided. In a computer system including a memory shared among a plurality of processing entities, for example, multiple threads, a method of performing compound atomic operations comprises providing a pool of locks for synchronizing access to the memory; assigning the locks among the plurality of entities to minimize lock contention; and performing the compound atomic operations using the assigned locks. Each lock may be assigned in accordance with an address of the shared memory from the processing entity's compound atomic operations. Assigning locks may be performed in a manner to minimize concurrent atomic updates to the same or overlapping portions of the shared memory.

Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.

Abstract: A method and apparatus are provided for accessing a dynamic memory device. The method comprises receiving a command from a controller to access a memory, receiving, from the controller, at least one of burst length information and latency information in association with the command to access the memory; and providing data to or from the memory in response to the command based on at least one of the burst length information and the latency information.

Abstract: A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance criteria for the blocks of concurrent code to reduce overall execution time of the concurrent code. In one embodiment, the scheduler may be configured to schedule code blocks having a longer run time ahead of blocks having a shorter run time. The scheduler may be configured to schedule a group of said blocks based on a goal of each of the blocks of the group completing execution at approximately the same time. The scheduler may also be configured to initiate multi-threaded execution of each block of the group at different times according to the block-level performance criteria to the goal.

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract: According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.

Abstract: A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: Provided are a method, system, and program to allocate tasks among a plurality of processes within a distributed processing environment. Each process secures a list of elements and performs a first operation on an element of the list to produce a result corresponding to one of the processes. If the result corresponds to the process processing the element, the process performs a second operation on the element. Each process then processes the next element on the list until all the elements of the list are processed. After the process processes all the elements on the list it further processes each element remaining on the list and performs the second operation on the elements remaining on the list. In one implementation, the distributed processing environment is a peer-to-peer virtual storage system and each process runs on a controller controlling a plurality of storage systems.

Abstract: A memory control unit and a memory unit is connected to each other by a bus used for transfer of address, data and control signals. The memory control unit outputs a first command including a first predetermined location in the memory unit, to the memory unit. The memory control unit outputs a second command including a second predetermined location in the memory unit, to the memory unit when a predetermined time period has elapsed since the output of the first command.

Abstract: A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder is coupled between a respective system bus and a respective system bus port of the memory controller.

Abstract: When storage controllers are added to a storage system to change the storage system from a configuration having only one storage controller to a configuration having plural storage controllers, or when storage controllers are removed from the storage system to change the storage system from a configuration having plural storage controllers to a configuration having only one storage controller, a controller-internal management-information memory controller carries out a copy process to copy management information from each of the storage controllers to a management-information-memory switch or vice versa at the same time as processing of read and write requests for access to the management information, made by a channel interface or a disc interface, in order to change storage locations of the management information while processing the read and write requests made by the host.

Abstract: A system for sharing a computational resource by buffering multiple requests from multiple devices to a memory (e.g. a multi-port RAM or FIFO) in a single clock cycle. The system includes a memory having a first write port and a second write port. A first request input is coupled to the first write port. A second request input is coupled to the second write port. A controller is coupled to the memory. The controller is configured to control the memory to store a first request into the memory via the first write port and a second request into the memory via the second write port. The first and second requests are received via the first and second request inputs and stored into the memory in one clock cycle. Requests are removed from the memory sequentially at a rate that is determined by the shared computational resource.

Abstract: A synchronous semiconductor memory device allows one memory bank to begin executing a data operation (e.g., reading data from a memory cell) while another memory bank is executing another data operation (e.g., writing data to a memory cell). The synchronous semiconductor memory device includes a write data path through which an input data signal is transmitted to the memory cell of a memory bank executing a write operation, and a read data path through which an output data signal is transmitted from the memory cell of a memory bank executing a read operation to an input/output pin. The read and write data paths are each connected to the memory banks via a common input/output line.

Abstract: Client and server based copies of a file are maintained in synchronicity as changes are made to the file. Data is compared to a previous version known to both the client and server and a highly compressed representation of the differences between the two is generated. These differences, or “diffs”, are then transmitted, and may use extensions to the HTTP (HyperText Transport Protocol) protocol.

Abstract: A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.

Abstract: A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.

Abstract: A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

Abstract: Each of a plurality of storage devices (N?1 to N-n) has a plurality of memory blocks for storing data. A data writing apparatus obtains error information which represents good blocks which can store data correctly, from the plurality of storage devices (N?1 to N-n). The data writing apparatus determines a memory block in which data is to be written, in each of the plurality of storage devices (N?1 to N-n), based on the obtained error information. The data writing apparatus controls the plurality of storage devices (N?1 to N-n), and writes predetermined data in the determined memory blocks.

Abstract: The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.

Abstract: A system for storing and retrieving data provided by the system on a system bus in a sequence at a predetermined system data rate. The system includes a system memory controller for enabling a system memory to store and retrieve the data at a rate twice the system data rate. Also provided is a trace buffer having a dual port random access memory. A trace buffer control system is provided for enabling the data on the system bus and fed concurrently to a pair of data ports of the dual port random access memory to be stored in the dual port random access memory at the predetermined system data rate and for enabling such dual port random access memory stored data to be retrieved from the dual port random access memory in the same sequence as such data was provided on the system data bus.

Abstract: A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.

Abstract: A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.

Abstract: A memory controller system for processing memory access requests comprising a first memory controller operable to address a first plurality of memory modules a second memory controller operable to address a second plurality of memory modules, the first and second memory controllers configurable to process a memory transaction in an operational mode of the memory controller system selected from the group consisting of an independent cell mode, a multiplexer-mode (mux-mode), and a lockstep mode, and a bus interface block operable to convey the memory transaction to both of the first and second memory controllers is provided.

Abstract: A highly parallel data storage chip device providing a plurality of parallel data tracks allocated into separate physical groups upon a data storage medium. A controller establishes logical groups of data tracks located in different physical groups. A servo track provides tracking information for a plurality of read/write devices that move relative to the length of each data track, thereby permitting parallel data transfer between the read/write devices and the distributed data tracks of the logical group.

Abstract: A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Abstract: One or more servers are adapted to execute tape application programs. A controller provides communications between the one or more servers and a random access storage device. The controller is configured so that the application programs can concurrently access the random access storage device as a sequential access tape storage device.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.

Abstract: A system-on-a-chip is described herein. The system-on-a-chip includes a microprocessor, a non-volatile imperfect semiconductor memory device and a memory controller. The memory controller is configured to transfer device data between the microprocessor and the non-volatile semiconductor imperfect memory device.

Abstract: A semiconductor memory device includes a memory core circuit, a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle, a timing generator configured to request a read access to the memory core circuit immediately after inputting of a read command if a command supplied from the exterior to the command circuit is the read command, to perform a read operation on the memory core circuit immediately after the request of the read access if there is no currently performed operation in the memory core circuit, to request a write access to the memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to the write access is entered from the exterior to the command circuit, to perform a write operation on the memory core circuit immediately after the request of the write access if there is no currently performed operation in the memory core circuit, and to control an order of a plurality

Abstract: A system and method are disclosed for providing a synchronization mechanism for access to shared information. According to an embodiment of the present invention, a lock with more than one part can be obtained or leased by writing to the first part, writing to the second part, reading the first part to determine whether the first part reads what was written to it, and obtaining the lock if what is read is the same as what was written.

Abstract: In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.

Abstract: A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.

Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

Abstract: A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.

Abstract: A memory management system for resolving contention for access to a plurality of memories. Signals are continuously applied to an access flow regulator indicating the busy/idle state of each memory. The access flow regulator uses the received signals to determine the present busy/idle state of each of the memories. Requests are applied to the access flow regulator for read and write access to the memories. The access flow regulator operates in response to a determination that one of the memories is currently idle for granting a request access to a memory as soon as it switches from a busy to and idle state.

Abstract: A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence of 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.