Abstract: The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory device can be, e.g., a memory card, a multimedia card or a secure digital card, etc. A new command or commands can be used to inform a memory device controller when the data in one particular sector, allocation unit or block can be deleted. Using that information the memory device controller then can be able to do some internal maintenance, e.g., by moving valid data from a fragmented erase block to another so that the fragmented erase block can be cleared and erased for future use as well as performing effective wear leveling maintenance and write performance optimization.

Abstract: A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has improved throughput performance in part because it can function without precharge signals, row address latch signals, and column address latch signals, among others. The transparent memory array further comprises a plurality of row address decoders, each having a row address input bus and a row address output bus. One row address decoder's input bus is connected to the processor, while its output bus is connected to a first memory bank. The memory array is also comprised of a plurality of column address decoders, each having a column address input bus and a column address output bus. One column address decoder's input bus is connected the processor, while its output bus connected to the first memory bank.

Abstract: The portion of a source block storage resource to be replicated, and the corresponding portion of the block storage resource being written to, are each divided into a predefined number of equal-sized spans. A digest calculation is then generated for each span in a corresponding pair and compared. If the digests do not match, those spans are divided into still smaller spans, and digests are calculated and compare iteratively, to identify smaller areas of discrepancies and reduce the number of blocks that are actually written.

Abstract: An embodiment of the present invention provides a computer system including a first memory and a second memory, where the first memory is substantially faster than the second memory. A method includes steps of: inspecting a request queue for block requests from a plurality of concurrent calling processes, the request queue including a plurality of block requests not yet processed by any of the plurality of concurrent calling processes; retrieving one of the plurality of block requests, wherein each block is accessed at most once by each calling process; determining whether the retrieved block request can be fulfilled from the first memory; and returning the retrieved block to the calling process whose state indicates that the block is needed if the retrieved block request can be fulfilled from the first memory.

Abstract: A storage network control apparatus is operable to present virtualized storage to a host system and includes a monitoring component, an analysis component, a detection component, and a migration component. The monitoring component is for monitoring input/output (I/O) activity for virtual storage logical units over time. The analysis component is for identifying a repeating instance of peak I/O activity for a virtual storage logical unit over time and for generating a predictive signature therefrom. The detecting component is for identifying an instance of such a predictive signature. The migration component is responsive to the detecting component, and is for migrating data mapped by the virtual storage logical unit across additional real storage units to improve the I/O performance of the virtual storage logical unit prior to a recurrence of the repeating instance of peak I/O activity. A corresponding logic arrangement may be incorporated in hardware, software or a combination thereof.

Abstract: Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory corresponding to the image. The data operations include a first data operation involving a first read operation followed by a first write operation, and a second data operation involving a second read operation followed by a second write operation. After starting the first read operation, a determination is made whether data associated with the first data operation overlaps with data associated with the second data operation. If a data overlap occurs, the second read operation is started after the first write operation is completed, and if no data overlap occurs, the second read operation is started before the first write operation is completed.

Abstract: The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a semiconductor memory device. Two memory chips are sequentially selected in the way of combinations different from each other from within a plurality of memory chips each having a first storage area and a second storage area. Data are simultaneously read from the first storage area of one of the selected two memory chips and the second storage area of the other thereof.

Abstract: A hard disk drive (HDD) emulator comprises a dynamic random access memory, a controller that refreshes content of the dynamic random access memory, and an input/output port coupled to the controller. The input/output port provides a hard disk drive interface. An operating system of a computing system in which the HDD emulator is installed uses the dynamic random access memory as a swap storage space.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.

Abstract: A memory controller includes a memory diagnosing part for controlling access from a CPU to a memory, and accessing and diagnosing the memory, an information setting part for setting cycle information according to a loaded condition of the CPU, and a cycle adjusting part for adjusting a cycle for the memory diagnosing part to access the memory based on the cycle information of the information setting part.

Abstract: A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

Abstract: A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem to access desired storage locations within the memory subsystem.

Abstract: The present invention relates to a system and methodology to mitigate memory current requirements in an industrial controller and to facilitate efficient on-line editing, storage and retrieval of user programs and data. A segmented memory architecture is provided, wherein a first memory segment is loaded with programmed instructions and other data that is relatively static in nature. A second memory segment is provided for storage of dynamic information such as controller data table variables that change frequently and/or rapidly during program execution of the controller. An execution memory is concurrently loaded with the user program to facilitate high performance program execution and to enable on-line edits of the user program during operation of the controller.

Abstract: Disclosed are interface buses that facilitate communications among two or more electronic devices in standard mode and burst mode, and bus bridges from such buses to a memory unit of such a device. In one aspect, interface buses group the data lines according to groups of bits, and include group-enable lines to convey a representation of which groups of data lines are active for each data transfer operation. In another aspect, exemplary interface buses include burst-length lines to convey a representation of the number of data bursts in a burst sequence, thereby obviating the need to provide sequential addresses over the bus. Exemplary bus bridges are capable of interpreting the signals on the interface bus and transferring data bursts between the interface bus and one or more memory units within the device.

Abstract: In response to requests for I/O processing sent from a computer, I/O which should be processed at a priority is enabled to be processed without being affected by other processing, by classifying I/O into those to be processed at a priority and those not to be processed at a priority. The storage control apparatus comprises an I/O processing controller with a memory that is common for the whole controller. The storage control apparatus manages information for dividing and controlling a plurality of I/O processes as priority and non-priority in that memory and operates while suppressing non-priority I/O processing on the basis of information in the memory.

Abstract: A main LSI includes a plurality of master circuits that transmit access requests to an SDRAM, an input interface that receives an access request from a master circuit in a sub LSI, an arbitration circuit that receives the access requests from the internal master circuits and from the input interface, sequentially selects, in accordance with a predetermined arbitration rule, a master circuit to be allowed to access the SDRAM, and determines output timings for addresses pertaining to the data transfers from the sequentially selected master circuits, and an access signal generation circuit that causes the sequentially selected master circuits to access the SDRAM in accordance with the corresponding output timings.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: An address processing section allocates addresses of desired data in a main memory, input from a control block, to any of three hit determination sections based on the type of the data. If the hit determination sections determine that the data stored in the allocated addresses does not exist in the corresponding cache memories, request issuing sections issue transfer requests for the data from the main memory to the cache memories, to a request arbitration section. The request arbitration section transmits the transfer requests to the main memory with priority given to data of greater sizes to transfer. The main memory transfers data to the cache memories in accordance with the transfer requests. A data synchronization section reads a plurality of read units of data from a plurality of cache memories, and generates a data stream for output by a stream sending section.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus.

Abstract: A dual storage apparatus is provided that comprises a first and a second memories for respectively retaining a set of identical data and a selector for selecting either of the two (2) sets of the data respectively read from the first and the second memory based on a read control signal inputted into the selector, having a request management unit for, when the read control signal has been inputted, attaching an identifier for identifying the read control signal to the inputted read control signal and outputting the signal and the identifier; and a plurality of memory control units for each of the first and the second memories. The dual storage apparatus detects a synchronization error by verifying coincidence of the identifier attached by the request management unit and controls the selector such that the data from a system from which no synchronization error has been detected.

Abstract: One goal of consistency interval replication is to achieve a consistent copy of data generated by independent streams of writes from nodes in a clustered/distributed environment. Two writes to the same block from different nodes may arrive at a replication target in a different order from the order in which they were written to primary storage. A consistency interval coordinator may analyze a list of blocks modified during a consistency interval to determine conflict blocks written to by two different nodes during the same consistency interval. Conflict resolution may involve a node reading data for a conflict block from primary storage and forwarding it to the replication target or a node completing a suspended in-progress write for the conflict block. Once the conflicts have been resolved, the replication target may checkpoint the data modified during the interval and nodes may resume writes to the conflict blocks for the new interval.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: Methods and apparatus for use with memory systems and memory modules are included among the embodiments. In exemplary systems, error-correction coding (ECC) data is temporally multiplexed with user data on the same data bus lines in a burst mode transfer, such that separate chips and data lines are not required to support ECC. The memory devices on the modules each contain additional indirectly addressable ECC segments associated with addressable segments of the device. The temporally multiplexed ECC data is read from and written to the indirectly addressable segment associated with the addressable data transmitted in the burst mode transfer. In some embodiments, two types of burst modes are supported, one which includes ECC data and one which does not. This allows one type of memory module to support both ECC and non-ECC systems, and in some cases to use ECC for some data and not for other data in the same system. Other embodiments are described and claimed.

Abstract: A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and second memory devices via a command/address bus, and is connected to the first memory device via a data bus separate from the command/address bus and having an upper half and a lower half. However, the CPU is connected to the second memory device via only the upper half of the data bus.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.

Abstract: A buffer management device of record and reproduction apparatus for an optical storage medium and a management method for a buffer memory are provided. By employing two sets of pointers to manage the parts of the buffer memory needed for decoding and encoding respectively, the buffer memory inside the record and reproduction apparatus such as a DVD drive has a better efficiency of switching between the read operation and the write operation.

Abstract: Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

Abstract: A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: Embodiments include methods, apparatus, and systems for data transfer in storage systems. One embodiment includes a method that transmits a state of cached write data and mapping metadata associated with a disk group from a first array to a second array and then transfers access to the disk group from the first array to the second array while host applications continue to access data in the disk group.

Abstract: A method, apparatus and computer program product are provided for implementing feedback directed deferral on nonessential direct access storage device (DASD) operations. A kernel DASD I/O manager maintains a queue depth count value for a DASD unit and maintains a busy flag that indicates when the queue depth count value is greater than a predefined threshold. The kernel DASD I/O manager defers optional operations responsive to the busy flag being set for the DASD unit.

Abstract: A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is read with a first bit length from a first bit field in the first memory unit starting at a first start point. The bit segment that has been read is stored in the first bit field in the second memory unit starting at a second start point. The first or the second start points is updated by a predetermined value and the updated start point is stored for subsequent method steps.

Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: One embodiment of the present invention provides a system that facilitates applying a dynamic lock to a range of a resource within a computer system. Upon receiving a request to lock to the range of the resource from a thread, the system examines an active lock pool to determine if the range of the resource is currently locked. If not, the system retrieves a dynamic lock from a free lock pool. Next, the system sets resource information in the dynamic lock so that the dynamic lock is associated with the resource. The system also sets owner information in the dynamic lock so that the dynamic lock is associated with the thread that is requesting the dynamic lock. Finally, the system adds the dynamic lock to the active lock pool.

Abstract: A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register.

Abstract: Memory management within a runtime execution environment may be configured in accordance with data associated with executable code loaded therein.

Abstract: For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer includes the local caches coupled together, the local caches individually including a first cache layer, and at least one of a data transfer command and data corresponding to the transfer command are multicast to the secondary cache layer through an interconnection bus, the interconnection bus coupling the at least one virtual engine and at least one physical storage device.

Abstract: Various systems and methods for buffer memory management are disclosed. In one embodiment a buffer memory includes at least one queue configured to store a number of buffer access tasks. Buffer reclamation logic is executed to free at least one segment of the buffer memory holding an amount of stale data. Buffer reclamation logic is also included that enables the buffer reclamation logic to submit a buffer access task to the buffer memory based upon a total number of the buffer access tasks stored in the at least one queue.

Abstract: A method for operating a memory device that comprises periodically generating a refresh request signal for performing a refresh operation, providing an access request signal for performing an access operation, performing the refresh operation if the refresh request signal occurs prior to the access request signal, and performing the access operation if the access request signal occurs prior to the refresh request signal.

Abstract: Methods and systems for allowing access to computer storage systems. Multiple requests from multiple applications can be received and processed efficiently to allow traffic from multiple customers to access the storage system concurrently.

Abstract: A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.

Abstract: An apparatus and a method for memory access of sharing the address and the data buses used in multi-media player, comprising at least one SDRAM, storing the large data and as a buffer in high speed; at least one flash memory, storing the programs, the user's defaults and firmware, wherein the address and data pins of the SDRAM and the flash memory are coupled with a same bus respectively, and SDRAM and flash memory are not accessed at the same time; a memory interface, connecting the address bus and data bus shared by the SDRAM and flash memory. The memory interface further comprises an arbiter, deciding which one of the access requests is executed according to the request priority. It is noticed that only one of the SDRAM or the flash memory can be accessed at one time.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Abstract: A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.

Abstract: A method and apparatus for performing an incremental update of a lookup table while the lookup table is available for searching is presented. To add or delete a route, a second set of routes is stored in a second memory space in the lookup table, while access is provided to the first set of routes stored in a first memory space in the lookup table. Access is provided to the first memory space through a first pointer stored in a subtree entry. After storing the second set of routes in the second memory space, access is switched to the first set of routes in the first memory space by replacing the first pointer stored in the subtree entry with a second pointer to the second memory space.