Concurrent Accessing Patents (Class 711/168)
  • Patent number: 7702859
    Abstract: A new and useful DMA-like arrangement provides fast inter-system transfers of large data volumes. A preferred embodiment of the invention includes a data-transfer-out system and further includes a data-transfer-in system. At least one of the systems has a dual ported memory structure configured in a way so that data can move out of a memory module of the structure from one port while other data can independently move into the memory module through the other port. The systems are detachable with respect to each other, and the memory modules of both systems are correspondingly paired with compatible specifications such as module sizes. Furthermore, these memory modules are physically configured in a way so that inter-system data transfer occurs in a parallel (i.e., module to module) manner without the aid of the CPU of the system that has the dual ported memory structure.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 20, 2010
    Inventors: Elwyn Timothy Uy, Mingjie Lin
  • Publication number: 20100088484
    Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 8, 2010
    Inventor: Frankie F. Roohparvar
  • Patent number: 7694099
    Abstract: A memory controller with an interface for providing a connection to a plurality of memory devices at least one of said plurality of memory devices supporting burst mode data transfers comprises data interface circuitry for connecting to a plurality of separate data buses for communicating data signals between said memory controller and a respective one of said memory devices, each of said data buses providing a dedicated data signal path to a different one of said memory devices, address interface circuitry for connecting to a common address bus for communicating address signals to each of said memory devices on a shared address signal path, address signals which are directed to different ones of said memory devices being time division multiplexed together on said common address bus, and device selecting circuitry for generating one or more device selecting signals synchronised with said time division multiplexing of said common address bus to select that memory device to which address signals currently asser
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: April 6, 2010
    Inventor: Daren Croxford
  • Patent number: 7694093
    Abstract: A memory module including first and second ranks is provided. Each rank includes a separate plurality of individually accessible memory locations. Also included in the memory module is a control circuit coupled with the first rank and the second rank. The control circuit is configured to receive a write command for writing data to the first rank, and to process the write command to write the data to both the first rank and the second rank. Another embodiment of the invention features the control circuit alone.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mark Shaw, Christian Petersen
  • Patent number: 7680996
    Abstract: At the beginning of an online backup operation, the backup software system creates a snapshot of source data storage. The snapshot includes a watch-list used for identifying blocks of a source storage which are watched by snapshot management means for update. If a block included into the watch-list was requested for update, the snapshot management means preserve original contents of that block in a retention container for the purpose of temporary store. The retention container includes a set of temporal stores dedicated for transient storing of blocks until they are backed up. Backed up blocks can be operatively excluded from the snapshot so that unchanged blocks are excluded from the watch-list and updated blocks are removed from the retention container.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: March 16, 2010
    Assignee: Paragon Software GmbH
    Inventors: Konstantin Komarov, Oleg Fateev, Maxim Melkov, Vladimir Usatyuk
  • Patent number: 7676640
    Abstract: An electronic data flash card is accessible by a host system, and includes a flash memory controller and at least one flash memory device coupled to the flash controller. The boot code and control code for the flash memory system (flash card) are stored in the flash memory device during a programming procedure. The flash controller transfers the boot code and control code to a volatile main memory (e.g., random access memory or RAM) at start up or reset making a RAM-based memory system. Boot code and control code are selectively overwritten during a code updating operation. A single flash controller thus supports multiple brands and types of flash memory to eliminate stocking issues.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 9, 2010
    Assignee: Super Talent Electronics, Inc.
    Inventors: David Q. Chow, Charles C. Lee, Frank I-Kang Yu, Edward W. Lee, Ming-Shiang Shen
  • Patent number: 7673076
    Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: March 2, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An
  • Patent number: 7673111
    Abstract: In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Shelley Chen, Randy B. Osborne
  • Patent number: 7669014
    Abstract: A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input matrix and outputting the at least one input matrix in transposed form. A data input is provided to receive a plurality data words on each cycle and a data output is provided to output a plurality of data words on each cycle. A read address logic is provided to generate read addresses such that one cell of each dual port memory block can be read out on each cycle. A write address logic is provided to generate write addresses such that one cell k of each dual port memory block can be written on each cycle. In each cycle, one storage cell of each dual port memory block is addressed by the read address logic. The data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: February 23, 2010
    Assignee: Nokia Corporation
    Inventor: Jarno Mikael Tuominen
  • Patent number: 7665003
    Abstract: A method of testing a memory is provided that includes initiating a test on a computer readable memory. The computer readable memory provides output data associated with the test. Further, the method includes selecting to receive the output data from a first register or a second register. In a particular embodiment, the method may include selecting to receive the output data from the first register or the second register by use of a control line. In another particular embodiment, the method may include selecting to receive the RAM input data from the first register or the second register by use of a control line. The control line is configured dynamically by hardware or software on cycle by cycle basis. In a particular embodiment, the test is a built-in-self-test (BIST).
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 16, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Shen, Paul Bassett
  • Publication number: 20100030993
    Abstract: An access control device which increases memory access efficiency to data stored in a memory according to the present invention comprises a plurality of groups of the memory, divides and stores the data in different memory areas of the plurality of groups of the memory distinguished based on the predetermined bits of an access address to the plurality of groups of the memory, and accesses the data stored in the different memory areas of the plurality of groups of the memory simultaneously in the same clock cycle of access to the memory.
    Type: Application
    Filed: July 18, 2007
    Publication date: February 4, 2010
    Inventor: Tetsuro Takizawa
  • Patent number: 7657704
    Abstract: When receiving a verification command for verifying a part of the disk array, each of the disks of the disk array are simultaneously verified such that a part of the disk array practically verified is larger than the part assigned to be verified in the verification command, and verification results are recorded. When receiving the next verification command for verifying another part of the disk array, if the part to be verified is already verified, then the recorded verification result is directly returned in response to the present verification command, thus an efficiency of verifying disk arrays can be raised.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: February 2, 2010
    Assignee: Via Technologies Inc.
    Inventor: Yong Li
  • Patent number: 7644248
    Abstract: According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Ramesh Subashchandrabose, Anupam Mohanty, Rajat Agarwal
  • Patent number: 7640414
    Abstract: Methods, systems, and computer program products for forwarding store data to loads in a pipelined processor are provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: December 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jason Alan Cox, Kevin Chih Kang Lin, Eric Francis Robinson
  • Patent number: 7636828
    Abstract: Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: December 22, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Craig VanZante, King Wayne Luk
  • Patent number: 7634619
    Abstract: A method and apparatus within a processing system is provided for separating access to an instruction memory and a data memory to allow concurrent access by different pipeline stages to both the instruction memory and the data memory. An instruction memory interface is provided to access the instruction memory. A data memory interface is provided to access the data memory. Redirection logic is provided to determine whether an access by the data memory interface should be directed to the instruction memory interface utilizing either the address of the access, or the type of instruction that is executing. If the access is redirected, the access to the instruction memory is performed by the instruction memory interface, and data retrieved by the instruction memory interface is then provided to the data memory interface, and in turn to the pipeline stage that requested the data memory interface to access the data.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: December 15, 2009
    Assignee: MIPS Technologies, Inc.
    Inventors: Gideon D. Intrater, Anders M. Jagd, Ryan C. Kinter
  • Patent number: 7631139
    Abstract: The contents of a RAM disk are copied to an image file in nonvolatile memory on power-down and copied back on reboot to provide an appearance of persistence. A locking method can use in-use tables to limit access to the same blocks of data in a RAM disk.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: December 8, 2009
    Assignee: Superspeed Software
    Inventor: Shawn T. Diehl
  • Publication number: 20090300271
    Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.
    Type: Application
    Filed: August 25, 2008
    Publication date: December 3, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jiunn-Yeong Yang, Chien-Hua Chu, Kuo-Yi Cheng, Li-Chun Liang, Chih-Kang Yeh
  • Patent number: 7613886
    Abstract: Methods and apparatus provide for receiving a request from an initiating device to initiate a data transfer into a local memory for execution of one or more programs therein, the local memory being operatively coupled to a first of a plurality of parallel processors capable of operative communication with a shared memory; facilitating the data transfer into the local memory; and producing a synchronization signal indicating that the data transfer into the local memory has been completed.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: November 3, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Takeshi Yamazaki
  • Patent number: 7613866
    Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: November 3, 2009
    Assignee: Thomson Licensing
    Inventors: Tim Niggemeier, Thomas Brune
  • Patent number: 7610200
    Abstract: A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor coupled to the host, and at least two copies of a parameter block associated with the sound data. The sound processor can access a first copy of the at least two copies while the host is accessing a second copy of the at least two copies. As a result, parameter blocks are freely updated by the host processor and freely read by the sound processor without conflict and without performance loss.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: October 27, 2009
    Assignee: LSI Corporation
    Inventor: David H. Lin
  • Patent number: 7610447
    Abstract: Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets and memory modules. In systems that are not fully populated, the system is configurable to use a plurality of the signal line sets for a single memory module.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: October 27, 2009
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Frederick A. Ware, Ely K. Tsern, Craig E. Hampel
  • Patent number: 7607134
    Abstract: A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating that one of the destinations is available to accept a forward message; simultaneously sending a forward message to each available destination; simultaneously receiving, after a predetermined period of time, a plurality of reverse messages from the destinations, each reverse message corresponding to one of the forward messages simultaneously sent to an available destination; and serially sending the reverse messages to the source.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 20, 2009
    Inventor: Stephen Clark Purcell
  • Patent number: 7603534
    Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 13, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7596669
    Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 29, 2009
    Assignee: Broadcom Corporation
    Inventor: Joseph Herbst
  • Patent number: 7594089
    Abstract: A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one memory location responsive to a memory access instruction relating to the particular one memory location, the interface including: a request storage for storing a plurality of concurrent memory access instructions for one or more of the particular memory locations, each the memory access instruction issued from an associated independent thread context; an arbiter, coupled to the request storage, for selecting a particular one of the memory access instructions to apply to the gating memory; and a controller, coupled to the request storage and to the arbiter, for: storing the plurality of memory access instructions in the request storage; initiating application of the particular one memory access instruction selecte
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: September 22, 2009
    Assignee: MIPS Technologies, Inc.
    Inventors: Sanjay Vishin, Kevin D. Kissell, Darren M. Jones, Ryan C. Kinter
  • Patent number: 7590811
    Abstract: Methods and systems are disclosed that relate to making back-up data available to a host server. An exemplary method includes making primary and secondary data volumes accessible to a first server and presenting the primary data volume and the secondary data volume to the first server as a single virtual data volume. The secondary data volume is a copy of the primary data volume. The method further includes directing a server I/O request to the primary data volume if the primary data volume is accessible or to the secondary data volume if the primary data volume is not accessible and the secondary data volume is not reserved by a second server.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: September 15, 2009
    Assignee: EMC Corporation
    Inventor: Cesareo Contreras
  • Publication number: 20090228615
    Abstract: A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s).
    Type: Application
    Filed: September 5, 2008
    Publication date: September 10, 2009
    Applicant: Microsoft Corporation
    Inventors: Richard D. Beckert, Mark M. Moeller, Hang Li
  • Publication number: 20090228674
    Abstract: To realize a disk array device which suppresses vibrations during HDD spinning-up, there is provided a disk array apparatus, comprising: a plurality of disk drives; and a controller for controlling the plurality of disk drives, the disk array apparatus controlling power of the plurality of disk drives for each disk group including of the plurality of disk drives. The two disk drives included in the same disk group are arranged in sets on one base member. The controller controls to set start timings of the two disk drives constituting the set identical to each other.
    Type: Application
    Filed: April 25, 2008
    Publication date: September 10, 2009
    Inventor: Katsumi OUCHI
  • Patent number: 7577774
    Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: August 18, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An, Hung Ong
  • Patent number: 7577789
    Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: August 18, 2009
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Frederick A. Ware, Ely K. Tsern, Craig E. Hampel
  • Publication number: 20090204780
    Abstract: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware.
    Type: Application
    Filed: April 15, 2009
    Publication date: August 13, 2009
    Inventors: Tetsujiro KONDO, Kenji Takahashi, Hiroshi Sato, Tsutomu Ichikawa, Hiroki Tetsukawa, Masaki Handa
  • Publication number: 20090198847
    Abstract: A serial memory interface is described, including a memory array, a plurality of serial ports in data communication with the memory array, transferring data between the memory array and at least one of the plurality of serial ports, and a logic block that is configured to control access to the memory array by the plurality of serial ports, the logic block using the serial ports to transfer data between the memory array and at least one of the plurality of serial ports.
    Type: Application
    Filed: April 3, 2009
    Publication date: August 6, 2009
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventor: Robert Norman
  • Patent number: 7558933
    Abstract: A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: July 7, 2009
    Assignee: ATI Technologies Inc.
    Inventor: Richard K. Sita
  • Patent number: 7558934
    Abstract: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: July 7, 2009
    Assignee: Sony Corporation
    Inventors: Tetsujiro Kondo, Kenji Takahashi, Hiroshi Sato, Tsutomu Ichikawa, Hiroki Tetsukawa, Masaki Handa
  • Patent number: 7558127
    Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nak-Won Heo, Chang-Sik Yoo
  • Patent number: 7552301
    Abstract: An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control means for giving access to the memory with a high priority, a memory access arranging method includes a step of causing a clock to be supplied to the processor to wait when a contention of access of the processor and the input/output control means to the memory is generated, a step of executing the access of the input/output control means to the memory, and a step of canceling the clock wait of the processor after ending the access of the input/output control means to the memory, and executing the access of the processor to the memory.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventor: Atsuhiro Mori
  • Patent number: 7552247
    Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).
    Type: Grant
    Filed: August 15, 2004
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas B. Berg, Adrian C. Moga, Dale A. Beyer
  • Publication number: 20090157994
    Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 18, 2009
    Inventors: Craig E. Hampel, Frederick A. Ware
  • Patent number: 7549013
    Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: June 16, 2009
    Assignee: Lexar Media, Inc.
    Inventors: Petro Estakhri, Berhanu Iman
  • Patent number: 7546416
    Abstract: A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 7535592
    Abstract: This invention relates to an image processing apparatus capable of processing plural jobs at a high rate. The image processing apparatus is comprised of first and second buffer memory devices, which are independent of each other and configured to be simultaneously accessible; a compression-extension device, which is exclusively connected to each of the buffer memory devices; a control section to assign a buffer memory device to input image data raster by raster (one page of the image data) when executing input processing of the image data, which is input from a scanner or executes output processing of the image data to a printer section, so that the control section regulates and changes the image data flow raster by raster.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: May 19, 2009
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventor: Tetsuya Niitsuma
  • Publication number: 20090125785
    Abstract: The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
    Type: Application
    Filed: January 13, 2009
    Publication date: May 14, 2009
    Inventors: Sergey Anatolievich Gorobets, Kevin M. Conley
  • Patent number: 7533232
    Abstract: In a modified Harvard architecture, conventionally, read operations in the same cycle are only implemented when different memory banks are to be accessed by the different read operation. However, when different sublines in the same memory bank are being accessed, cycles may be saved by accessing both sublines in the same cycle.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Ramesh V. Peri, John S. Fernando, Ravi Kolagotla, Srinivas P. Doddapaneni
  • Patent number: 7529896
    Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. Jeddeloh, Terry R. Lee
  • Patent number: 7529886
    Abstract: A method, system, and storage medium for the InfiniBand™ Poll verb to support a multi-threaded environment without the use of kernel services to provide serialization for mainline Poll logic. Poll is the verb, which allows a consumer to determine which of its work requests have completed, and provides ending status. In addition to multiple concurrent threads using Poll against a single Completion Queue, Poll is serialized with Destroy Queue Pair and Destroy Completion Queue. Completion Queues are used to maintain completion status for work requests. Queue Pairs are used to submit work requests and are related to a Completion Queue at the time they are created.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: David B. Emmes, Donald W. Schmidt
  • Patent number: 7526626
    Abstract: A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: April 28, 2009
    Assignee: Broadcom Corporation
    Inventor: James Daniel Kelly
  • Patent number: 7523255
    Abstract: Embodiments of the present invention provide disk controller operable to facilitate the efficient storage and retrieval of multiple content (data) streams to magnetic disk media. This disk controller includes an interface module, a memory module, and a processing module. The interface module is operable to couple the disk controller to a hard disk drive. The memory module and processing module in combination are operable to execute instructions that detect the geometry associated with the hard disk drive. Then the disk controller is operable to determine when the hard disk drive geometry supports assigning unique RW heads to unique content (data) streams. When the hard disk geometry supports assigning unique RW heads to unique content (data) streams, RW heads may be preferentially reserved or assigned to unique content streams wherein the RW heads are able to write unique content streams to memory locations within the hard disk drive, wherein these memory locations may be contiguous or near contiguous.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: April 21, 2009
    Assignee: Broadcom Corporation
    Inventor: Yasantha Nirmal Rajakarunanayake
  • Patent number: 7523270
    Abstract: A multi-port memory device has a plurality of ports which are connected to different external devices with the memory device performing serial data communication independently. The memory device has a plurality of banks, each of which has a plurality of cell arrays. The memory device also has a write counter for increasing the counting number whenever write data are applied to the banks through the ports and a write data register for temporarily storing the write data according to the count number. A write flag signal generator generates a flag signal for writing the temporarily stored data to the banks. The memory device also has a write enable signal generator for generating a write enable signal is response to the flag signal to write the temporarily stored write data to the banks.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: April 21, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jae-Il Kim
  • Patent number: 7523250
    Abstract: A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 21, 2009
    Assignee: Qimonda AG
    Inventors: Paul Wallner, Andre Schäfer, Peter Gregorius