Abstract: A window-based flash memory storage system and a management and an access method therefor are proposed. The window-based flash memory storage system includes a window-based region and a redundant reserved region; wherein the window-based region is used to store a number of windows, each window being associated with a number of physical blocks. The redundant reserved region includes a dynamic-link area, a window-information area, a dynamic-link information area, and an boot-information area; wherein the dynamic-link area includes a plurality of dynamic allocation blocks, each being allocatable to any window. The window-information area is used to store a specific window-information set that is dedicated to a certain window within a specific range of data storage space. The dynamic-link information area is used to record the status of the allocation of the dynamic allocation blocks to the windows.

Abstract: A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh operations on a periodic basis while avoiding collisions with controller-generated data accesses. An internal refresh cycle can be executed without interfering with any data accesses by starting the refresh after decoding a non-conflicting command in one of these time slots and finishing before the next command time slot. If an internal refresh operation is delayed (e.g., by the decoding of a conflicting access command) it will be completed at the earliest opportunity thereafter.

Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A method for determining a read strobe pulse delay for data read from a memory having a plurality of memory chips. Each one of the chips provides data along with an associated read strobe pulse. The data read from each one of the plurality of chips is stored in a corresponding one of a plurality of storage devices in response to the read strobe pulse associated with such one of the plurality of chips. A training system determines a delay which when applied in to the plurality of read strobe pulses enables valid read data from the plurality of memory chips to be stored in each one of the plurality of the storage device in response to the read strobe pulses being delayed by the read pulse strobe delay. A process is used to enable preservation of the user data during the training process for use subsequent to the training process.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

Abstract: A storage subsystem and a storage controller adapted to take advantage of high data transfer rates of fiber channels while offering enhanced reliability and availability and capable of connecting with a plurality of host computers having multiple different interfaces. A loop is provided to serve as a common loop channel having fiber channel interfaces. Host interface controllers (HIFC) connected to host computers having different interfaces permit conversion between the fiber channel interface and a different interface as needed. Control processors, shared by the host interface controllers, each reference FCAL (fiber channel arbitrated loop) management information to capture a frame having an address of the processor in question from among the frames passing through the loop. I/O processing is then carried out by the controller in accordance with a range of logical unit numbers (LUN) set in the captured frame.

Abstract: A method, system, and program product for controlling multi-node access to a disk storage system. In accordance with the method of the present invention, an active access authorization is set for a first node. The active access authorization enables read and write access by the first node to user and meta data within the disk storage system. A passive access authorization is set for a second node. The passive access authorization enables read-only access by the second node to logical volume management meta data within the disk storage system.

Abstract: An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are interconnected by a dual concentric ring topology. Local controllers on any given node initiate bus operations on behalf of said processors and I/O adapters on that node. Snoop requests are launched onto the ring topology simultaneously in both directions. As the messages traverse the nodes on the ring, they trigger remote controllers to perform coherent actions such as cache accesses or directory updates. Messages arriving on each node from both directions are combined with each other and with locally generated responses to form cumulative final responses. Additionally, controllers on the requesting node may perform local coherent actions based on the information conveyed by the returning final responses.

Abstract: A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

Abstract: The specification discloses a heap memory management system in which software streams remove and replace blocks of heap memory from the heap pile, managed in a linked list fashion, in a last-in/first-out fashion at the top of the list. A hardware device returns blocks of heap memory, and this return is to the end or bottom of the linked list. In this way, software streams may remove and return blocks of heap memory simultaneously with hardware devices returning blocks of heap memory.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: A memory model for a run-time environment is disclosed that includes a process-specific area of memory where objects in call-specific area of memory and session-specific area of memory can be migrated to at the end of a database call. User-specific objects can be then migrated to the session-specific area of memory. In one embodiment, the process-specific area of memory can be saved in a disk file and used to hot start another instance of an application server.

Abstract: A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors. The messaging network operates independently of the data transfer section and such network is coupled to the plurality of first directors and the plurality of second directors. The first and second directors control data transfer between the first directors and the second directors in response to messages passing between the first directors and the second directors through the messaging network to facilitate data transfer between first directors and the second directors. The data passes through the cache memory in the data transfer section. A method for operating a data storage system adapted to transfer data between a host computer/server and a bank of disk drives.

Abstract: A synchronous memory circuit is capable of double data transfer rate per clock cycle, 100% bus utilization (i.e., no idle clock cycles in bus turn arounds), and has only one clock cycle of latency in each of read and write burst operations.

Abstract: A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

Abstract: A striping disk controller and disk drive system for a computer system wherein the computer system includes a CPU connected to a system bus and executes an operating system including a BIOS, the striping disk controller and disk drive system includes, 1) an interface connected to the system bus and communicating with the BIOS, 2) first and second disk drives each having data separator electronics, data formatting electronics and head positioning electronics, and 3) a striping controller connected between the first and second disk drives and the interface, the striping controller adapted to cause data being communicated between the system bus and the first and second drives to be written to and read from the first and second drives in an interleaved form and substantially in parallel.

Abstract: An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals for external tap-off. The number of first control signals corresponds to a number of memory banks. The first control signals are each associated with a memory bank and indicate that an associated memory bank is being accessed. The number of second control signals corresponds to the number of connection panels. One of the second control signals is produced if an access collision occurs between access to one of the memory banks via one connection panel and access to the same memory bank via another connection panel. Two processor units are connected to the connection panels and access the memory independently of one another on the basis of the control signals.

Abstract: Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.

Abstract: In a dual apparatus and a method thereof using a concurrent write function, a PCI bridge of an active board snoops a processor bus. When a processor carries data and a control signal to the processor bus in order to change content of a memory of the active board, the PCI bridge checks whether data synchronization is required. When the data synchronization is required, the PCI bridge buffers the data and the control signal from the processor bus, and transmits them to a standby board through a PCI bus. Accordingly, the content of the memory of the standby board is changed. While the PCI bridge performs the content change of the memory of the standby board, the processor of the active board changes content of the memory of the active board. Accordingly, a performance of the processor can be improved, and accordingly data synchronization can be performed quickly.

Abstract: An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same line detection unit receives a plurality of first instruction fields and a plurality of second instruction fields. The same line detection unit generates a same line signal in response to the first instruction fields and the second instruction fields. The cache storage simultaneously reads data from a single line in the cache storage in response to the same line signal.

Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.

Abstract: The invention is aimed at providing a high-speed processor system capable of performing distributed concurrent processing without requiring modification of conventional programming styles. The processor system in accordance with the invention has a CPU, a plurality of parallel DRAMs, and a plurality of cache memories arranged in a hierarchical configuration. Each of the cache memories is provided with an MPU which is binarily-compatible with the CPU and which has a function to serve as a processor.

Abstract: A host adapter, which interfaces two I/O buses, caches data transferred from one I/O bus to another I/O bus in a data first-in-first-out (FIFO)/caching memory. In addition, when a target device on the another I/O bus is ready to receive the data, data is transferred from the data FIFO/caching memory even though not all of the data may be cached in that memory. Hence, data is concurrently transferred to and transferred from the data FIFO/caching memory. The data transfer to the target device is throttled if cached data is unavailable in the data FIFO/caching memory for transfer, e.g., the data cache is empty for the current context.

Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.

Abstract: A method and apparatus for optimizing access to memory, wherein the method includes the steps of receiving a first request for access to a memory, receiving at least two additional requests for access to the memory, and determining a first clock overhead associated with the first request for access to the memory. The method further includes the steps of determining an additional clock overhead associated with each of the at least two additional requests for access to the memory in conjunction with the first request, determining a combination of requests that can be processed together using an optimized overhead, and processing the combination of requests as a single request with the optimal overhead.

Abstract: The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.

Abstract: Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Abstract: A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one embodiment, the register is located in the memory device and used to determine if a memory access is to be performed. In another embodiment, the register is located external to the memory and used by a processor and/or chip set to determine if an access request is needed.

Abstract: A system and method provides active inheritance on memory writes such that entities issuing later writes ensure that the effects of earlier writes to the same memory block will be seen. A write chain is preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The write chain links the entities requesting write access to the memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in ensuring that all earlier writes are complete before its write is allowed to complete.

Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Abstract: Memory transactions are carried out in an order that maximizes concurrency in a memory system such as a multi-bank interleaved memory system. Read data is collected in a buffer memory to be presented back to the bus in the same order as read transactions were requested. An adaptive algorithm groups writes to minimize overhead associated with transitioning from reading to writing into memory.

Abstract: A memory system includes a memory cache responsive to a single processing unit. The memory cache is arrangeable to include a first independently cached area assigned to store a first number of data packets based on a first processing unit context, and a second independently cached area assigned to store a second number of data packets based on a second processing unit context. A memory control system is coupled to the memory cache, and is configured to arrange the first independently cached area and the second independently cached area in such a manner that the first number of data packets and the second number of data packets coexist in the memory cache and are available for transfer between the memory cache and the single processing unit.

Abstract: In general, in one aspect, the disclosure describes storing identification of one or more memory buckets associated with different, respective, queued write commands, and, based on the stored identification, determining whether at least one bucket associated with a read command is included in one or more buckets associated with at least one queued write command.

Abstract: A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.

Abstract: The present invention provides a method, apparatus and article of manufacture for selecting commands to execute from a command queue in a data storage device. The present invention reduces maximum service times under random queued workloads by executing the oldest command in the queue at a constant and predetermined rate. This yields a minimal yet predictable performance penalty, while significantly reducing maximum service times.

Abstract: In a computer processor, multiple partially translated real addresses for a pipelined operation are compared with the real addresses of one or more other operations in the pipeline to detect an address conflict, without waiting for the address translation mechanism to fully translate the real address. Preferably, if a match is found, it is assumed that an address conflict exists, and the pipeline is stalled one or more cycles to maintain data integrity in the event of an actual address conflict. Preferably, the CPU has caches which are addressed using real addresses, and an N-way translation lookaside buffer (TLB) for determining the high-order portion of a real address. Each of the N real address portions in the TLB is compared with other operations in the pipeline, before determining which is the correct real address portion.

Abstract: A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

Abstract: An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next location to be written in a queue. The system also allows an incoming descriptor to point to a plurality of data frames for transfer to the host processor, wherein the peripheral need not read a new descriptor each time a frame is to be transferred to the host.

Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.

Abstract: When an output of data is switched from a memory to a memory controller, the memory controller takes in write data output from the memory, and outputs the write data taken in to a data bus. Subsequently, the memory controller outputs read data taken thereinto to the data bus, and then outputs write data of its own to the data bus.

Abstract: One embodiment of the present invention provides a memory controller that contains a distributed cache that stores cache lines for pending memory operations. This memory controller includes an input that receives memory operations that are directed to an address in memory. It also includes a central scheduling unit and multiple agents that operate under control of the central scheduling unit. Upon receiving a current address, a given agent compares the current address with a cache line stored within the given agent. All of the agents compare the current address with their respective cache line in parallel. If the addresses match, the agent reports the result to the rest of the agents in the memory controller, and accesses data within the matching cache line stored within the agent to accomplish the memory operation.

Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: An embodiment of the present invention includes a digital equipment system comprising a host for sending commands to read or write files having sectors of information, each sector having and being modifyable on a bit-by-bit, byte-by-byte or word-by-word basis. The host being operative to receive responses to the commands. The digital equipment further including a controller device responsive to the commands and including one-time-programmable nonvolatile memory for storing information organized into sectors, based on commands received from the host, and upon commands from the host to re-write a sector, the controller device for re-writing said sector on a bit-by-bit, byte-by-byte or word-for-word basis.

Abstract: A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache directory updates. When a first queue issues a write access request for a first block of a cache line, the first queue concurrently asserts a last_in_line signal identifying the first queue as the last sequential queue to request access to that cache line. If there is an active write access requests for the cache line, the first queue undertakes a series of operations to enable sequentially correct updates to the cache directory with all previous updates taken into consideration.

Abstract: Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

Abstract: A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

Abstract: A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh operations on a periodic basis while avoiding collisions with controller-generated data accesses. An internal refresh cycle can be executed without interfering with any data accesses by starting the refresh after decoding a non-conflicting command in one of these time slots and finishing before the next command time slot. If an internal refresh operation is delayed (e.g., by the decoding of a conflicting access command) it will be completed at the earliest opportunity thereafter.