Memory Configuring Patents (Class 711/170)
  • Patent number: 11748002
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for executing concurrent writes to a data store. One of the systems includes a data store comprising a plurality of storage segments, wherein each storage segment comprises a plurality of blocks; and an allocator system comprising: a plurality of threads, and a plurality of bitmaps each corresponding to a respective storage segment of the data store, wherein the allocator system is configured to perform operations comprising: assigning a respective bitmap to each thread of the plurality of threads; and executing, by each thread of the plurality of threads, one or more write requests to one or more blocks of the storage segment corresponding to the thread using the bitmap assigned to the thread, wherein executing a write request by a thread includes updating the bitmap assigned to the thread.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: September 5, 2023
    Assignee: VMware, Inc.
    Inventors: Aditya Kotwal, Venkata Ramanan, Sandeep Rangaswamy, Brian Caulfield
  • Patent number: 11748030
    Abstract: An illustrative method includes receiving, by an integrated storage manager from an operating system level virtualization service, a request to perform an operation with respect to one or more storage systems; determining, by the integrated storage manager, multiple versions of a performance impact among the one or more storage systems based on potentially implementing the request in multiple ways; and implementing, by the integrated storage manager based on the determining of the multiple versions of the performance impact, the request in a particular way that improves one or more storage system metrics of the one or more storage systems.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 5, 2023
    Assignee: Pure Storage, Inc.
    Inventor: Patrick East
  • Patent number: 11740800
    Abstract: Disclosed in some examples are methods, systems, and machine-readable mediums that provide a memory allocation mechanism that evenly spreads the allocations for an application over all the MCs on the system, thus minimizing congestion and resulting in optimal application performance.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Estep, Tony M. Brewer
  • Patent number: 11740921
    Abstract: The technology provides for allocating an available resource in a computing system by bidirectional communication between a hypervisor and a container scheduler in the computing system. The computing system for allocating resources includes one or more processors configured to receive a first scheduling request to initiate a first container on a first virtual machine having a set of resources. A first amount of resources is allocated from the set of resources to the first container on the first virtual machine in response to the first scheduling request. A hypervisor is notified in a host of the first amount of resources allocated to the first container. A second amount of resources from the set of resources is allocated to a second virtual machine in the host. A reduced amount of resources available in the set of resources is determined. A container scheduler is notified by the hypervisor for the reduced amount of resources of the set of resources available on the first virtual machine.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 29, 2023
    Assignee: Google LLC
    Inventor: Jeremy Warner Olmsted-Thompson
  • Patent number: 11740792
    Abstract: A data storage system can use non-volatile solid state drives (SSDs) to provide backend storage. The data storage system and SSDs can implement log structured systems (LSSs) experiencing write amplification (WA). The aggregated WA of the LSSs can be minimized when the WAs of both LSSs of the system and SSDs are equal, within a specified tolerance. An amount of storage capacity which the LSS of the data storage system is allowed to use can be limited and vary based on the system's data capacity denoting the storage capacity with valid data. Pm can denote a percentage of Cs, the advertised capacity of the SSDs, storing valid data. Po can be a percentage of Cs denoting the upper bound of the system's used capacity. Po and Pm, as well as the utilization and WA of both the data storage system and SSDs, can be evaluated and adjusted adaptively and holistically.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: August 29, 2023
    Assignee: Dell Products L.P.
    Inventors: Shuyu Lee, Vamsi K. Vankamamidi
  • Patent number: 11743326
    Abstract: A system, method, and machine-readable storage medium for providing a recommendation to a client to modify minimum IOPS settings are provided. In some embodiments, a client may assign a minimum input/output operations per second (IOPS) setting to each volume of a plurality of volumes. The plurality of volumes may reside in a common cluster and include a first number of volumes. A set of volumes of the plurality of volumes may be determined, where each volume of the set of volumes has a relative disparity that satisfies a relative threshold. The set of volumes includes a second number of volumes. A minimum IOPS recommendation may be transmitted to the client to modify (e.g., increase or decrease) the minimum IOPS settings of the set of volumes in response to determining that a ratio of the second number of volumes to the first number of volumes is greater than a performance threshold.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 29, 2023
    Assignee: NETAPP, INC.
    Inventors: Tyler Cady, Austino Nicholas Longo
  • Patent number: 11741056
    Abstract: A method for processing requests includes receiving a request to write data, in response to the request, identifying a sparse virtual space segment using an available space tracking metadata hierarchy, and initiating writing of the data to a physical segment, wherein the physical segment is associated with the sparse virtual space segment.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 29, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Jean-Pierre Bono, Marc A. De Souter
  • Patent number: 11740823
    Abstract: In a multi-node storage system, a node's capacity has an upper limit, and capacities provided by nodes are smaller than a capacity of a global pool. A volume having a capacity larger than the capacity of one node is created by the node. A write error occurs when an amount of data larger than the capacity of the node is written. A storage system reduces the frequency of such a write error. A global pool is based on a plurality of local pools of a plurality of storage nodes that constitute a node group. In any of the storage nodes, a capacity relationship is maintained where a used capacity of a volume created by the storage node is equal to or less than an available capacity of a local pool of the storage node. A storage management unit manages the node group and selects the storage node.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 29, 2023
    Assignee: HITACHI, LTD.
    Inventors: Akira Deguchi, Hirotaka Nakagawa
  • Patent number: 11733865
    Abstract: One or more techniques and/or systems are provided for dynamically provisioning logical storage pools of storage devices for applications. For example, a logical storage pool, of one or more storage devices, may be constructed based upon a service level agreement for an application (e.g., an acceptable latency, an expected throughput, etc.). Real-time performance statistics of the logical storage pool may be collected and evaluated against the service level agreement to determine whether a storage device does not satisfy the service level agreement. For example, a latency of a storage device within the logical storage pool may increase overtime as log files and/or other data of the application increase. Accordingly, a new logical storage pool may be automatically and dynamically defined and provisioned for the application to replace the logical storage pool. The new logical storage pool may comprise storage devices expected to satisfy the storage level agreement.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: August 22, 2023
    Assignee: NetApp, Inc.
    Inventors: Sachithananthan Kesavan, Rajesh Nagarajan, Nandakumar Ravindranath Allu
  • Patent number: 11734200
    Abstract: A method for accessing data in an external memory of a microcontroller, the microcontroller having an internal memory. The method includes: providing a classification data record in the internal memory, the classification data record for data stored in segments in the external memory including a segment-data classification for each segment, the segment-data classification characterizing the data stored in the respective segment; and a read access in which data corresponding to a predetermined data classification are read from the external memory.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 22, 2023
    Assignee: ROBERT BOSCH GMBH
    Inventors: Axel Aue, Martin Assel
  • Patent number: 11734093
    Abstract: In a method for data placement in a storage device including one or more blocks and a controller, the method including: receiving, by the controller of the storage device, a request to write data; determining, by the controller, a data status of the data; calculating, by the controller, one or more vulnerability factors of the one or more blocks; determining, by the controller, one or more block statuses of the one or more blocks based on the one or more vulnerability factors; selecting, by the controller, a target block from the one or more blocks based on the data status and the one or more block statuses; and writing, by the controller, the data to the target block.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nima Elyasi, Changho Choi
  • Patent number: 11734246
    Abstract: Disclosed herein are systems and method for multiplexing data of an underlying index. In an exemplary aspect, an index handler may: search for a data file in a plurality of data buckets associated with an index, wherein at least one respective data bucket of a plurality of data buckets is attached to a respective slot of a plurality of slots; identify, based on the searching, a first data bucket of the plurality of data buckets that comprises the data file; in response to determining that the first data bucket is not attached to any of the plurality of slots, attach the first data bucket to a first slot of the plurality of slots; and enable access to the data file via the first data bucket attached to the first slot.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: August 22, 2023
    Assignee: Acronis International GmbH
    Inventors: Alexander Andreev, Sergey Onuchin, Hiten Gajjar, Dulitha Gunasekera, Dian Bakti, Prabhuraj Reddy, Yee Chen Lim, Serguei Beloussov, Stanislav Protasov
  • Patent number: 11733899
    Abstract: Storage volume placement in a selected of plural storage arrays interfaced with a network is managed by an Ansible module having a placement role that identifies storage resource pools of the network, compares the storage resource pool characteristics against storage volume constraints and lists acceptable storage resource pools in a priority order that allows automated selection of a storage resource pool for storage volume placement. In one embodiment, the network is searched for storage group names associated with the storage volume placement request to check for idempotency.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 22, 2023
    Assignee: Dell Products L.P.
    Inventors: Anil A. Degwekar, Akash Shendge, Arindam Datta
  • Patent number: 11733894
    Abstract: One or more non-transitory computer-readable media can store program instructions that, when executed by one or more processors, cause the one or more processors to perform steps of organizing storage as a set of storage regions, each storage region having a fixed size; and for each storage region, storing a storage allocation structure of the storage region formatted in a first format selected from a format set including at least two formats, determining a change of an allocation feature of the storage region, based on the allocation feature of the storage region, selecting, from the format set, a second format of the storage allocation structure, and reformatting the storage allocation structure in the second format.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 22, 2023
    Assignee: NUTANIX, INC.
    Inventors: Rohit Jain, Harshit Agarwal
  • Patent number: 11734180
    Abstract: A method may use memory efficiently to extend cache. A processor receives a request to write data. The size of the data in the write request is compared to a threshold. When the size of the data exceeds the threshold, the data is stored on a solid state device. Page descriptors for the data on the solid state device are stored in a metadata log, and a reference to a first page descriptor of the page descriptors in the metadata log is stored in a first hash table in memory.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: August 22, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Oran Baruch, Vamsi K. Vankamamidi
  • Patent number: 11728812
    Abstract: Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: August 15, 2023
    Inventor: Dean Gans
  • Patent number: 11720491
    Abstract: A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: August 8, 2023
    Assignee: Next Silicon Ltd
    Inventors: Dan Shechter, Elad Raz
  • Patent number: 11720389
    Abstract: A storage system includes a plurality of storage devices coupled to at least one host through a network and configured to form a virtual network of virtual machines generated when the plurality of storage devices are coupled to the network, wherein each of the plurality of storage devices allocates memory resources to the virtual machines and shares device information for the plurality of storage devices through the virtual machines and wherein the host: selects from the plurality of storage devices a main storage device, and transmits a storage pool generation condition to the main storage device that identifies a number of storage pools and a capacity of each storage pool, wherein the main storage device generates at least one storage pool that satisfies the storage pool generation condition using the memory resources allocated to each of the virtual machines.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 8, 2023
    Assignee: SK hynix Inc.
    Inventor: Tae Jin Oh
  • Patent number: 11722925
    Abstract: Some embodiments provide a method for quantifying quality of several service classes provided by a link between first and second forwarding nodes in a wide area network (WAN). At a first forwarding node, the method computes and stores first and second path quality metric (PQM) values based on packets sent from the second forwarding node for the first and second service classes. The different service classes in some embodiments are associated with different quality of service (QoS) guarantees that the WAN offers to the packets. In some embodiments, the computed PQM value for each service class quantifies the QoS provided to packets processed through the service class. In some embodiments, the first forwarding node adjusts the first and second PQM values as it processes more packets associated with the first and second service classes. The first forwarding node also periodically forwards to the second forwarding node the first and second PQM values that it maintains for the first and second service classes.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: August 8, 2023
    Assignee: VMWARE, INC.
    Inventors: Jegadish Devadoss, Kartik Kamdar, Stephen Craig Connors, Satheesh Kumar Rajendran, Ram Kumar Manoharan
  • Patent number: 11720291
    Abstract: A method includes retrieving, by a workspace client on a computing device, a first set of resource associations from a workspace server. The first set of resource associations identify one or more data file-types executable by each application on a virtualization server. The method also includes generating, by the workspace client, from the first set of resource associations, a second set of resource associations. The second set of resource associations identify a subset of applications on the virtualization server operable to perform operations on each of the one or more data file-types. The method further includes obtaining, by a storage provider client on the computing device, the second set of resource associations. The storage provider client is configured to enable one or more applications on the virtualization server to execute at least one data file accessible from a storage provider.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 8, 2023
    Inventors: Georgy Momchilov, Mukund Ingale
  • Patent number: 11720993
    Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 8, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Gutierrez, Muhammad Amber Hassaan, Sooraj Puthoor
  • Patent number: 11714558
    Abstract: Systems, apparatuses, and methods related to predictive memory management are described. Error correction operations can be performed on a memory system and can include a latency associated with performing various error correction techniques on data and the health of physical addresses used to store the data can be predicted based on that latency information. In an example, a method can include determining, by a controller, latency information corresponding to one or more error correction operations performed on data received by the controller, and assigning, based on the latency information corresponding to a health of physical address locations corresponding to the data, and taking an action involving the physical address locations based, at least in part, on the information corresponding to the health of the plurality of physical address locations corresponding to the data.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: August 1, 2023
    Assignee: Mircon Technology, Inc.
    Inventor: Reshmi Basu
  • Patent number: 11714785
    Abstract: A client identifies a first data unit to be shared from a first file to a second file and sends an operation to copy that indicates the first data unit to be shared. The operation to copy the first data unit from the first file to the second file is received. In response to receiving the operation to copy the first data unit from the first file to the second file, it is determined whether the first data unit can be shared with the second file. In response to determining that the first data unit cannot be shared with the second file, the first data unit is copied to the second file. In response to determining that the first data unit can be shared with the second file, the first data unit is shared between the first file and the second file.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: August 1, 2023
    Assignee: NetApp Inc.
    Inventors: Sisir Shekhar, Akshatha Gangadharaiah, Saravana Selvarai
  • Patent number: 11714783
    Abstract: A request is received to retrieve at least a portion of a file from a compressed data archived image stored in a backup storage device. The compressed data archived image comprises a backup of a file system having a number of directories and a number of files. The compressed data archived image comprises a file that includes a compression of the number of files. An address of the at least the portion of the file within the compressed data archived image is determined. The at least the portion of the file is retrieved at the address in the compressed data archived image, without decompressing the compressed data archived image.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 1, 2023
    Assignee: NetApp, Inc.
    Inventors: Sisir Shekhar, Rakesh Bhargava M R, Krishna Murthy Chandraiah Setty Narasingarayanapeta
  • Patent number: 11714547
    Abstract: A memory sub-system can receive a definition of a performance target for each of a number of applications that use the memory sub-system for storage. The memory sub-system can create a plurality of partitions according to the definitions and assign each of the partitions to a block group. The memory sub-system can operate each block group with a trim tailored to the performance target corresponding to that block group and application.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Minjian Wu
  • Patent number: 11709595
    Abstract: A technique for storage management involves: determining multiple source disk slices from a storage array that provides redundant storage, a current disk group where each of the multiple source disk slices is located being different from a target disk group where the source disk slice is specified to be located; determining multiple destination disk slices from the target disk group based on the multiple source disk slices, the multiple destination disk slices being used to replace the multiple source disk slices; and causing data to be moved to the multiple destination disk slices from the multiple source disk slices. Accordingly, such a technique may improve the reliability of a storage system.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: July 25, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Yuetao Ma, Changrui Shao, Haiying Tang, Xiaobo Zhang, Chun Ma
  • Patent number: 11709603
    Abstract: Techniques are provided for multi-tier write allocation. A storage system may store data within a multi-tier storage environment comprising a first storage tier (e.g., storage devices maintained by the storage system), a second storage tier (e.g., a remote object store provided by a third party storage provider), and/or other storage tiers. A determination is made that data (e.g., data of a write request received by the storage system) is to be stored within the second storage tier. The data is stored into a staging area of the first storage tier. A second storage tier location identifier, for referencing the data according to a format utilized by the second storage tier, is assigned to the data and provided to a file system hosting the data. The data is then destaged from the staging area into the second storage tier, such as within an object stored within the remote object store.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: July 25, 2023
    Assignee: NetApp, Inc.
    Inventors: Ganga Bhavani Kondapalli, Kevin Daniel Varghese, Ananthan Subramanian, Cheryl Marie Thompson, Anil Paul Thoppil
  • Patent number: 11710915
    Abstract: An information handling system includes a first z-axis compression connector, a first dual in-line memory module (DIMM), a second z-axis compression connector, a second DIMM, and a printed circuit board. A first side of the first compression connector is affixed to the printed circuit board. A first surface of a first memory circuit board of the first DIMM is affixed to a second side of the compression connector. A first side of the second compression connector is affixed to a second side of the first memory circuit board. A first side of a second memory circuit board of the second DIMM is affixed to a second side of the second compression connector. The first compression connector has a first depth, and the second compression connector has a second depth that is different from the first depth.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: July 25, 2023
    Assignee: Dell Products L.P.
    Inventors: Arnold Thomas Schnell, Joseph Daniel Mallory
  • Patent number: 11711318
    Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: July 25, 2023
    Assignee: Mellanox Technologies Ltd.
    Inventors: Ioannis (Giannis) Patronas, Michael Gandelman, Liron Mula, Aviad Levy, Lion Levi, Jose Yallouz, Paraskevas Bakopoulos, Elad Mentovich
  • Patent number: 11709599
    Abstract: A memory controller connectable to a semiconductor memory including a plurality of memory areas, includes a counter circuit configured to count a degree of wear of each of the memory areas in response to a memory operation addressed thereto, and a control circuit configured to set a rate of for wear leveling to be performed on the plurality of memory areas based on a total number of memory operations performed thereon, and select whether to perform wear leveling on each of the memory areas based on the rate, the degree of wear counted for the memory area, a first threshold for the degree of wear, and a second threshold for the degree of wear. The second threshold is greater than the first threshold.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Shohei Onishi, Kenta Yasufuku
  • Patent number: 11709739
    Abstract: Described in detail herein are systems and methods for single instancing blocks of data in a data storage system. For example, the data storage system may include multiple computing devices (e.g., client computing devices) that store primary data. The data storage system may also include a secondary storage computing device, a single instance database, and one or more storage devices that store copies of the primary data (e.g., secondary copies, tertiary copies, etc.). The secondary storage computing device receives blocks of data from the computing devices and accesses the single instance database to determine whether the blocks of data are unique (meaning that no instances of the blocks of data are stored on the storage devices). If a block of data is unique, the single instance database stores it on a storage device. If not, the secondary storage computing device can avoid storing the block of data on the storage devices.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 25, 2023
    Assignee: Commvault Systems, Inc.
    Inventors: Deepak Raghunath Attarde, Rajiv Kottomtharayil, Manoj Kumar Vijayan
  • Patent number: 11704242
    Abstract: A time period is received from a user over which memory settings of a microservice are to be dynamically managed. Memory settings for the microservice are stored in a configuration file. During the time period, memory utilization of a set of memory regions provided by a process virtual machine for execution of the microservice is monitored. The memory utilization of each memory region is analyzed to identify memory regions that have been over-utilized and memory regions that have been under-utilized. For each memory region identified as being over-utilized or under-utilized, a memory setting in the configuration file and corresponding to an identified memory region is changed. After the change and once the microservice has entered an idle state, a command is generated to restart the microservice so that the changed memory settings can take effect.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: July 18, 2023
    Assignee: Dell Products L.P.
    Inventors: Min Liu, Gururaj Kulkarni
  • Patent number: 11704240
    Abstract: A garbage data scrubbing method includes obtaining an input/output (IO) busy/idle status of a terminal at a current moment, where the IO busy/idle status includes a busy state and an idle state. When the IO busy/idle status of the terminal at the current moment is the idle state, a discard message is delivered to a storage device, where the discard message includes an initial address and a size of to-be-scrubbed physical space in the storage device, and where the discard message is used to unbind a mapping relationship between a physical address of the to-be-scrubbed physical space and a corresponding logical address.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: July 18, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Yu, Hao Chen, Bifeng Tong, Chengliang Zheng, Xiyu Zhou
  • Patent number: 11705191
    Abstract: Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 18, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rami Rom, Ofir Pele, Alexander Bazarsky, Tomer Tzvi Eliash, Ran Zamir, Karin Inbar
  • Patent number: 11704158
    Abstract: Methods, systems, and computer storage media storing instructions for managing processing system efficiency. One of the methods includes obtaining data splitting a plurality of general-purpose processing units in a processing system into a high-priority domain and a low-priority domain, wherein the general-purpose processing units in the high-priority domain are assigned to perform one or more tasks comprising one or more high-priority tasks, and the general-purpose processing units in the low-priority domain are assigned to perform one or more low-priority tasks; and during runtime of the processing system, obtaining memory usage measurements that characterize usage of system memory by the high-priority domain and the low-priority domain; and adjusting, based on the memory usage measurements, a configuration of (i) the high-priority domain, (ii) the low-priority domain, or (iii) both to adjust utilization of the system memory by the general-purpose processing units.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: July 18, 2023
    Assignee: Google LLC
    Inventors: Liqun Cheng, Rama Krishna Govindaraju, Haishan Zhu, David Lo, Parthasarathy Ranganathan, Nishant Patil
  • Patent number: 11704048
    Abstract: An electronic device includes a controller; and a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to execute processes. The non-transitory computer-readable storage medium includes a plurality of memory blocks. The processes include grouping the plurality of memory blocks into a plurality of super blocks; selecting a first super block among the plurality of super blocks depending on one or more logical addresses corresponding to write-requested data, and writing the data; and mapping the first super block to a first logical address range. The first logical address range is configured by successive addresses corresponding to a super block size, and a start address of the successive addresses is a start logical address of the one or more logical addresses.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Seok Hoon Jung, In Woong Heo
  • Patent number: 11704029
    Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Patent number: 11698744
    Abstract: Aspects of the present disclosure relate to data deduplication (dedup) techniques for storage arrays. At least one input/output (IO) operations in an IO workload received by a storage array can be identified. Each of the IOs can relate to a data track of the storage array. a probability of the at least one IO being similar to a previous stored IO can be determined. A data deduplication (dedup) operation can be performed on the at least one IO based on the probability. The probability can be less than one hundred percent (100%).
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 11, 2023
    Assignee: EMC IP Holding Company LLC
    Inventor: Ramesh Doddaiah
  • Patent number: 11698746
    Abstract: An operation performed on a non-volatile memory device is detected. A type of the operation is determined. The type of the operation comprises a type identifier and a type modifier. A journal entry is generated reflecting the operation. The journal entry comprises a body reflecting the operation and a header comprising the type identifier and the type modifier. A combination of the type identifier and the type modifier define a size of the journal entry. The journal entry is written to a volatile memory device.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tom V Geukens, Daniel A Boals
  • Patent number: 11698871
    Abstract: Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: July 11, 2023
    Assignee: PETAIO INC.
    Inventors: Yimin Chen, Fan Yang
  • Patent number: 11698742
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jianmin Huang, Aparna U. Limaye, Avani F. Trivedi, Tomoko Ogura Iwasaki, Tracy D. Evans
  • Patent number: 11693463
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 4, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 11695785
    Abstract: The technology disclosed relates to streamlined analysis of security posture of a cloud environment. In particular, the disclosed technology relates to a system that analyzes data posture in a cloud environment database using a snapshot of the database. A computer-implemented method includes receiving a request to access a database in the cloud environment, wherein the database includes a first authentication requirement. The method includes identifying a snapshot of the database, wherein the snapshot includes a second authentication requirement that is different than the first authentication requirement. The method includes accessing the snapshot using the second authentication requirement, generating a representation of the database using the snapshot, and generating a data posture analysis result indicative of a data posture of the database based on scanning the representation of the database.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: July 4, 2023
    Assignee: Normalyze, Inc.
    Inventors: Ravishankar Ganesh Ithal, Yang Zhang
  • Patent number: 11693768
    Abstract: A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Peng Xu, Jiangang Wu, Yun Li
  • Patent number: 11687265
    Abstract: Techniques are provided for incremental snapshot copy to an object store. A list of deallocated block numbers of primary storage of a computing device are identified. Entries for the list of deallocated block numbers are removed from a mapping metafile. A list of changed block numbers corresponding to changes between a current snapshot of the primary storage and a prior copied snapshot copied from the primary storage to the object store is determined. The mapping metafile is evaluated using the list of changed block numbers to identify a deduplicated set of changed block numbers without entries within the mapping metafile. An object, comprising data of the deduplicated set of changed block numbers, is transmitted to the object store for storage as a new copied snapshot.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 27, 2023
    Assignee: NetApp, Inc.
    Inventors: Tijin George, Jagavar Nehra, Roopesh Chuggani, Dnyaneshwar Nagorao Pawar
  • Patent number: 11687449
    Abstract: A computer-implemented method is provided for reducing Compare And Swap (CAS) operations in a concurrent marking Garbage Collection (GC) process that operates on objects corresponding to a bit map of multiple blocks. The method includes finding, from among the objects, live objects that belong to a same block in the bit map from among the multiple blocks when traversing object trees of the objects for GC marking. The method further includes loading a latest value of the same block from the bitmap, updating the latest value by setting corresponding marking bits in the bit map, and updating the same block in the bit map with a single CAS operation.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 27, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michihiro Horie, Kazunori Ogata
  • Patent number: 11687488
    Abstract: A directory deletion method and apparatus, and a storage server, where the directory deletion method includes receiving, by a storage server, a delete operation authentication request of a host, where the delete operation authentication request carries user information and information about a target directory, storing, by the storage server, the user information and returning a file identifier (FID) of the target directory to the host after authentication succeeds, sending, by the host to the storage server, a delete request carrying the FID, performing, by the storage server, verification on the file and the subdirectory using the user information, and deleting a successfully verified empty subdirectory and a successfully verified file. Hence, the directory deletion method and the apparatus, and the storage server improve directory deletion efficiency.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 27, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yin Long, Shengqian Jia
  • Patent number: 11687563
    Abstract: A system and method of scaling capacity of data warehouses to user-defined levels. The method includes provisioning a data warehouse including a plurality of processing resources, the plurality of processing resources including at least one processor and at least one storage device. The method includes receiving a request to process database data stored on a storage platform including a plurality of shared storage devices in association with the data warehouse, wherein the request indicates a performance level for processing the request. The method includes determining that a capacity of the plurality of processing resources of the data warehouse would reach a threshold capacity when processing the request according to the performance level. The method includes increasing the capacity of the data warehouse for the data warehouse to process the request according to the performance level.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: June 27, 2023
    Assignee: Snowflake Inc.
    Inventors: Benoit Dageville, Thierry Cruanes, Marcin Zukowski
  • Patent number: 11681613
    Abstract: Various examples are directed to systems and methods for managing a memory device. Processing logic may identify a set of retired blocks at the memory device that were retired during use of the memory device. The processing logic may modify a first table entry referencing the first block to indicate that the first block is not retired. The processing logic may also modify a second table entry referencing the second block to indicate that the second block is not retired. The processing logic may also recreate a logical-to-physical table entry for a first page of at the first block, the logical-to-physical table entry associating a logical address with the first page.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: June 20, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R Brandt
  • Patent number: 11675709
    Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Carminantonio Manganelli, Paolo Papa, Yoav Weinberg, Giuseppe Ferrari, Massimo Iaculo, Lalla Fatima Drissi