Abstract: The described technologies enable a computing device to allocate at least a portion of its persistent memory as volatile memory during runtime. At least some implementations create a file in the persistent memory of the computing device. The file is created in the persistent memory of the computing device during runtime of a virtual machine (VM) hosted by the computing device. The file may be allocated to the VM. The file allocated to the VM may be used as volatile memory. For example, the VM may use the file to store temporary data (e.g., volatile data). In some implementations, the temporary data is associated with an application executing in the VM.

Abstract: Systems and methods of cache flushing include receiving, from a software application, a first cache flush request to perform a range-based cache flush of a contiguous virtual address range within a virtual memory that maps to a physical memory. A single cache walk is triggered via a second cache flush request to a cache. The single cache walk performs the range-based cache flush for the contiguous physical address range from a beginning address of the contiguous physical address range to an ending address of the contiguous physical address range in response to the first cache flush request.

Abstract: There is provided an apparatus, medium and method for cache invalidation. The apparatus comprises a cache having a plurality of entries grouped into a plurality of entry sets. Each entry of the plurality of entries identifies an address range having one of a plurality of predetermined address range sizes. The apparatus further comprises cache invalidation circuitry responsive to a cache invalidation request indicating an address invalidation range to trigger invalidation of entries in the cache that overlap the address invalidation range. The cache invalidation circuitry is configured to operate in one of a plurality of invalidation modes based on the address invalidation range and cache occupancy information indicating address range sizes identified by the plurality of entries in the cache.

Abstract: A storage system (100) stores metadata using an append log to provide speed and reliability. Appending entities to the end of a metadata store (154) and provides reliability in the event of failure because a failed append operation at worst corrupts the end of the append log, which is easily detected and corrected. A metadata store (154) can be split into sections (158). A used section (158) may be identified as garbage when the stored metadata in other sections (158) make the all of its stored entity sets stale. A used section (158) can be made garbage by storing the entity sets from the section (158) in another section (158). Sections (158) containing garbage thereby change to unused allow replacement and removal of previous sections (158) of metadata.

Abstract: A data association system includes a POST connector which collects data maintained in an information system a pipeline which stores the data collected by the POST connector; and a pipeline orchestrator which controls anonymization of the data stored by the pipeline. the data association system is characterized in that the pipeline executes anonymization processing of anonymizing the data, the POST connector and the pipeline store data before being anonymized by the anonymization processing, and the pipeline orchestrator instructs, after execution of the anonymization processing, the POST connector and the pipeline to delete the data before being anonymized.

Abstract: The described technologies enable a computing device to allocate at least a portion of its persistent memory as volatile memory during runtime. At least some implementations create a file in the persistent memory of the computing device. The file is created in the persistent memory of the computing device during runtime of a virtual machine (VM) hosted by the computing device. The file may be allocated to the VM. The file allocated to the VM may be used as volatile memory. For example, the VM may use the file to store temporary data (e.g., volatile data). In some implementations, the temporary data is associated with an application executing in the VM.

Abstract: This application provides a data reading method for a retrieval task and a retrieval apparatus. The method includes receiving a first retrieval task request, where the first retrieval task request corresponds to a first retrieval start address and a first retrieval end address in a target data area, and reading data for a first retrieval task starting from the first retrieval start address. The method includes receiving a second retrieval task request in a process of reading data for the first retrieval task. The method further includes obtaining an address of data to be read for the first retrieval task after receiving the second retrieval task request, and determining a second retrieval start address of a second retrieval task in the target data area based on the address of the data to be read. The method further includes reading data for the second retrieval task starting from the second retrieval start address.

Abstract: The invention relates to a method for operating a memory assembly. A physical address is received. The physical address is associated with a first memory segment of a memory assembly. The physical address is modified to a modified physical address. The modified physical address is associated with a second memory segment of the memory assembly.

Abstract: A semiconductor device includes a plurality of cores, each including an instruction execution circuit and a first cache, and a second cache shared by the plurality of cores. In each of the cores, a number of completed instructions for each type of the instructions executed by the instruction execution circuit are counted, and an execution frequency for each type of instructions are calculated. Based on the execution frequencies, a cache line size preferable for use in the first cache in the core is selected. Based on the selected preferable cache line sizes for the cores, a cache line size used in the first caches and the second cache is determined.

Abstract: A vehicle includes electronic control units (ECUs) to control devices and functions of the vehicle, domain control units (DCUs) to group the ECUs by domain and manage the groups of the ECUs by domain, and a connectivity control unit (CCU) to communicate with the DCUs and an external device. Each of the ECUs includes a memory to store data and software and a processor to generate a control signal to control a device or a function based on the data and software. The DCU determines whether an ECU is available to store new data based on at least one of a remaining capacity and an available level of a memory of the ECU, and when the ECU is unavailable to store the new data, the DCU selects other memory of the ECUs managed by other DCU as an alternative memory, and store the new data in the alternative memory.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving, at a storage drive, a portion of a write command. Metadata information is extracted from the received portion of the write command, and sequentially added to a metadata buffer. Parity information is extracted from the received portion of the write command, and adding to a parity buffer. The data in the received portion of the write command is stored in a memory in the storage drive. A determination is also made as to whether an open segment in the memory which corresponds to the received portion of the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. The metadata information and parity information is also destaged from the respective buffers to a physical storage location in the memory.

Abstract: A computer-implemented method, according to one embodiment, includes: sequentially adding metadata information that has been extracted from a received write command to a metadata buffer, and adding parity information that has been extracted from the received write command to a parity buffer. The data corresponding to the received write command is also sent to memory. A determination is made as to whether an open segment in the memory which corresponds to the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. Moreover, the metadata information is destaged from the metadata buffer and parity information is destaged from the parity buffer to a physical storage location in the memory.

Abstract: Methods and apparatuses to fragment data in a flash memory device are presented. The apparatus includes a host configured to request a flash memory device, via a memory bus, to fragment data stored in the flash memory device in response to a determination of a data fragmentation status of the flash memory device exceeding a threshold. The method includes determining a data fragmentation status of the flash memory device exceeding a threshold and requesting, by a host, the flash memory device to fragment data stored in the flash memory device in response to the determining the data fragmentation status exceeding the threshold.

Abstract: Examples relate to a controller apparatus or controller device for a solid-stage storage device, to an apparatus or device for a host computer, to corresponding methods and computer programs, to a solid-stage storage device and to a host computer comprising a solid-state storage device. Examples provide a controller apparatus for a solid-state storage device. The solid-state storage device comprises non-volatile buffer memory circuitry and storage circuitry. The controller apparatus comprises interface circuitry for communicating with a host computer. The controller apparatus comprises processing circuitry configured to obtain a control instruction related to a file system of a partition from the host computer. The partition is at least partially stored within the storage circuitry of the solid-state storage device. The control instruction indicates a location of file system metadata within the partition.

Abstract: In one embodiment, a computer-implemented method for configuring virtualization of a storage system includes: creating a storage pool for each array designated by an administrator for virtualization; creating one or more volumes for each storage pool; creating or selecting a volume controller designated by the administrator for hosting virtualization; identifying one or more ports of the volume controller; and mapping the one or more volumes to the one or more ports of the volume controller. Corresponding systems and computer program products are also disclosed.

Abstract: The present disclosure discloses a method and apparatus for constructing a three-dimensional map. A specific embodiment of the method includes: acquiring multiple frames of a monocular image containing a target object collected by a monocular camera, and constructing a three-dimensional map containing the target object and other objects in the monocular image based on the monocular image; determining an absolute scale of the target object, and determining a ratio of a relative scale corresponding to the target object to the absolute scale; and adjusting a scale of each object in the three-dimensional map to obtain a three-dimensional map meeting a preset condition based on the ratio. The method and apparatus provided by the present disclosure achieves the construction of a world coordinate system with absolute scales in a three-dimensional map constructed based on a monocular image.

Abstract: According to at least some example embodiments of the inventive concepts, an electronic device includes an embedded storage device that is, configured to connect to a removable storage device, and configured to directly communicate with the removable storage device, when connected to the removable storage device; and an application processor connected to directly communicate with the embedded storage device and not directly connected with the removable storage device, wherein, the embedded storage device is configured to, in response to a disable command received from the application processor, decrease an amount of power supplied to all or some of circuits included in the embedded storage device, and provide a bypass path that is configured to transfer a normal command and data from the application processor to the removable storage device, when the removable storage device is connected to the bypass path.

Abstract: A computer-implemented method according to one embodiment includes receiving a request to initialize a storage device, the request including a volume serial number associated with the storage device, identifying a size of the storage device, where the size is indicated within the request, determining a size of a table of contents and a location for the table of contents within the storage device, based on the identified size of the storage device, selecting a type of the table of contents from a plurality of different types, based on the identified size of the storage device, and automatically initializing the storage device, including creating the table of contents, reserving a physical area of the storage device for the table of contents using a physical extent, and inserting the table of contents into the storage device, where the table of contents has the determined size of the table of contents, the determined location for the table of contents, and the selected type of the table of contents.

Abstract: Processing within a non-uniform memory access (NUMA) computing environment is facilitated by obtaining memory for a memory heap for an application of a virtualized environment of the NUMA computing environment, and assigning portions of memory of the obtained memory to locality domain-based freelists. The assigning including obtaining, for a selected portion of memory of the portions of memory, a locality domain within the NUMA computing environment with which the portion of memory is associated, and adding the selected portion of memory to a corresponding locality domain-based freelist of the locality domain-based freelists based on the associated locality domain of the portion of memory. Domain locality is then used in allocating the memory from the locality domain-based freelists to processors of the NUMA computing environment performing processing of the application.

Abstract: A memory system may include: a memory system may include: a memory device suitable for storing user data and corresponding metadata; and a controller including a memory, the controller being suitable for storing user data and corresponding metadata in the memory and for controlling the memory device for storing therein the user data and the metadata of the memory when sizes of the user data and metadata of the memory reach first and second thresholds, respectively.

Abstract: An indicia-reading system is provided that incorporates a hybrid approach to decoding indicia such as barcodes. An indicia-capturing subsystem acquires information about indicia within the indicia-capturing subsystem's field of view. An indicia-decoding module decodes indicia information acquired by the indicia-capturing subsystem. The indicia-decoding module includes a primary, basic signal processor for initially decoding indicia information, and a secondary, advanced signal processor for decoding indicia information that is not decoded by the primary, basic signal processor.

Abstract: A persistence management system performs, at a server, operations associated with a number of applications. At the server, a persistence manager can intercept a file system call from one of the applications, wherein the file system call specifies a file located on a remote persistent storage device separate from the server. The persistence manager can determine that data belonging to the file requested by the file system call is stored on a local persistent storage device at the server, retrieve the data from the local persistent storage, and respond to the file system call from the application with the data.

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

Abstract: A method of storing computer executable instructions and data elements of a program in a plurality of memory blocks of an embedded system. The method includes receiving object code that comprises instructions that symbolically refer to one or more data elements; metadata that identifies the data elements in the object code; and a data element description that identifies each of the data elements as either a regular data element or a non-regular data element. Executable code is generated based the object code, metadata and the data element description that comprises computer executable instructions that refer to the data elements using an address in the memory, wherein the regular data elements are referenced by an address in a non-instruction memory block of the plurality of memory blocks and the non-regular data elements are referenced by an address in an instruction memory block. The executable code is then loaded into the memory of the embedded system.

Abstract: In a computer-implemented method for linking selectable parameters within a graphical user interface a first selectable parameter and a second selectable parameter are displayed within the graphical user interface, wherein the first selectable parameter is selectable within a first range and the second selectable parameter is selectable within a second range. A selection of the first selectable parameter within the first range is received. Responsive to receiving the selection of the first selectable parameter, an available range of the second range is provided, wherein the available range is a subset of the second range such that a selection of the second selectable parameter is bounded by the available range.

Abstract: Aspects of the present disclosure involve a system and method for verifying and validating accurate memory module placement on a printed circuit board. In one embodiment, the printed circuit board is configured to include actuating elements that can be used to verify correct memory module location placement on the printed circuit board. In another embodiment, the actuating elements can be used to validate accurate memory module placement. The actuating elements can be in the form of buttons that may be depressed and configured to trigger light emitting diodes (LEDs) that correspond to the slots on the printed circuit board.

Abstract: A method translates the native machine codes that do not allocate memory for metadata, do not store, and do not propagate metadata by augmenting them with extra instructions to allocate memory for metadata, to store, and to populate metadata such that metadata are readily available at run time for checking programming errors.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: A disk drive includes a controller and at least one disk, which may include a first I-region, a second I-region, and an E-region. The first and second I-region may have a first final logical block address (LBA) and a second final LBA, respectively. The controller may be configured to cause information to be written to the first I-region and the second I-region using a first type and a second type of magnetic recording, respectively. The controller also may be configured to set at least one of the first final LBA or the second final LBA to a final LBA value higher than the at least one of the first final LBA or the second final LBA, respectively, after writing user data to at least a portion of the first I-region or the second I-region and without removing the user data.

Abstract: In one aspect, a method to synchronize volumes includes comparing a first root hash of a root hash node in a first hash tree of a first volume with a second root hash of a second root hash node in a second hash tree of a second volume, for each child node of the first root hash node, comparing a hash of the child node with a hash of a corresponding node in the second hash tree if the first root hash and the second hash are not the same, for each hash in the first hash tree that does not match the corresponding hash in the second hash tree, determining if its node is a leaf node and copying the corresponding data block of the first volume to the corresponding data block of the second volume if a node is determined to be a leaf node.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

Abstract: Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.

Abstract: Detecting the operation of a virtual machine by identifying seed candidates from sets of random numbers generated at a computer, where each of the sets includes multiple random numbers, identifying candidate performance counter frequencies from the seed candidates and from timing information associated with the sets of random numbers, and determining that the computer is operating as a virtual machine if any of the candidate performance counter frequencies is consistent with a predefined virtual machine performance counter frequency.

Abstract: A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

Abstract: A method for partitioning a molecular subset is described. The partitioning method takes into account molecular structure and its manner of storage and transmission, transformations to be applied to the molecular subset and their implementation, and constraints imposed by the implementation of the partitioning method. Using this method, a molecular subset can be stored, transmitted, and processed more efficiently. The resulting efficiency makes it possible to design and run applications which require complex molecular processing, such as rational drug discovery, virtual library design, etc.

Abstract: A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Abstract: Described is a printed-circuit board (PCB) that supports memory systems in which the memory core organization changes with device width. The PCB includes a memory-controller mounting location and module connectors to receive respective memory modules. Each module connector connects directly to the controller mounting location via a respective set of system data lines that does not connect to any other module connector. System data lines also extend directly between module connectors to support memory configurations with different numbers of modules. The memory systems support one memory module of a wide data width or multiple memory modules of narrower data widths. The number of physical memory banks accessed reduces with device data width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.

Abstract: Various embodiments of a system and method for archiving data items to one or more archival storage devices are described. According to some embodiments of the method, an archival software application may implement a plurality of producer agents, where each of the producer agents is executable to produce items of a different type. The archival software application may also implement a plurality of archiving agents for archiving the items produced by the producer agents to one or more archival storage devices. In some embodiments each of the archiving agents may be executable to archive any item of any type produced by the producer agents. The archival software application may also implement a plurality of indexing agents executable to create a searchable index of the items archived to the one or more storage devices.

Abstract: The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.

Abstract: Generally described, the present application corresponds to the management of journaling messages in a messaging environment. A set of electronic messaging clients can be associated with a designated journaling destination that may be different from a default journaling destination associated with each individual messaging client. Additionally, the messaging environment can alternate between multiple designated journaling destinations to increase the mail load that a single journal destination can manage. The messaging environment can evaluate journaling criteria to select alternate designated journaling destinations from a set of available alternate journaling destinations.

Abstract: Systems and methods of a memory allocation buffer to reduce heap fragmentation. In one embodiment, the memory allocation buffer structures a memory arena dedicated to a target region that is one of a plurality of regions in a server in a database cluster such as an HBase cluster. The memory area has a chunk size (e.g., 2 MB) and an offset pointer. Data objects in write requests targeted to the region are received and inserted to the memory arena at a location specified by the offset pointer. When the memory arena is filled, a new one is allocated. When a MemStore of the target region is flushed, the entire memory arenas for the target region are freed up. This reduces heap fragmentation that is responsible for long and/or frequent garbage collection pauses.

Abstract: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.

Abstract: A distributed virtual appliance is disclosed, including: allocating network traffic to a plurality of compute units implementing a network service associated with the distributed virtual appliance; and dynamically adding or removing one or more compute units implementing the network service without disruption to the network traffic.

Abstract: Certain example embodiments relate to a method of storing data in a tabular data structure having columns and rows in a column-oriented storage system. At least one of the columns is divided into a plurality of segments. Each segment has an associated cell size that indicates the maximum size of the data items in the respective segment. When storing a data item into one of the segments, it is determined whether the size of the data item exceeds the cell size of the segment; and if the size of the data item exceeds the cell size of the segment, the cell size of the segment is adapted to accommodate the size of the data item. The adapting of the cell size of the segment to accommodate the size of the data item is performed independent of the cell sizes of the other of the plurality of segments.

Abstract: Various systems and methods are described for configuring a logical data storage container. In one embodiment, an instruction to perform an operation to modify an attribute of the logical data storage container that is an abstraction of a plurality of pertinent storage containers is received. A translated instruction to perform a sub-operation associated with the operation is transmitted to each of a number of the plurality of pertinent storage containers. A level of success of the performing of the operation on the logical data storage container is detected based on a comparison of a threshold value to a level of success of the performing of the sub-operation on each of the number of the plurality of pertinent storage containers. A report of the detected level of success is communicated.

Abstract: An execution environment for functional code may treat application segments as individual programs for memory management. A larger program of application may be segmented into functional blocks that receive an input and return a value, but operate without changing state of other memory objects. The program segments may have memory pages allocated to the segments by the operating system as other full programs, and may deallocate memory pages when the segments finish operating. Functional programming languages and imperative programming languages may define program segments explicitly or implicitly, and the program segments may be identified at compile time or runtime.

Abstract: Releasing a data set at a source device in connection with migrating data from the source device to a target device includes mapping application address space to address space containing metadata for the target device and providing additional local metadata therefor, replacing within the application the address of metadata for the source device with the address of metadata for the target device, setting a diversion flag that is part of the additional local metadata, where the diversion flag indicates a remapping of extent, and closing and unallocating the data set at the source device. Releasing a data set at a source device in connection with migrating data from the source device to a target device may also include determining if an application uses standard I/O operations. The metadata may include UCB data.

Abstract: A write operation writes first data to a target logical address range included in a first logical address range of a virtually provisioned device. It is determined that physical storage is not allocated for the target logical address range. First processing is performed to allocate a first portion of physical storage having a first corresponding logical address subrange that includes the target logical address range. The first portion is allocated from a physical device included in a first storage tier. The first processing includes selecting the first storage tier from multiple storage tiers in accordance with selection criteria including metrics characterizing an expected workload or level of activity for the first corresponding logical address subrange of the virtually provisioned device. Mapping information is updated to indicate that the first corresponding logical address subrange of the virtually provisioned device maps to the first portion of physical storage.