Based On Component Size Patents (Class 711/172)
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Patent number: 7831762Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.Type: GrantFiled: November 29, 2006Date of Patent: November 9, 2010Assignee: Intel CorporationInventor: Cheng Zheng
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Patent number: 7818534Abstract: A portion of data records of a full input data set are imported into memory of a computer system for processing by an executing application. The full input data set includes data records of a dimensionally-modeled fact collection. An amount of the data of the full input set to import is determined based on an amount of available memory of the computer system. The sampling characteristics for sampling the full input data set are determined based on the amount of the data that can be imported and on characteristics of the full input data set and application involved. The full input data set is then sampled and a portion of the records are imported into the memory of the computer system for processing. The sampling characteristics are determined such that analysis as a result of processing by the executing application of the sampled portion of the records imported is representative of the analysis that could otherwise be carried out on the full input data set, with a calculable statistical relevance.Type: GrantFiled: May 9, 2007Date of Patent: October 19, 2010Assignee: Yahoo! Inc.Inventors: David A. Burgess, Amit Umesh Shanbhag, Brian T. Selle, Glen Anthony Ames, Sundara Raman Rajagopalan
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Patent number: 7818524Abstract: A method of data migration for independent storage device expansion and adaptation is disclosed. The method migrates user data of a first storage unit being pre-expanded or pre-adapted to relevant regions of a second storage unit being post-expanded or post-adapted in multiple batches and includes the following steps. A number corresponding to a start data stripe of the first storage unit is provided in each batch. A data stripe migration quantity is determined. Data stripe user data of the determined data stripe migration quantity subsequent to and including the start data stripe of the first storage unit is duplicated and stored in relevant regions of the second storage unit. Subsequent to duplicating and storing each batch, the original user data of data stripes of the determined data stripe migration quantity subsequent to and including the start data stripe of the first storage unit remains undamaged.Type: GrantFiled: June 11, 2007Date of Patent: October 19, 2010Assignee: Via Technologies, Inc.Inventor: Ling Chi
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Patent number: 7818488Abstract: Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.Type: GrantFiled: October 27, 2004Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang-Soo Park, Jeong-Hyeon Cho, Byung-Se So, Jung-Joon Lee, Young Yun, Kwang-Seop Kim
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Patent number: 7818349Abstract: An ultra-shared-nothing parallel database system includes at least one master node and multiple slave nodes. A database consisting of at least one fact table and multiple dimension tables is partitioned and distributed across the slave nodes of the database system so that queries are processed in parallel without requiring the transfer of data between the slave nodes. The fact table and a first dimension table of the database are partitioned across the slave nodes. The other dimension tables of the database are duplicated on each of the slave nodes and at least one of these other dimension tables is partitioned across the slave nodes.Type: GrantFiled: February 17, 2005Date of Patent: October 19, 2010Assignee: DATAllegro, Inc.Inventor: Stuart Frost
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Publication number: 20100262803Abstract: A storage method and system where the storage system includes a plurality of servers and a control server configured to select a storage area available to be used by each of the servers from among storage areas of a group of storage devices sharable among the plurality of servers. The system includes, a detecting unit configured to detect an available capacity of a specified storage device other than the storage group, where the specified storage device is designated for use only by a specified server selected from among the servers, a specifying unit configured to specify an available area corresponding to the available capacity detected from the specified storage device through the detecting unit, and a setting unit configured to set the specified available area to a shared storage area that is available to be shared among the server.Type: ApplicationFiled: March 31, 2010Publication date: October 14, 2010Applicant: FUJITSU LIMITEDInventors: Kosuke UCHIDA, Yasuo Noguchi
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Publication number: 20100262766Abstract: A method of formatting a data storage device that includes a plurality of flash memory chips includes monitoring a failure rate of memory blocks of one or more flash memory chips of a storage device that has a first usable size for user space applications, estimating a future usable size of the data storage device based on the monitored failure rate, and defining, via a host coupled to the data storage device, a second usable size of the data storage device for user space applications based on the monitored failure rate.Type: ApplicationFiled: April 7, 2010Publication date: October 14, 2010Applicant: GOOGLE INC.Inventors: Robert Stevan Sprinkle, Albert T. Borchers, Andrew Timothy Swing
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Patent number: 7814289Abstract: A virtualization system, upon judging that a write operation from a higher-level device is an operation to write in the format of the virtual volume, even when the write position of the write operation is in a virtual area different from a virtual area to which an allocated actual area has been allocated, if there is an unused area in the allocated actual area, writes management information to the unused area according to the write operation, and if there is no unused area in the allocated actual area, newly allocates an unallocated actual area, and writes management information to the newly allocated actual area according to the write operation.Type: GrantFiled: November 28, 2006Date of Patent: October 12, 2010Assignee: Hitachi, Ltd.Inventors: Shintaro Inoue, Yutaka Takata, Mikio Fukuoka, Eiju Katsuragi, Hisaharu Takeuchi
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Publication number: 20100257333Abstract: A storage system connected to a computer and a management computer, includes storage devices accessed by the computer, and a control unit for controlling the storage devices. A first-type logical device corresponding to a storage area set in at least one of the storage devices and a second-type logical device that is a virtual storage area are provided. The control unit sets at least two of the first-type logical devices different in a characteristic as storage areas included in a storage pool through mapping. The first-type logical device stores data by allocating a storage area of the second-type logical device to a storage area of the first-type logical device mapped to the storage pool. The characteristic of the second-type logical device can be changed by changing the allocated storage area of the second-type logical device to a storage area of another first-type logical device.Type: ApplicationFiled: June 17, 2010Publication date: October 7, 2010Applicant: Hitachi, Ltd.Inventor: Yoshiaki Eguchi
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Patent number: 7809914Abstract: A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library.Type: GrantFiled: November 7, 2005Date of Patent: October 5, 2010Assignee: CommVault Systems, Inc.Inventors: Rajiv Kottomtharayil, Ho-Chi Chen
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Patent number: 7809900Abstract: A system, method, and computer program product are provided for delaying operations that reduce a lifetime of memory. In use, at least one aspect associated with a lifetime of memory is identified. To this end, at least one operation that reduces the lifetime of the memory is delayed, based on the aspect.Type: GrantFiled: September 7, 2007Date of Patent: October 5, 2010Assignee: SandForce, Inc.Inventor: Radoslav Danilak
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Patent number: 7809902Abstract: Provided is a system and method for de-interleaving a data stream stored in a buffer having a plurality of memory locations. Each location has a memory width of (W) bytes and the data stream is formed of a number of data words each including (N) number of data bytes, and (N) is a non-integer multiple of the width (W). The method includes storing the data words into respective memory locations and appending each of the stored data words with number (X) of dummy bytes, a sum of (N)+(X) being an integer multiple of the width (W). The appended dummy bytes are then stored in the respective memory locations.Type: GrantFiled: January 24, 2003Date of Patent: October 5, 2010Assignee: Broadcom CorporationInventors: Gregory H. Efland, Jeff Z. Guan, Lin Yin
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Publication number: 20100241798Abstract: A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation.Type: ApplicationFiled: June 4, 2010Publication date: September 23, 2010Inventor: Wanmo Wong
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Patent number: 7801163Abstract: A method for allocating space among a plurality of queues in a buffer includes sorting all the queues of the buffer according to size, thereby to establish a sorted order of the queues. At least one group of the queues is selected, consisting of a given number of the queues in accordance with the sorted order. A portion of the space in the buffer is allocated to the group, responsive to the number of the queues in the group. A data packet is accepted into one of the queues in the group responsive to whether the data packet will cause the space occupied in the buffer by the queues in the group to exceed the allocated portion of the space.Type: GrantFiled: April 13, 2006Date of Patent: September 21, 2010Inventors: Yishay Mansour, Alexander Kesselman
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Patent number: 7797489Abstract: A system and method for managing space availability in a distributed striped file system is provided. A master data server is configured to send space availability detection messages to a plurality of data volumes servers hosting constituent volumes of a striped volume set. If one of the constituent volumes in the striped volume set has a low-in-space flag set, then the master data volume instructs all of the constituent volumes to set a low-in-space required flag, and no further writes are accepted for the striped volume set. The low-in-space and low-in-space required flags represent two states, and these states are returned in response to subsequent space availability detection messages from the master data server. A procedure for utilizing reserved space to complete an accepted cross stripe write operation is also provided.Type: GrantFiled: June 1, 2007Date of Patent: September 14, 2010Assignee: NetApp, Inc.Inventors: Tianyu Jiang, Richard P. Jernigan, IV, Eric Hamilton
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Patent number: 7783824Abstract: A data processing device 1 has flash ROM having a plurality of sectors, and a CPU for erasing data stored in a predetermined area of the flash ROM. A plurality of erase areas is set in the flash ROM based on the sector structures of a plurality of flash ROM devices. The CPU erases data using the erase areas set in flash ROM.Type: GrantFiled: November 1, 2006Date of Patent: August 24, 2010Assignee: Seiko Epson CorporationInventors: Masanao Nakazawa, Atsushi Natsuno, Mitsuaki Teradaira
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Publication number: 20100211704Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.Type: ApplicationFiled: February 12, 2010Publication date: August 19, 2010Applicant: Renesas Technology Corp.Inventor: Ryohei Higuchi
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Publication number: 20100211756Abstract: A system and method for allocating memory to multi-threaded programs on a Non-Uniform Memory Access (NUMA) computer system using a NUMA-aware memory heap manager is disclosed. In embodiments, a NUMA-aware memory heap manager may attempt to maximize the locality of memory allocations in a NUMA system by allocating memory blocks that are near, or on the same node, as the thread that requested the memory allocation. A heap manager may keep track of each memory block's location and satisfy allocation requests by determining an allocation node dependent, at least in part, on its locality to that of the requesting thread. When possible, a heap manger may attempt to allocate memory on the same node as the requesting thread. The heap manager may be non-application-specific, may employ multiple levels of free block caching, and/or may employ various listings that associate given memory blocks with each NUMA node.Type: ApplicationFiled: February 18, 2009Publication date: August 19, 2010Inventors: Patryk Kaminski, Keith Lowery
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Patent number: 7779215Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.Type: GrantFiled: March 4, 2005Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventors: Ming-Shi Liou, Bowei Hsieh, Jiin Lai
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Patent number: 7774571Abstract: Provided is a system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends is queued for use by another task in a queue at a selected location within the queue in accordance with the classification of said allocation unit. In one embodiment, an allocation unit is queued at a first end of the queue if classified in a first class and is queued at a second end of the queue if classified in said second class. Other embodiments are described and claimed.Type: GrantFiled: December 10, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Michael Thomas Benhase, Lawrence Carter Blount, James Chien-Chiung Chen, Juan Alonso Coronado, Roger Gregory Hathorn
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Patent number: 7761683Abstract: A variable width memory system is disclosed. The variable width memory system facilitates efficient utilization of memory resources and delivery of information in a convenient manner. A plurality of memory locations store information and the bit widths of at least two of the memory locations are different. A controller directs access to the plurality of memory locations. Information is communicated between the controller and memory locations via a bus coupled to the controller and memory locations.Type: GrantFiled: March 5, 2002Date of Patent: July 20, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventor: Brian N. Ripley
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Patent number: 7757063Abstract: There are disclosed systems and computer program products for dynamically resizing memory pools used by database management systems. In one aspect, if a decrease in allocation to the memory pool is required, at least one page grouping that may be freed from the memory pool is identified as a candidate based on its position in a list of page groupings. If the page grouping contains any used memory blocks, the used memory blocks may be copied from a candidate page grouping to another page grouping in the list in order to free the candidate page grouping. Once the candidate page grouping is free of used memory blocks, the candidate page grouping may be freed from the memory pool. As an example, this system or computer program product may be used for dynamically resizing locklists or lock memory.Type: GrantFiled: October 30, 2008Date of Patent: July 13, 2010Assignee: International Business Machines CorporationInventors: Wojciech Kuczynski, Adam J. Storm, Roger Luo Quan Zheng, Sarah Posner, Christian Marcelo Garcia-Arellano, Sam Sampson Lightstone
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Publication number: 20100174860Abstract: Disclosed are a non-volatile memory and page dynamic allocation and mapping technology thereof. According to the page dynamic allocation and mapping technology, by variable memory allocation, fragmentation may be prevented and page faults may be minimized in response to pages being loaded through page mapping of the non-volatile memory.Type: ApplicationFiled: December 15, 2009Publication date: July 8, 2010Inventor: Min-chan KIM
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Patent number: 7752412Abstract: In a nonvolatile memory system, a host allocates clusters and records allocation information in a File Allocation Table that is stored in the nonvolatile memory. A controller separately allocates certain data and records allocation in a record in a volatile memory. File Allocation Table information provided to the host is modified according to the record in the volatile memory.Type: GrantFiled: September 29, 2006Date of Patent: July 6, 2010Assignee: Sandisk CorporationInventors: Andrew Tomlin, Sergey Anatolievich Gorobets
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Patent number: 7747813Abstract: An apparatus, method, and computer program product are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.Type: GrantFiled: September 7, 2007Date of Patent: June 29, 2010Assignee: SandForce, Inc.Inventor: Radoslav Danilak
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Patent number: 7739312Abstract: An apparatus and method for containerization of multiple data objects within a block of a single container. The apparatus and method may pack multiple data objects together in a block of a logical container in a file system. The method may include receiving data in the form of multiple data objects to be stored in a file system, and collectively data packing the multiple data objects together in at least one block of a logical container in the file system. The block is a fundamental unit of storage space of the file system, and each block of the logical container includes multiple extents to store data from at least one data object of the multiple objects. The apparatus may include a plurality of storage devices coupled to a storage server. The storage server is configured to store the multiple data objects in at least one block of the logical container in the file system. Some data objects may be stored in multiple extents of one or more blocks depending on the size of the data object.Type: GrantFiled: April 27, 2007Date of Patent: June 15, 2010Assignee: Network Appliance, Inc.Inventors: Colin Stebbins Gordon, Pratap Vikram Singh, Donald Alvin Trimmer
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Patent number: 7733348Abstract: The present invention provides an image processing apparatus that can make effective use of a memory area.Type: GrantFiled: June 14, 2005Date of Patent: June 8, 2010Assignee: Canon Kabushiki KaishaInventors: Yoshiaki Katahira, Fumio Shoji, Takao Ikuno, Masahiro Odaira, Toru Fujino, Kenji Kasuya, Noritsugu Okayama, Yasuhito Niikura
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Patent number: 7734888Abstract: A file system receives a request to set a capacity guarantee for a virtual volume associated with a logical aggregation of physical storage. In response, the file system sets the capacity guarantee to indicate that the logical aggregation of physical storage is to provide a specified amount of space to the virtual volume. The amount of space provided to the virtual volume may be based, at least in part, on a guarantee type. The guarantee type may include, for example, volume, file, none, or partial.Type: GrantFiled: April 8, 2005Date of Patent: June 8, 2010Assignee: Netapp, Inc.Inventors: Eric C. Hamilton, Peter Griess, Robert L. Fair, Himanshu Aggarwal, John K. Edwards
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Patent number: 7730279Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.Type: GrantFiled: April 24, 2009Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Adam P. Burns, Michael N. Day, Brian Flachs, H. Peter Hofstee, Charles R. Johns, John Liberty
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Patent number: 7730277Abstract: A multi-stage technique invalidates and replaces loadable physical volume block numbers (pvbns) stored in indirect blocks of a dual vbn (“flexible”) virtual volume (vvol) of a storage system to enable efficient image transfers and/or fragmentation handling of the flexible vvol. Each loadable pvbn of a pvbn/virtual vbn (vvbn) block pointer pair is converted into a special block pointer having a predefined reserved value that provides a temporary “pvbn_unknown” placeholder until replaced by a real (actual) pvbn. The technique further allows the storage system to serve data from the flexible vvol using the placeholders while the actual pvbns are computed, thereby eliminating latencies associated with completion of actual pvbn replacement for the pvbn_unknown placeholders.Type: GrantFiled: October 25, 2004Date of Patent: June 1, 2010Assignee: NetApp, Inc.Inventors: Ashish Prakash, John K. Edwards, Sriram Rao
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Publication number: 20100131698Abstract: A memory sharing method for flash driver includes determining a target memory size corresponding to a target flash driver, and loading a target flash program included in the target flash driver into a stack memory allocated in a specific memory device when an unused size of the stack memory available for data storage is greater than the target memory size. Additionally, the step of determining the target memory size includes determining a specific flash program having a maximum size among a plurality of flash programs included in the target flash driver, and setting the target memory size equal to the maximum size of the specific flash program.Type: ApplicationFiled: November 24, 2008Publication date: May 27, 2010Inventor: Chien-Liang Tsai
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Publication number: 20100122061Abstract: Systems, memory modules and methods of configuring systems including memory modules are provided. The memory modules include device parameters specifically corresponding to memory devices of the memory module. The device parameters may be retrieved from a database, and the system may be configured in accordance with the device parameters retrieved from the database.Type: ApplicationFiled: January 20, 2010Publication date: May 13, 2010Applicant: Micron Technology, Inc.Inventors: Jeffery W. Janzen, Scott Schaefer, Todd D. Farrell
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Publication number: 20100122049Abstract: A system and method for managing an electronic storage volume is described. The method includes assigning a threshold to a constrained storage space to define a first state in which an amount of data stored in the constrained storage space exceeds the threshold and a second state in which the amount of data stored in the confined storage space does not exceed the threshold. The method also includes comparing the amount of data to be stored in the constrained storage space and the threshold, and performing a predefined action if the comparison indicates that the amount data to be in the confined storage space would cause a transition between the first state and the second state.Type: ApplicationFiled: January 19, 2010Publication date: May 13, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruthie D. Lyle, Fonda Daniels, Andrew L. Schirmer
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Publication number: 20100115225Abstract: Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed.Type: ApplicationFiled: October 13, 2009Publication date: May 6, 2010Inventors: Jaehong Kim, Heeseok Eun, Yong June Kim, Seung-Hwan Song
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Publication number: 20100115185Abstract: Without corresponding to different address spaces between an access device (100) and a nonvolatile memory device (200), the access device (100) designates a file ID to manage a data storing state only in a physical address space in the nonvolatile memory device (200). The access device (100) sends the nonvolatile memory device (200) a transfer rate through a transfer rate transmitting unit (121). A filling-up rate calculating unit (251) calculates a filling-up rate of a physical block corresponding to an assurance speed required by the access device (100). A remaining amount corresponding to the transfer rate is sought by using the calculated rate and is transmitted to a remaining amount receiving unit (122) of the access device (100).Type: ApplicationFiled: August 7, 2007Publication date: May 6, 2010Applicant: PANASONIC CORPORATIONInventors: Tadashi Ono, Tatsuya Adachi, Masahiro Nakanishi, Takuji Maeda
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Patent number: 7702877Abstract: A RAID storage system includes an outer stripe size that is an integer multiple J of a product of an inner stripe size and a number of data disks in a RAID disk set, where J is greater than one (1).Type: GrantFiled: December 27, 2006Date of Patent: April 20, 2010Assignee: ARRIS GroupInventors: William A. Braun, Benedict J. Jackson
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Patent number: 7702849Abstract: The invention relates to a method for storing data (DATA) on a memory medium (MEM). The data (DATA) forms a file totality (FILE) and the memory medium (MEM) includes several unit-storage areas (U1-U10). At least one first bookkeeping (FDE, FAT) is maintained of the storage state of the memory medium, which consists of information of the location in the unit-storage areas of the data belonging to each file totality. In the storing process—the data is stored in the unit storage areas and—the said first bookkeeping, for example, concerning the location of the data in the unit storage areas, is updated. The data forming the said file totality is stored as file parts (file1, file2, fileN), on the data (data1, data2, . . . , dataN) of which the said storing process is performed.Type: GrantFiled: September 3, 2004Date of Patent: April 20, 2010Assignee: Nokia CorporationInventors: Pertti Saarinen, Osmo Schroderus
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Publication number: 20100095083Abstract: A method for selectively utilizing a plurality of disparate solid state storage locations is disclosed. The technology initially receives class types for a plurality of disparate solid state storage locations. The characteristics of the received data are determined. The received data is then allocated to one of the plurality of disparate solid state storage locations based upon the determined characteristics of the received data.Type: ApplicationFiled: December 16, 2009Publication date: April 15, 2010Applicant: Microsoft CorporationInventors: Bohdan Raciborski, Dilesh Dhokia, Bhrighu Sareen
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Patent number: 7697329Abstract: Methods, apparatus, and systems in accordance with this invention include memories that include a data array and a configuration array adapted to store configuration information for configuring the data array. The data array and the configuration array include a plurality of wordlines and a plurality of bitlines. The plurality of wordlines in the data array extend in the same direction as the plurality of wordlines in the configuration array. Likewise, the plurality of bitlines in the data array extend in the same direction as the plurality of bitlines in the configuration array. The configuration array may include a wordline driver layout, a bitline driver layout, relative positions of zia contact regions, a diode sensing orientation, a sense amplifier layout, a voltage regulator layout, and a layout of conductors proximate to the array that are each substantially similar to corresponding elements of the data array. Numerous other aspects are disclosed.Type: GrantFiled: January 31, 2007Date of Patent: April 13, 2010Assignee: Sandisk 3D LLCInventors: Tyler Thorp, Brent Haukness
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Patent number: 7698520Abstract: A method for processing backup in the invention calculates a necessary capacity of a second storage medium when backing up in a plurality of divided sessions backup target data stored on a first storage medium, decides the number of dividing into the sessions based on the calculated necessary capacity and an available capacity of the second storage medium, and copies the backup target data from the first storage medium to the second storage medium, the backup target data being divided according to the number of dividing into the sessions.Type: GrantFiled: March 12, 2007Date of Patent: April 13, 2010Assignee: Seiko Epson CorporationInventors: Eiji Minami, Harutoshi Wada
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Patent number: 7694100Abstract: In one embodiment, a method is provided. The method of this embodiment provides determining if a management queue can be created, and if a management queue can be created, allocating virtually contiguous memory to a management queue associated with a device, registering the management queue, and creating a management queue context.Type: GrantFiled: December 20, 2004Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Hemal V. Shah, Gary Y. Tsao, Arturo L. Arizpe, Scott Hahn, Ali S. Oztaskin, Greg D Cummings, Ellen M. Deleganes
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Patent number: 7694102Abstract: There are disclosed systems, computer program products, and methods for self-tuning memory. In an embodiment, a method for self-tuning memory comprises setting a tuning interval and a target range for free memory for a memory pool. If memory consumption falls outside of the set target range for free memory during a tuning interval, a new target size for the memory pool is set based on the target range for free memory. Memory allocation for the memory pool is increased or decreased for the next tuning interval, such that the new target size for the memory pool is reached. A decrement rate may be used to provide a controlled decrease of the memory pool over a plurality of tuning intervals if necessary, until the new target size for the memory pool is reached.Type: GrantFiled: March 30, 2006Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Christian Marcelo Garcia-Arellano, Sam Sampson Lightstone, Adam J. Storm, Wojciech Kuczynski, Matthew Albert Huras, Xun Xue, Matthew James Carroll
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Patent number: 7694072Abstract: A system, method and computer program for allocating physical memory from a group of N memory devices to logical volumes. A group of N memory devices are partitioned into a plurality of bands, each of the group of N memory devices sharing a portion of each of the plurality of bands. A cluster map for each of the plurality of bands is generated. The cluster maps indicate the physical address for each of a plurality of clusters. Each of the plurality of clusters are distributed equally over two or more of the N memory devices to ensure a specified level of redundancy for each of the plurality of bands. Each of the N memory devices share an approximately equal number of clusters. Available bands are determined and are allocated to a logical volume.Type: GrantFiled: September 22, 2005Date of Patent: April 6, 2010Assignee: Xyratex Technology LimitedInventor: Paul Nehse
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Patent number: 7689799Abstract: Method and apparatus for specifying and identifying logic volumes in computer systems that store logical volumes on multiple storage elements are disclosed. The logical volume identifier may be unique with respect to all other logical volumes stored on the storage elements. The logical volumes may be conventional logical volumes, partitions, or hyper volumes.Type: GrantFiled: November 1, 2004Date of Patent: March 30, 2010Assignee: EMC CorporationInventor: David Black
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Patent number: 7689794Abstract: Disclosed are systems and methods for reserve allocation of event data. A request event is received. The request event is associated with memory storing request event data. Memory for response event data is allocated from a first pool. The response event data is associated with a response, and the response is associated with the request. Upon failure of the allocation of memory for the response event data, memory is obtained for out-of-memory response event data. The out-of-memory response event data is associated with the response event. The request event is completed using the response event.Type: GrantFiled: October 22, 2004Date of Patent: March 30, 2010Assignee: Scientific-Atlanta, LLCInventors: Eric Allen, Altan Stalker, Paul Porter, Mark Murray, David Decker
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Publication number: 20100077175Abstract: For decreasing seeks generated when switching an execution flow between commands to enhance read and write performances of a disc drive, a command is implemented with a specifically-designed data structure, and commands having neighboring physical addresses and the same type of read or write operations are grouped and linked together. With the aid of command groups, seeks between commands are significantly decreased, though starvation may arise. A few techniques are further provided for preventing starvation of command groups and for preserving the benefits of decreasing seeks.Type: ApplicationFiled: September 19, 2008Publication date: March 25, 2010Inventors: Ching-Yi Wu, Pao-Ching Tseng, Jih-Liang Juang
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Patent number: 7681008Abstract: In a nonvolatile memory system, a host allocates clusters and records allocation information in a File Allocation Table that is stored in the nonvolatile memory. A controller separately allocates certain data and records allocation in a record in a volatile memory. File Allocation Table information provided to the host is modified according to the record in the volatile memory.Type: GrantFiled: September 29, 2006Date of Patent: March 16, 2010Assignee: SanDisk CorporationInventors: Andrew Tomlin, Sergey Anatolievich Gorobets
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Patent number: 7676631Abstract: A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. In this way, a conventional CPU can be operated without read/write access to an external memory in respect of at least part of its memory address space, and therefore with a higher performance resulting from faster memory access and reduced external memory requirements. The CPU 3 may be one of a set of CPU chips 20, 21 in a data processing system, one or more of those chips 20 optionally having read/write access to an external memory 23.Type: GrantFiled: August 5, 2002Date of Patent: March 9, 2010Assignee: Infineon Technologies AGInventors: Taro Kamiko, Pramod Pandey
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Patent number: 7676627Abstract: A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process.Type: GrantFiled: January 10, 2007Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventors: Wanmo Wong, Karunakaran Muthusamy
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Patent number: 7676645Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.Type: GrantFiled: October 19, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Yu-Cheng Hsu, John Norbert McCauley, Cheng-Chung Song, William Griswold Sherman