Abstract: A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.

Abstract: A computer system including a processor and a storage device and a method for accessing at least one page of the storage device, are described. The computer system further includes a control circuit coupled to the processor and to the memory device. The control circuit is configured to change a state, such as open or closed, of the at least one page, when one of a page miss and row miss cycle to that at least one page is aborted. The control circuit is configured to restore the state of the at least one page a predetermined number of cycles after the state of the at least one page was changed. Performance benefits may be obtained in a computer system including a second level (L2) cache if upon a page miss or row miss cycle that has been aborted, the state of a page previously accessed is restored. The paging process efficiently controls the opening and closing of pages and takes into account the system architecture and the occurrence of certain events such as a host bus being idle, a cycle being aborted, etc.

Abstract: Architectures and circuits are described for various implementations of a memory-centric computing system for DSP and other compute-intensive applications. A shared, reconfigurable memory system is accessible to both a host processor or controller and to one or more execution units such as a DSP execution unit. By swapping memory space between the processor and the execution unit so as to support continuous execution and I/O, improved performance is achieved while cost is reduced. The shared memory system includes multiple reconfigurable memory segments to allow allocation of various amounts of memory to respective execution units or I/O or DMA channels as needed to optimize performance. A "virtual two-port" solution also is described for using single-port memory in the shared configuration with multiple address sources.

Abstract: A method and circuit are provided for generating a minimum-sized address filter to detect when the address space of an embedded memory having a smaller address space than another larger embedded memory is being exceeded. The method includes decomposing a maximum address into alternating sequences of consecutive binary ones (1's) and zeros (0's), discarding a final sequence if it contains binary 1's, and generating a filter circuit from a filter function formed from the alternating sequences of consecutive binary 1's and 0's. A built-in self test (BIST) circuit incorporating the address filter provides the ability to test a plurality of embedded memories at full speed in parallel. A computer system including a computer program for generating the filter circuit may also be provided.

Abstract: An automatic memory space switching method including the step of enabling a CPU of an electronic apparatus to run a BIOS of a ROM when started, the step of enabling the ROM to provide a control signal to the CPU, causing it to detect an updated version of software program in memory ICs, the step of enabling the CPU to control a switch controller and a common selector in switching a CSROM thereof to the memory IC which is stored with the updated version of software program when the CPU detects the existence of an updated version of software program in one memory IC, the step of enabling the CPU to run the detected updated version of software program and then to continuously run a posterior software program stored in the ROM, and the step of enabling the CPU to run the software program stored in the ROM without making a switching operation when the CPU detects no updated version of software program in the memory ICs.

Abstract: A non-volatile memory access protocol that facilitates concurrent accessing operations to multiple non-volatile memory components. This approach provides significant speed advantages over prior art non-volatile protocols. Also, power consumption is reduced in comparison to prior art synchronous protocols used for volatile memory because each memory component need not be continuously selected.

Abstract: A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller.

Abstract: An external hard disk is connected to a personal computer (PC) through the parallel port. A parallel-port expansion card is installed on the AT bus in the PC for communicating with the external hard disk. The parallel-port expansion card has a ROM containing intercept code. The address of the ROM is automatically configured when the system BIOS scans for expansion ROMs during booting. When no other ROM drives the data bus when an address is scanned, the parallel-port card latches the address and has the ROM drive its data onto the bus. Future accesses to the latched address access the ROM. The ROM's code replaces the interrupt table's starting address of the hard-disk-controller routine with the address of an intercept routine. All hard-disk operations using the interrupt first execute the intercept routine. The intercept routine copies any data writes to the external disk. Thus the external disk has a redundant copy of the PC's internal hard disk.

Abstract: A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

Abstract: When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer by generating and storing one or more incoming MMU (IMMU) entries that map the read buffer to an assigned global address range. The remote data read request, along with the assigned global address range is communicated to the server node. At the server, the request is serviced by performing a memory import operation, in which one or more outgoing MMU (OMMU) entries are generated and stored for mapping the global address range specified in the read request to a corresponding range of local physical addresses. The mapped local physical addresses in the server are not locations in the server's memory. The server then performs a DMA operation for directly transferring the data specified in the request message from the disk to the mapped local physical addresses.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device.

Abstract: A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.

Abstract: A method of locating a memory address of a nonvolatile memory card that corresponds to an external address in an integrated circuit card controller that controls memory operation of the card is described. The controller includes a first memory address mapping window and a second memory address mapping window, each storing one of a first and a second set of memory addresses of the nonvolatile memory card. The method includes the steps of accessing the first window for the memory address associated with the external address when external circuitry accesses the nonvolatile memory card with the external address. If the first window has the memory address, then the first window is accessed for the memory address. If the first window does not have the memory address, then the second window is accessed for the memory address. If the second window does not have the memory address, then the second window is updated with a third set of memory addresses of the nonvolatile memory card.

Abstract: A three-dimensional data storing method for storing three-dimensional (3-D) data on cubical vertices belonging to a cube, the method includes the steps of: index-numbering each vertex of the three-dimensional data so that cubical vertices on the surface belonging commonly to two neighboring cubes have the same index number; classifying the 3-D data according to each index number; and storing the classified 3-D data in a plurality of memories corresponding to each index number, whereby the three-dimensional data can be accessed in parallel.

Abstract: A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.

Abstract: To provide for fast access times with very large key fields, an associative memory utilizes a location addressable memory and look up tables to generate from a key an address in memory storing an associated record. The look up tables, stored in a memory, are constructed with the aid of arithmetic data compression methods to create a near perfect hashing of the keys. For encoding into the look up table, keys are divided into a string of symbols. Each symbol is assigned an index value, such that a modulo sum of index values for symbols of a particular key is a unique value that is used as an address to the memory storing the record associated with that key.

Abstract: A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater is operable to echo transactions in either an upstream or downstream direction. During configuration, the PCI repeater snoops configuration cycles on the primary bus to build an address map of devices on the primary bus. The PCI repeater then uses the address map as a lookup table as a positive determination of whether to forward a transaction upstream.

Abstract: By overlaying two memory banks to form a single, monolithic memory and setting a movable boundary point between those two banks, one can exceed the fixed addressing capability of a microprocessor. By moving the boundary, one can then access common-value memory locations in one or the other of the memory regions. The manipulation of the boundary can be performed by a microprocessor.

Abstract: In a data processing unit having a plurality of general purpose registers, an instruction is loaded. Such an instruction includes an operation, and at least one operand field, where the operand field specifies one of a plurality of base registers and a displacement value. To calculate a general purpose register address specified by such an operand field, the displacement value is added to a base value stored in a base register that is specified by a portion of the operand field. Finally, the data processing unit addresses a selected one of the general purpose registers, utilizing the calculated general purpose register address, for execution of the specified operation. Thus, the data processing unit is capable of addressing a larger number of general purpose registers than may be directly addressed utilizing a value represented by a limited number of bits within the operand field.

Abstract: A real time clock plus user memory and extra memory integrated in a single circuit with access to the extra memory either by direct addressing or by providing the address as data to specified addresses in the user memory. Further, the user memory has two banks with the same addresses, and bank selection derives from a bit in another portion of the user memory.

Abstract: A method for partitioning keys onto radix tree logical pages and a parallel index page build algorithm in order to provide radix tree build speedup proportional to the number of processors on the system and controlled efficient page utilization. Also, since keys are intelligently partitioned so that a complete set of keys is inserted into a logical page, there is no page overflow during the tree construction and thus page splitting is eliminated. Since radix index trees are really groups of logical pages in which each logical page contains a small tree, the tree is built (with respect to the logical pages) from the bottom up, while within each individual logical page the tree is constructed from the top down. The space required for a logical page is pre-allocated to allow construction of limbs to begin without waiting for the build of their underlying pages to complete.

Abstract: A data processing system includes a microprocessor and a memory coupled to each other, and has a burst access function in which, when an active burst request signal is supplied to the memory, only a first address is outputted to the memory, so that a plurality of items of data are accessed sequentially from the first address. A memory region of the memory is divided into a plurality of memory blocks, and the microcomputer includes a register for storing burst access/single access information for each of the memory blocks, and a decoder receiving an address to be outputted to the memory for knowing to which memory block a memory region to be accessed belongs. When the memory region to be accessed is a memory block for the burst access, a burst request signal is activated.

Abstract: A data processing system (10) including a chip select circuit (40) which allows flexible attribute protection, and a method for providing a plurality of chip select signals in the data processing system are disclosed. Each of two or more decoders (42, 48) determines whether a bus cycle address is within a programmable region and matches one or more programmable attributes, and if so activates a corresponding match signal. A logical operation circuit (60) then selectively causes a chip select signal (72) to be activated in response to a logical operation performed on the match signals. In one embodiment, the logical operation circuit (60) may cause the chip select signal (72) to be activated if either of two match signals (47, 53) is activated, allowing for example the same region of memory to be accessed from two address spaces using the same chip select signal (72).

Abstract: A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.

Abstract: A paging receiver includes a receiver, a decoder 303, a central processing unit 102, a ROM 104 in which programs to be executed by the CPU and data are stored in a plurality of bank modes, a RAM 105, and a demodulated data outputting apparatus. The decoder includes a bank mode switching register 601 that is used to select a plurality of bank modes. The register stores an initial hardware value and a bank switch value that is used to select one of the plurality of bank modes upon initialization by software, and one of the plurality of bank modes is selected in accordance with the initial hardware value and the bank switch value by the software. When the capacity of the ROM is limited, the capacity of the ROM can be assured sufficiently only by selecting one of the bank modes, and software designing can proceed only after some change of design.

Abstract: An interface between a memory that has "n" address bit inputs and a processor which has "p" address bit outputs (where p<n) and "q" programmable data bit outputs (where q.gtoreq.n-p). The interface includes a logic circuit connected to a byte select bit output, to a memory read-write command bit output and to an appropriately programmed one of the "q" programmable bit outputs of the processor. The logic circuit produces a least significant bit address bit input AI0 defined by the equation AI0=R/W & byte-s OR R/W & I/O0. The interface connects the remaining "p" address bit inputs of the memory succeeding to the "p" address bit outputs of the processor, in order, and connects the remaining "n-p-1" most significant address bit inputs of the memory to the same number of appropriately programmed programmable bit outputs of the processor.

Abstract: Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The allocation circuitry has a first circuit which identifies related data units by identifying a probability that the related data units may be successively read from the cache memory. A second circuit within the allocation circuitry allocates the corresponding entries in each of the ways to the related data units, so that related data units are stored in a common set of entries. Accordingly, the related data units will be simultaneously outputted from the set-associative cache memory, and are thus concurrently available for processing. The invention may find application in allocating entries of a common set in a branch prediction table (BPT) to branch prediction information for related branch instructions.

Abstract: Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Abstract: A distributed computer system is disclosed which includes a central location and a plurality of remote locations. A central location computer system generates a module which includes a data section containing a plurality of data units. Each of the data units is either a minimum addressable data unit or a longer data unit. Each longer data unit contains a plurality of minimum addressable data units. The module also includes a swap section containing data identifying locations of longer data units within the data section. A remote location computer system receives a module, and contains a loader. The loader swaps the minimum addressable data units of the longer data units in the data section. A transmission link, transmits the module from the central location computer system to the remote location computer system.

Abstract: A parallel computer of a distributed storage type, which can omit an overhead time of a processing apparatus required for an address computation, is provided with an array address converting apparatus for generating a PE number of a PE retaining an array element that is an object of an access and an address on storage apparatus of the array element within the PE in each PE. Upon an access to an array element of array data, the processing apparatus activates the array address converting apparatus, a communicating apparatus gives an address on storage apparatus generated by the array address converting apparatus to a PE having a PE number generated by the array address converting apparatus to transmit access demand information for the array element. This parallel computer of a distributed storage type is applicable to a computer system for processing enormous data at a high speed such as numerical calculation, image processing or the like.

Abstract: Read Only Memory (ROM) (10) data may be selectively inverted to decrease energy dissipation. Within the ROM (10), a plurality of memory cells (16) are connected to bit-line (18) and word-line (20) and store data, which determines the loading for a particular line. Line loading may be manipulated by accessing initial mapping information (23) of the ROM (10) and calculating the line loading on each line (18 or 20) and whenever a line's load exceeds a threshold, data stored in the memory cells (16) on the particular line (18 or 20) are inverted. Having done this, new mapping information (23) is produced and used to retrieve data from the ROM (10).

Abstract: A memory access method and apparatus which may access bytes of information from two contiguous memory segment addresses at a time. The amount of information which is accessed at one time is a memory access unit. The number of bytes in a memory segment is also the number of bytes in a memory access unit. The method and apparatus for accessing memory divides each memory segment between separate memories having the same number as the number of bytes in a memory segment. Each of the memories are simultaneously addressed according to a segment address input and an offset input, to thereby enable selected bytes of information stored through two contiguous memory segment addresses to be accessed. Although bytes in two contiguous memory segments may be accessed at a given moment, no more bytes than are contained in a memory access unit are accessed at a given moment.

Abstract: Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the processor 100 determines whether the interrupt is of a fast interrupt type. When the interrupt if of a fast interrupt type, the processor executes the operational codes identified by the interrupt without having to flag the main set of operational codes. Upon completion of the fast interrupt, the processor 100 resumes performing the main set of operational codes. In addition to performing the fast interrupt, the processor 100 contemporaneously performs a data block identification routine. When the data block identification routine identifies a data block, the main set of operational codes is interrupted to perform a data block service routine. The processor 100 includes an address generation unit 102 and a peripheral address generation unit 104.

Abstract: A control device is provided that controls a connection between a specific one of a plurality of arithmetic processors and a specific one of a plurality of main memory units in accordance with an access request supplied from the specific arithmetic processor. The access request has request tag information. A buffer section buffers the request tag information in response to a write-in address. A supplying section supplies the specific main memory unit with an additional access request having the write-in address as an identifier instead of the request tag information. When the specific main memory access ends, the specific memory unit supplies the control device with a reply signal having the identifier as a reply identifier. A read section reads the request tag information out of the buffer section in accordance with the reply identifier. The request tag information is delivered from the control device to the specific arithmetic processor.

Abstract: A single wire data bus is utilized by a bus master to communicate with and identify electronic devices also connected to the single wire data bus. Each of the electronic devices include a unique ID (identification), wherein the bus master, using a one-wire protocol, can identify all of the electronic devices connected to the single wire data bus.

Abstract: A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an address item (ADI) for a point (PO) of a two-dimensional space of points (IM) associated with data coded on 2.sup.d bits, the respective bits of the first and second words representing two coordinates (X, Y) of the point in the said space. A configuration input receives a value of k (k1, k2, k3), chosen to be positive or zero and less than or equal to n, and representative of a geometrical configuration chosen for the two-dimensional?s!?pace! space (IM).

Abstract: A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.

Abstract: A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.