Abstract: In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Abstract: A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

Abstract: A memory controller for an incoming multi-channel bitstream including a computer memory having an address range, a plurality of memory controllers, and a selector coupling the memory controllers to the computer memory. Each memory controller is capable of providing an address within the address range of the computer memory. In use, the selector selects a memory controller based on a received data type in an incoming bitstream. The selector then provides an address received from the selected memory controller to the computer memory.

Abstract: The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual copy of the I/O facilities to be shared. The remote translation control entry table on the hosted partition is loaded with data from a hypervisor in response to requests made by the OS running in the hosted partition. The hypervisor, in response to requests from the OS running in the hosting partition, copies the data from the remote translation control entry into a standard translation control entry table on the hosting partition owning the physical I/O facilities that target the I/O page buffers of the hosted partition to perform the desired I/O operation. The I/O page buffers of the hosted partition are accessed by the hosting partition's I/O facilities using the data stored in the standard translation control entry table.

Abstract: Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.

Abstract: A digital camera (10) includes a shutter button (50). When the shutter button (50) is depressed, a file name and size information “0” is written into a directory entry of a recording medium (44), and a movie file to which a plurality of markers are assigned in a predetermined manner is recorded in a data area of the recording medium (44). Upon completion of recording the movie file, FAT information showing a ring state of the movie file is written into an FAT area of the recording medium (44), and size information of the directory entry is rewritten. The file name of the latest movie file is stored in a non-volatile memory (M), and a CPU (46) detects the size information of the latest movie file from the directory entry based on the file name when a power switch (54) is input. When the detected size information indicates “0”, the FAT information is created based on the marker assigned to the latest movie file.

Abstract: A register setting method which facilitates writing of change information into a register for storing operation condition information that defines the operation of a device. The method includes the steps of storing first operation condition information in a first register, storing second operation condition information in a second register, changing the first operation condition information, and when the first operation condition information is changed, changing the second operation condition information to changed first operation condition information in accordance with change information for changing the first operation condition information.

Abstract: A method for removing cookies, temporary Internet files, and defragmenting a hard drive to optimize streaming video performance. A program residing on a computer automatically (and configurably) removes cookies and temporary Internet files from a hard drive, and defragments the hard drive on shutdown of the computer system.

Abstract: A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the memory address. The memory interface can connect to a host configured to access data in a conventional SDRAM memory device so that the host can access data in the memory.

Abstract: An information processing method separates tone component information higher than a trial frequency band and quantization accuracy information and normalization coefficient information of non-tone components higher than the trial frequency band. The number of tone components and the number of quantization units are minimized (to zero), and the other data is arranged in an extended area that cannot be referred to by a known player. Trial time information is written in an area containing unreferenced spectral coefficient information, which may be replaced, where necessary, with dummy data. A player for playing trial data refers to the trial time information, selects a random portion(s) from a trial-permitted area(s), the total playback time being within the trial time, and rearranges data included in the extended area of each selected frame at a playable position, thus playing the trial data. The present invention is applicable to encoders, data players, and data recorders.

Abstract: A circular buffer for use in a telecommunications system is described as well as a method of operating the same in which data is protected during wraparound procedures. In the operation of the circular buffer at least four reference values are stored to enable address calculations: a first reference value representative of a begin address of the circular buffer; a second reference value representative of an end address of the circular buffer; a third reference value representative of a current write address of the circular buffer; and a fourth reference value representative of a current read address of the circular buffer. The cyclic state of the buffer is also monitored in order to protect the data after a wraparound or when the buffer is full. The buffer is able to accommodate multirate data arrival.

Abstract: The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.

Abstract: A method for interpreter optimization includes receiving multiple data units organized according to a first endian order, reordering the data units according to a second endian order and interpreting the reordered data units. According to one aspect, the data units include at least one opcode having at least one operand, each operand including at least one data unit. According to another aspect, a class loader reorders the code within a classfile from big-endian format to little-endian format.

Abstract: A method for capturing characters of a file utilizes a printer driver program to capture the characters. Since a file is intended to be printed, the characters is distinguished from image codes of the file by the printer driver program, the characters thus is able to be intercepted and captured during the file printing process. The captured characters that represent text contents of the file are further provided to created and expand a database. Therefore, the database has the searchable text contents, i.e. the captured characters, without any need of a file format recognizing process.

Abstract: There are provided a voltage level control circuit with a reduced power comsumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through.

Abstract: An electronic apparatus has in a CPU core an instruction correcting circuit that includes memory cells, a comparator and a selector. The memory cells store, when initializing the electronic apparatus, a correction address, a correction instruction and a correction enabling bit, which are associated with contents of a read-only memory. The comparator compares an instruction address output from an instruction prefetch stage of the CPU core with the correction address stored in the memory cells. The selector selects either an instruction code read from the instruction address of the read-only memory or the correction instruction stored in the memory cells in response to a compared result of the comparator. The electronic apparatus can correct the ROM data after manufacturing without reducing the number of available interrupts or the operation speed of the CPU.

Abstract: We propose a new form of software transactional memory (STM) designed to support dynamic-sized data structures, and we describe a novel non-blocking implementation. The non-blocking property we consider is obstruction-freedom. Obstruction-freedom is weaker than lock-freedom; as a result, it admits substantially simpler and more efficient implementations. An interesting feature of our obstruction-free STM implementation is its ability to use of modular contention managers to ensure progress in practice.

Abstract: A storage sub-system employs a staging control information table by which staging of data to be read and redundant data thereof can be executed together to reduce response time in the event of a data read failure. The staging control information table also permits pre-read staging to be executed in the forward, backward or both the forward and backward directions, to reduce response time.

Abstract: Disclosed is a method and apparatus for detecting and monitoring program hot spots during execution that may be implemented in hardware. A hot spot detector tracks branch instructions which are retired. Frequently executed branch instruction addresses within a particular interval are designated as hot spot candidates. A hot spot detection counter is used to track non-hot spot branches and hot spot candidate branches. When hot spot candidate branches are frequently encountered compared to non-hot spot candidate branches, the hot spot detector may notify the operating system and hot spot candidate branch addresses may be supplied to a runtime optimizing compiler and a monitor table or a hot spot monitor. The hot spot monitor may disable the hot spot detector when a program is operating in known hot spots and may enable the hot spot detector if the program has strayed from known hot spots.

Abstract: A system and method for virtualizing a new network storage additionally installed and an existing network storage as a single file system by inheriting a directories tree structure from the existing network storage, wherein a virtualizing system of the new network storage has the function of reading out setup information of the existing network storage according to an expansion request from the administrator, registering the existing network storage as a member of the virtualizing system, copying a directories tree structure of the existing network storage, and swapping setup information of the existing network storage and that of he new network storage with each other.

Abstract: An IC card includes a card body, a memory section buried inside the card body and adapted to store data information and control information, and an interface section. The interface section inputs the data information to be stored in the memory section and outputs the data information stored in the memory section. The interface section also outputs the control information stored in the memory section. The memory section stores control information including card maker identification information to be reported to the outside. Therefore, it becomes possible to automatically identify the maker of each IC card, so that the IC card, the IC card reading/writing apparatus, etc., can be procured from multiple vendors when an IC card system is constructed.

Abstract: A large message can be stored by separating the message into an envelope portion containing information such as headers, protocols, and addresses, and a payload portion containing items such as file attachments. The envelope portion can be stored in local storage, while the payload can be stored to a persistent store. The message can be processed incrementally, such that the entire message is never in system memory. Once the envelope portion is processed, the payload portion can be read in increments without being processed, and those increments written directly to the persistent store. Alternatively, the payload can be streamed to the persistent store. A pointer in the envelope can then be used to locate and retrieve attachments from persistent storage.

Abstract: An improved backup system for computer networks provides simplified operation, reduced utilization of computer system resources, and increased recovery potential in the events of information loss. At each backup time interval, the computer system sends all files created or modified since the time stamp to the backup system. The file stream flowing from the computer system to the backup system contains metadata at the boundaries of each file. Once all files are received from the computer system, the backup system produces a new full backup tape by merging the present backup tape with the newly received files, replacing each file on the presently existing tape that was modified with the newer version of that file. The resulting backup tape contains substantially the same set of files that would result from a full backup, or, if desired, a higher level backup.

Abstract: The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: A method and system for detecting memory leaks in an object-oriented environment during real-time trace processing is provided. During the profiling of a program executing in a data processing system, a profiler processes events caused by the execution of the program, and the profiler maintains a profile data structure containing execution-related metrics for the program. The execution-related metrics may include object allocation and deallocation metrics that are associated with object processing initiated on behalf of an executing method. An object allocator allocates objects during the execution of the program and modifies object allocation metrics in the profile data structure. Object metrics are stored in a particular location and a pointer to that location is stored in a hash table associated with the object's ID. In another embodiment the pointer to the location is stored in a shadow heap in the same relative position as the position of the object in the heap.

Abstract: Featured is a method for reducing overhead associated with system input output (I/O) operations in a computer system having a plurality of processors and a physical memory accessed and used by the plurality of processors. The physical memory being accessed can be a global physical memory such as that used with SMP types of architectures or distributed physical memory such as that used with CCNUMA types of architectures. Such a method includes creating a pinned virtual memory range database in which is stored virtual memory address information corresponding to pinned physical memory for each applications program being run on the computer system. Also featured is an operating system for execution with a multiprocessor computer system and a multiprocessor computer including such an operating system for execution therein.

Abstract: A digital camera includes a CPU. When a memory card is attached to the digital camera, the CPU determines as to a format formed on the memory card. If the format is a normal format, the CPU changes the normal format to an optimal format. However, where an image file is already stored in the memory card or a directory for a file other than the image file is formed, the CPU does not change the format.

Abstract: This invention allows to control archive of data without any load on the operator of a service by automatically changing the archive condition in correspondence with product information related to the service. When data is to be archived in an apparatus connected to a network, the data archive period is changed on the basis of the information of a product related to the service, which is sent from the user. For example, when the archive condition is the archive period, control is executed to delete data that has expired.

Abstract: A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bi-directional ports. A pair of directors controls the flow of data to and from the disk drives. A first fiber channel port by-pass selector section is provided. The first fiber channel by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fiber channel links. The first fiber channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fiber channel selectively in accordance with a control signal fed to the first fiber channel by-pass selector section. The first fiber channel includes one, or more, of the first plurality of fiber channel links.

Abstract: A peer-to-peer cache architecture stores peer address certificates in different cache segments according to the number of IDs being stored and their relative distance in the peer name space. The cache instantiates regions of decreased range and increased granularity as additional information from close peers is learned. In a large peer cloud where the number of instantiated IDs is not known, each succeeding cache region covers one tenth of the preceding cache region. For peers with multiple IDs registered locally, the segmented cache of the present invention combines overlapping segments of the same granularity to eliminate the duplication of information that would otherwise occur. A cache tree, an instantiated segment tree, and an uninstantiated segment tree are arranged in red-black trees to simplify the search and proper placement and instantiation of information.

Abstract: Method and apparatus for providing data recovery in a one or multiple disk loss situation in a RAID5 like system. A data storage apparatus has a plurality of n disks storing data comprising a plurality of n data groupings stored across the plurality of n disks. Each one of the n data groupings comprises a data portion and a redundancy portion. The size of the data portion relative to the redundancy portion is as H to Q, where H/Q<(n−m)/m, where m is the maximum number of disks that may be lost at any given time. Advantageously, the n data portions are recoverable from any and all combinations of n-m data grouping(s) on n−m disk(s) when the other m data grouping(s) are unavailable, where 1≦m<n.

Abstract: A digital system is provided with a microprocessor (100), a cache (120) and various memory and devices (140a-140n). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) (130). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit (110) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.

Abstract: A method of forming a tantalum-containing layer on a substrate is described. The tantalum-containing layer is formed using a physical vapor deposition technique wherein a magnetic field in conjunction with an electric field function to confine material sputtered from a tantalum-containing target within a reaction zone of a deposition chamber. The electric field is generated by applying a power of at least 8 kilowatts to the tantalum-containing target. The magnetic field is generated from a magnetron including a first magnetic pole of a first magnetic polarity surrounded by a second magnetic pole of a second magnetic polarity opposite the first magnetic polarity. The first magnetic pole preferably has a magnetic flux at least about 30% greater than a magnetic flux of the second magnetic pole. The tantalum-containing layer deposition method is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, an interconnect structure is formed.

Abstract: A memory to support an Address-Data Multiplexed protocol in response to a substantially simultaneous assertion of RAS and CAS, and an Address—Address Multiplexed protocol in response to an assertion of RAS followed by an assertion of CAS.

Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

Abstract: A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests for a memory interface and receiving requested data from the memory interface, comprises a data transfer initiating unit for outputting first address data identifying a first memory range. Further, a boundary alignment unit is provided for generating second address data using the first address data, where the second address data identifies a second memory range that differs from the first memory range in at least one boundary. Further a corresponding boundary alignment may be done in a receive DMA engine. The DMA mechanism may be performed in a USB-2 host controller that has HyperTransport capabilities.

Abstract: A data processing device (4) for taking out necessary packet data from a sector in which a plurality of packet data exist in a mixed manner, is provided. This data processing device has an audio decoder unit (4b). The audio decoder unit has, in parallel, an audio packet extraction unit (43) for extracting an audio packet made up of audio data with respect to an input of sector data from an external memory (5) connected to a front-end processor unit (4a), a supplementary packet extraction unit (48) for extracting a supplementary packet made up of supplementary data, and a frame information extraction unit (52). Thus, when collectively providing the front-end processor unit and the audio decoder unit on one chip, a buffer memory for the frame state can be omitted.

Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

Abstract: The present invention comprises a device for use in a network environment equipped for upgrading system files, such as OS kernel, device drivers, network stacks and/or remote upgrade/install application, comprising a non volatile memory (15, 66), including:

Abstract: A system transfers BIOS instructions from a BIOS ROM to a processor for either execution or storage in a system memory. The BIOS ROM has an address bus coupled to an address bus of the processor and a data bus coupled to the an intelligent drive electronics (“IDE”) controller through the data bus portion of an IDE bus. In operation, the processor applies addresses directly to the address bus of the BIOS ROM, and the corresponding instructions are coupled through the IDE data bus and the system controller to the data bus of the processor.

Abstract: A multiprocessor system is described including a plurality of processors. At least one level of cache memory is operatively connected to each of the processors. At least one memory unit is shared by at least two of the processors. A status memory, in correspondence to each processor, is configured to store a current status in correspondence to memory regions capable of being stored in the cache memories. The current status indicates whether a memory region is non-shared. The system includes logic, in correspondence to and operatively connected to each processor, for generating minimum cache-coherence activities in response to a memory access request by a respective processor.

Abstract: A command filter selectively forwards received commands to a command queue for in-order execution. If the received command is a probe response command or if probe response information is extracted.from other commands, the probe response is stored in a storage location other than the command queue and executed out-of-order. Data movements specified by memory modifying commands already in the command queue and affecting the cache line in question are also performed out-of-order and the memory modifying command is discarded when it is removed in-order from the command queue.

Abstract: Instead of storing a previous version of file, a backup technique stores a transformation operator which reflects the differences between a previous version of a file and a subsequent version. The operator may include the difference between a numerical value in the previous file version and the corresponding value in a subsequent version. Further, the transformation operator may indicate textual or binary changes between the file versions. To recover the previous version, the transformation operator is applied to the newer version to regenerate the previous version. If desired, multiple transformation operators can be maintained for a given file to be able to regenerate more than just the immediately preceding version of the file, thereby creating a multilevel backup system. The transformation operators preferably are stored in a RAID-type storage system for fault tolerance.

Abstract: File management information for managing logical sequence of files recorded in a recording medium is formed and stored in a file management information storing unit. Block management information which includes a file number for identifying a file, sequential order number indicative of the sequential order of the block storing data of the file and page length information indicative of the size of the data stored in the block is formed and stored in a block management information storing unit. Access to the file is ensured based on the block management information, even when the file management information indicative of the logical sequence of the files is lost by accident.

Abstract: An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D2 next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D2, and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S1 into an address S2, and outputs the address S2 to the SRAM, which stores the data B at the address S2.

Abstract: Method and system aspects for increasing storage capacity in a digital image capture device are described. Compression levels of saved image files are utilized to increase storage capacity by identifying a level of compression of a saved image file in the digital image capture device. The identified level of compression is compared with a predetermined level of compression, and the saved image file is compressed to the predetermined level of compression when the identified level of compression does not match the predetermined level of compression to free storage space in the digital image capture device.

Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.