Abstract: An input/output (I/O) host adapter in an I/O system processes I/O requests from a host system to a plurality of I/O devices. The host adapter includes a circuit to automatically transfer I/O requests from host memory to adapter memory. The host adapter also includes a circuit to automatically transfer I/O responses from adapter memory to host memory.

Abstract: The present invention relates to the field of information extraction and storage and more specifically to techniques for extracting information from a plurality of articles in a distributed manner and for storing the extracted information in an information store. an embodiment of the present invention identifies a plurality of articles from which information is to be extracted and a plurality of information extractors for extracting the information from the articles. A database is provided for storing information related to the plurality of articles and the plurality of information extractors. The plurality of articles are assigned to the plurality of information extractors for information extraction. Information extracted by information extractors from the articles is stored in the information store.

Abstract: Provided are mechanisms that may be used to support efficient exportation of user data stored in a database system. According to an aspect of the present invention, a database system is configured to store data for users in separate repositories referred to as tablespaces. To store data in this manner, a database system may be configured in variety of ways.

Abstract: A buffer cache apparatus includes a storage unit storing data, a buffer cache and a control unit. The buffer cache stores a balanced tree and free lists. Data containing buffers are hierarchically provided as nodes in the balanced tree, and the free lists are respectively provided for different sizes. Each of the free lists includes at least one free buffer when the at least one free buffer exists. The control unit is responsive to a data request. The control unit searches the free lists for a desired buffer based on a size of a requested data requested by the data request, when the requested data does not exist in the balanced tree. Also, the control unit adds the desired buffer to the balanced tree to store the requested data from the storage unit into the desired buffer. The desired buffer has a size larger than the requested data size and as small as possible.

Abstract: A CAM may include a plurality of CAM cells. Each CAM cell is configured to generate an output indicating if a corresponding input bit and the bit stored in that CAM cell match. A circuit is configured to logically AND the outputs to generate a hit output. A first compare line generator circuit is configured to generate a first pulse responsive to a clock signal and a data signal and a second compare line generator circuit is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. A CAM may include a circuit configured to generate a pulse indicating a hit in an entry of the CAM and a latch circuit configured to capture the pulse responsive to the first clock signal and configured to clear responsive to the second clock signal. A first CAM may store a value in each entry and may further store a compare result.

Abstract: A system and method for synchronizing records stored in differing formats in a shared data environment. One aspect of the invention involves distinguishing a record without regard to its format. Once a record is introduced into the environment, it is detected. A record file is generated and associated with the event. A record file typically includes a record tag uniquely identifying a given record in the shared data environment and a record type indicating information such as whether or not the record represents a recurring event as well as the format of the record. A record file also contains data indicating the status of the particular event, that is, whether it is new, unchanged, modified, or deleted. When synchronizing, only those records with equivalent record tags are compared. The record type and status are then used to guide the synchronization of equivalent records.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: The equivalent computational precision in an associative memory is increased by determining the difference between the bit precision that is required in order to represent a given number in the memory and the bit precision that can be represented in a memory element of the memory, which is dictated by the inherent characteristics of the memory; determining, on the basis of the difference, the number of memory elements of the memory required in order to represent the given number with the required bit precision; and dividing the given number over the number of memory element of the memory, determining a base value to be loaded into the number of memory element and a remainder which indicates a subset of the number of memory element of the memory over which the remainder is to be divided.

Abstract: A method for updating firmware. The method includes providing replaceable information in a non-modifiable storage and replacement information in a modifiable storage or a removable storage and providing a replacement indicator. The replacement information is accessed instead of the replaceable information based upon the replacement indicator.

Abstract: An appliance includes a memory having at least a hidden partition of memory. The hidden partition of memory operates to store at least a portion of a program capable of contributing to one or more functions of the appliance. The appliance also includes a controller operable to process at least a portion of the program stored on the hidden portion of memory. The appliance further includes an external interface operable to provide access to at least an open portion of the memory. In one particular embodiment, the hidden portion of memory is inaccessible through the external interface.

Abstract: A system and method for automatically executing a participating application upon insertion of a removable media into a computing device. When the computing device detects that the removable media containing has been inserted, a task disk control file is read from the removable media. The task disk control file contains all of the configuration information necessary to run the participating application from the removable media. The participating application is then launched for use by a user. After the user is finished using the participating application, the removable disk is automatically ejected. In addition to monitoring for insertion of the removable media, events such as a completion of the self-contained application and a request to eject the media are monitored. When a completion event is encountered, all data files are saved, temporary files deleted and configuration information removed prior to the removable disk ejection.

Abstract: A system and method for data record summarization and exception testing is provided in which a data viewer program forms a logical pipe for processing and presenting data records from an input data record source to summarization and exception testing programs. The data viewer program creates a virtual data record stored in the processor memory of the system, which is then presented directly to the summarization and exception testing programs for processing. By providing this logical pipe between the input data record source and the processing programs, the present invention eliminates the need for intermediate storage files on disk memory, and also greatly increases the processing efficiency of the system. The system also includes a summarization program that is capable of directly summarizing the virtual data records piped into it from the data viewer program, thus eliminating the need for a time-consuming sorting process prior to summarization.

Abstract: The associative memory-based computer includes at least one associative memory, a plurality of associative data memories capable of temporarily holding input or output data of the associative memory, and a value judgement device receiving part of the data held in the associative data memory. The associative memory is formed of a chaotic neural network. The associative data memories include a first associative data memory sending/receiving data directly to/from the associative memory, and a plurality of second associative data memories sending/receiving data to/from the associative memory via the first associative data memory.

Abstract: An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

Abstract: An intelligent content addressable memory (CAM) cell for CIDR co-processors is disclosed. The CAM cell is operative to search and compare external data from an external search data key with stored data. The CAM cell comprises means for containing the stored data and means for enabling a mask prefix read path for a work matching the external search data key. Furthermore, the CAM cell includes means for merging a mask prefix pattern of all matching entries in order to generate a device longest prefix match. A comparison is made between the device longest prefix match and word mask prefix data in order to find the desired data.

Abstract: The present invention relates to a current conveyor circuit capable of operating at very low voltages, said circuit comprising: three LVCM's and four MOSFETS, wherein LVCM1 provides a constant bias current to flow through M3, if port X is kept open and the difference between the bias current and the injected current flows through M3 if a current is injected into port X, which gets reflected at port Z due to the action of LVCM1, M3 and M4, LVCM2 maintains the drain currents of M1 and M2 constant, and LVCM3 maintains a constant tail current in the circuit.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: An FPGA has an on-chip processor that reads configuration data onto the FPGA and controls the loading of that configuration data into FPGA configuration memory cells. After FPGA power-up, the processor reads a configuration mode code from predetermined terminals of the FPGA. If the configuration mode code has a first value, then the processor executes a first configuration program so that configuration data is received onto the FPGA in accordance with a first configuration mode. If the configuration mode code has a second value, then the processor executes a second configuration program so that configuration data is received onto the FPGA in accordance with a second configuration mode. The configuration programs can be stored in metal-mask ROM on-chip so they can be changed without re-laying out the remainder of the FPGA. Providing multiple configuration programs allows the FPGA to support multiple configuration modes using the same processor hardware.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A self-locking memory circuit for a tri state data bus having multiple bit lines. The circuit includes a non-inverting buffer chip for connection to each bit line and a resistor having a predetermined electrical resistance connected across the buffer chip. The chip and resistor provide a predetermined impedance to the flow of electrical current in the self-locking circuit. The circuit changes its state when the current of the latest information on a bit line builds or lowers above or below threshold levels of the self-locking circuit.

Abstract: A method for updating parametric data for use in data management system. The data management system includes a data storage device which includes a non-volatile memory device and a random access memory (RAM) device. The non-volatile memory device includes a transaction data storage device and a backup data storage device. When the requirements of a client device change, corresponding parameters stored in the RAM device can be changed and the changed parameters are written to the transaction data storage device. When the system restarts due to contingency, the contents of the backup data storage device are written to the RAM device, and then the corresponding parameters of the RAM device are updated according to the contents of the transaction data storage device. In this way, the contents of the RAM device can be restored to the parameters that was set before the system interruption.

Abstract: A flexible address mapping method and mechanism allows mapping regions of a microcontroller's memory and I/O address spaces for a variety of applications by defining memory regions which are mapped to one of a set of physical devices by a programmable address mapper controlled by a set of programmable address registers. The mapping allows setting attributes for a memory region to prohibit writes, caching, and code execution. A deterministic priority scheme allows memory regions to overlap, mapping addresses in overlapping regions to the device specified by the highest priority programmable address register.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their compliments are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their compliments to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their compliments to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: A scheme for managing nodes connected to a home network according to their physical location is disclosed. A communication device constituting each node is formed by at least one communication unit for carrying out communications through a connected network, having communication ports for connecting nodes through which data are to be exchanged by the nodes, and a configuration information memory unit for storing a configuration information regarding a configuration of the communication device, having a region for dynamically describing a location information regarding a physical location of the communication device.

Abstract: A method and apparatus provides random access to mainframe files that are accessed using an operating system that does not provide random access. This allows a computer system such as a mainframe on which random access is not supported to act as a file server for a computer system on which random access is supported without requiring the entire file to be downloaded to the client computer system.

Abstract: The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option, a bank selector encoder coupled to receive a memory partition indicator signal from the memory boundary option, and a bank selector decoder coupled to receive a bank selector code from the bank selector encoder. The decoder, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Abstract: The video game device which may display 2D images and pseudo 3D images without need to rewrite data in a frame buffer for a long time in a game. The frame buffer includes a display area storing images directly transferred to the monitor and a non-display area storing images used to produce the image transferred to the monitor. Only the changing parts of the images continuously displayed on the monitor are stored as small sized area in the non-display area and only the changing parts are put on the image to be displayed at a desired timing.

Abstract: File management method having first and second processing modes for storing file type information for discrimination between first and second processing modes in recording medium as file management information associated with file for file management. In first processing mode, when data in the form of file is written on a recording medium and a write error occurs, replacement processing to another write area is performed to write the data in another area. In second processing mode, when write error occurs, the replacement processing to other write area is not performed to write the data. Method includes reading file type information associated with a file to be processed from recording medium, converting the file type from file type indicative of first processing mode to file type indicative of second processing mode, and writing the file type after conversion in recording medium as file management information associated with the file to be processed.

Abstract: A memory repeater hub comprising a main memory channel interface circuit, an expansion control channel interface circuit, and an expansion memory channel interface circuit. The main memory channel interface circuit receives a memory control packet and a memory data packet from a main memory channel. The expansion control channel interface circuit receives a first expansion control packet and a second expansion control packet from an expansion control channel. The expansion memory channel interface circuit selectively transmits the memory control packet to an expansion memory channel responsive to the first expansion control packet, and selectively transmits the memory data packet to the expansion memory channel responsive to the second expansion control packet.

Abstract: The systems and methods described herein allow a user to perform localized searching from a standard web browser. In particular, the systems and methods of this invention use a two-prong approach to accomplish both a dynamic breadth-first crawl search and a contextualize index search to generate search results. The search results are then assembled in a unified results page and displayed to a user.

Abstract: A method for concurrent data migration includes classifying files to be migrated into plural jobs, selecting media to which to migrate each job, and using plural drives concurrently to write the jobs to the media. The selection of a medium is performed in a way that prevents the number of writeable media from exceeding the number of available drives, unless no allocated medium has sufficient space to store any files in a migration job. A medium is preferentially selected that has already been allocated for writing, has space to store at least one file in the job, is not in use for another job, and can be robotically mounted on a drive. If such a medium does not exist, then the set of available media is canvassed to locate an alternative medium.

Abstract: In a cluster of computing nodes having shared access to one or more file systems in data storage using parallel file system software, a method for managing the data storage includes initiating a session of a data management application on a first one of the nodes, while running a user application on a second one of the nodes. A request is submitted to the parallel file system software by the user application on the second node to mount one of the file systems in the data storage. A mount event message is sent from the second node to the first node responsive to the request, for processing by the data management application on the first node. When the file system is to be unmounted, preunmount and unmount events are sent for processing by the data management application on the first node.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: Systems, devices, structures, and methods are described that reduce energy consumption during a refresh cycle in a memory device. An isolation signal is held in a non-energized state until the it is determined that another action is to be performed on the section of memory associated with the isolation signal. The isolation accordingly cycles from an energized state to a non-energized state and back for each complete refresh cycle in the section of memory.

Abstract: In a virtual machine (VM) environment, a virtual machine ID (VMID) uniquely associated with a preferred virtual guest (222) is sent to a storage controller (108) along with requests to RESERVE or RELEASE a direct access storage device (DASD) (128). The VMID is used by the storage controller (108) along with a path group ID (PGID) to determine the scope of the RESERVE or RELEASE. Thus, preferred virtual guests (216) of a single host processor (112) may share the DASD while both preserving data integrity and operating with the performance benefits of Input/Output (I/O) Assist. Sharing is similarly provided for tape devices with requests to ASSIGN or UNASSIGN.

Abstract: A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

Abstract: A method for managing persistent storage in a memory storage system including a main memory and at least one disk memory device, in accordance with the invention, includes maintaining headers in persistent storage for a plurality of blocks wherein a header for each block includes a block size and an allocation status of the block and maintaining at least one data structure in main memory for allocating and deallocating persistent storage. A storage block is allocated by identifying the storage block by employing the at least one data structure in the main memory, modifying the at least one data structure in the main memory and assigning an allocation status for the block on disk. A storage block is deallocated by assigning an allocation status on disk for the block and modifying the at least one data structure in main memory.

Abstract: The present invention provides a conversion method for converting numeric multi-dimensional database dimension members to textual representations. The conversion is specifically designed to enable the textual representations of the numeric dimension members to be properly sorted and converted back into numeric representations with accuracy. All numeric and date data is transformed during conversion, such that the textual representation of the numeric and date data is properly sorted as a text string, in the same order as it would be sorted as a number. The present invention also provides a means for accurate reverse-conversion (i.e., from textual representation to numeric representation) by first converting into text the information necessary to support the precision required by the relevant convention of the numeric representation. The present invention also provides a convention for determining the data type of the textual representations of values of various data types.

Abstract: A data processing method for a digital camera that may record image data as image files and sound data as sound files on a storage medium, wherein sound files are classified into a sound memo file recorded in association with an image file, and a sound record file recorded independently. The image files and the sound record files are time-sequentially recorded in a recording directory on a storage medium, each being given a file-name that contains an individual file number representing the time sequence of recording. To discriminate between the image files and the sound files, an extender common to the image files or a second extender common to the sound files is attached to the file-name. The sound memo file is given the same file-name as that of an image file which the sound memo file is to be associated with, and is recorded in the same recording directory as the associated image file, though the extender common to the sound files is attached to the file-name of the sound memo file.

Abstract: A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline.

Abstract: A control unit that includes a processor having at least a first chip select output and a second chip select output. A signal provided by the first chip select output is activated during a normal operating mode of the control unit, and a signal provided by the second chip select output is activated during an application mode of the control unit. The control unit also includes a RAM memory having a chip select input for selecting the RAM memory and having a memory area for use as an application memory. A combination element electrically couples the signal provided by the first chip select output and the signal provided by the second chip select output to the chip select input of the RAM memory such that the signal provided by the first chip select output and the signal provided by the second chip select output do not have a perturbing effect on each other.

Abstract: A memory system (200) has an array of addressable storage elements (210) arranged in a plurality of rows and a plurality of columns, and decoding circuitry (220, 230) coupled to the array of addressable storage elements (210). The decoding circuitry (220, 230), in response to decoding a first address, accesses a first storage element of a first row of the plurality of rows, and, in response to decoding a second address consecutive to the first address, accesses a second storage element of a second row of the plurality of rows. The second row of the plurality of rows is different from the first row of the plurality of rows. By implementing a memory system wherein consecutive addresses correspond to storage elements of different rows, read disturb stresses along a single row can be minimized.

Abstract: A storage medium (computer readable medium) for recording information data in a protective manner such that an easy data processing can hardly succeed correct reproduction of information such as music information. A machine for creating data to be recorded in the storage medium and a machine for restoring the recorded data. Incomplete information data which is obtained by omitting some data in complete information data adapted to provided complete information is recorded in the storage medium. The data creation machine separates the complete information data into the incomplete information data and complementary information data, and writes the incomplete information data into the storage medium. The data restoration machine includes a first storage unit for recording the incomplete information data, and a second storage unit for recording the complementary information data which is the data omitted from the complete information data.

Abstract: An embodiment of the present invention includes a cache and a controller in a non uniform memory architecture (NUMA) system. The cache stores a plurality of entries, each of which contains an entry type indicating if the entry is one of a normal entry and a directory entry. The controller processes an access request from a processor for a memory block using the plurality of entries.

Abstract: A memory statistic counter and method for counting the number of accesses (writes or reads) by a microprocessor (10) to at least a portion of a memory comprising a decoding logic unit (16) for providing a selection signal for selecting the portion of memory in response to control signals from the microprocessor, and adding logic units (18, 20, 22). The memory statistic counter includes a register which is incremented each time the portion of memory is accessed by the microprocessor and providing a registration signal when the number of accesses is equal to a predetermined number, and a queuing unit (44) for registering a value in a registering memory (50), such as a first-in-first-out (FIFO) memory, in response to the registration signal and providing an interrupt signal to the microprocessor when all locations of the registering memory have been filled, thereby indicating to the microprocessor that a defined number of accesses to the portion of memory has occurred.

Abstract: Register file circuitry, for use in a processor or processor core, comprises a plurality of physical registers (320-32D-1) and a plurality of tag storing portions (340-34D-1) corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical registers.

Abstract: Disclosed is a system, which divides a memory into a plurality of equally-sized sub-memories and controls an address of each sub-memory, thereby significantly increasing the access speed to an auxiliary memory unit, which comprises a SCSI (Small Computer System Interface) interface controller for converting a SCSI interface bus into a PCI(Peripheral Component Interconnect Bus) interface bus for use in the system, a memory card module for storing data on the PCI interface bus therein, the memory card module being divided into a plurality of equally-sized memory blocks, and a CPU (Central Processing Unit) module for processing writing data on the PCI interface bus in the memory card module and reading out the data therefrom.

Abstract: The method is distinguished by the fact that an address, which is output by the first device or an address generating device connected downstream thereof, for determining the second device, and/or the association between the address and the device addressed as a result, and/or the data that are to be transferred are manipulated, during the transfer, in dependence on the address output by the first device or the address generating device connected downstream thereof.