Abstract: In an information distribution system that rates distribution information pieces from a distribution information provider based on a personal profile to distribute to a client where the personal profile has registered therewith various keywords contained in the distribution information pieces provided from the distribution information provider and evaluation values corresponding to the keywords and the evaluation values are learned in advance based on preferences of the client, distribution information pieces from another distribution information provider different from the distribution information provider are rated based on the personal profile to distribute to the client.

Abstract: The present invention is a system and method for content management that is operative to determine when a content page contains out of date content items as a result of changes made to the content items stored in a data source. The system comprises a template engine for executing templates to generate a content page, the template engine operative to generate a content page comprising content items selectively retrieved from a data source and arranged on the content page as defined by the template, each content item in the data source being associated with time stamp information to indicate the last time the content item was modified. One or more dependency records are generated to store information regarding the relationship between content items that comprise the content page and the content items stored in the data source.

Abstract: A technique includes providing a mapping table that indicates different rules for purging and/or archiving different database tables. Each rule is associated with a different database table. The rules are applied to purge and/or archive data from the different database tables.

Abstract: In a computer system having a processor, a system memory, a flash memory, and a memory controller, a method comprising the steps of loading a flash memory upgrade program containing a new flash memory image and a digital signature into a portion of the system memory; configuring the memory controller to limit the processor to accessing only the flash memory and the portion of the system memory; verifying the flash memory update program using the digital signature; and, updating the flash memory only if the flash memory upgrade program is authentic.

Abstract: Disclosed herein is a system and method for optimally designing automobile door seals. The system comprises data storage means, data management means and model design means. The data storage means consists of a plurality of storage units, each of which has data necessary for each condition. The data management means consists of a plurality of mode selection units for selecting a mode from the data storage means according to the characteristics of a door seal to be developed. The model design means designs a complete door seal by imposing a variety of conditions on a model selected from the data management means and performing various tests.

Abstract: A disk control apparatus includes a control circuit and a code conversion circuit. The control circuit analyzes read/write commands transmitted from a plurality of host computers using different coding schemes, and recognizes a code conversion mode which indicates execution/inexecution of code conversion and a code conversion direction. The code conversion circuit performs code conversion for data to be read/write from/in a plurality of disk storage units using different coding schemes.

Abstract: An application IF layer interprets and processes manipulations of an application program. A database IF layer interprets and processes manipulations common to a plurality of types of databases. Individual database manipulation implementation embedded in the database IF layer executes processes unique to databases for each of the plurality of types of databases.

Abstract: An information processing apparatus is constructed to include a storage unit, and a processing part which registers information of the information processing apparatus by transmitting to a first database of a registration center when a password input error is detected and stores transmission log information related to a transmission to the registration center into said storage unit.

Abstract: The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a select bit indicative of one of the first and the second storage elements. The decoder generates a select signal to access one of the first and the second storage elements based on the select bit.

Abstract: A method and system for automatic retrieval of a document linking to a starting document that has a static address on a data network. A sequence of commands that cause a browser in a computer system to navigate from a starting document to a target document on a data network is recorded. The recorded sequence of commands can be reproduced to cause the browser to navigate from the starting document through a sequence of intermediate documents to the refreshed version of the target document. More particularly, the invention allows retrieval of the target document even when the intermediate and the target documents are dynamically generated by a server computer and thus their online addresses change every time they are loaded.

Abstract: An information processing apparatus is constructed to include a judging part for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and a control part for carrying out a cache control when the judgement signal from the judging part indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request.

Abstract: A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.

Abstract: A portable digital audio device is capable of playing a number of different data file types, such as music data files, speech data files, video data files, and the like. Different CODECs are generally used for different data types. The system determines the data file type and selects the appropriate CODEC based on the reported data file type. In addition, the reported data file type is used to select the appropriate media interface manager and appropriate user interface. The user interface, or “skin” is selected for compatibility with the media interface manager and selected CODEC. The appropriate controls are enabled and displayed for user operation. As new CODECs are added to the system, appropriate media interface managers and skins are also added to provide the necessary user interface compatibility.

Abstract: An apparatus for and a method of non-linear constraint optimization in a storage system configuration. In accordance with the primary aspect of the present invention, the objective function for a storage system is determined, the workload units are selected and their standards are determined, and the storage devices are selected and their characteristics are determined. These selections and determinations are then used by a constraint based solver through non-linear constraint integer optimization to generate an assignment plan for the workload units to the storage devices.

Abstract: A semiconductor memory including a ferroelectric gate capacitor structure includes an insulating interlayer formed on the surface of a semiconductor substrate. The insulating interlayer includes a hole at a position corresponding to a channel region. In the channel length direction, the hole extends across the channel region. A ferroelectric gate capacitor structure is formed in the hole. The ferroelectric gate capacitor structure includes a dielectric film, ferroelectric film, and upper electrode formed in this order from the substrate side.

Abstract: Data is written into a circular buffer at an address pointed to by a write pointer. A number is written into the address with the data. Each time the circular buffer is traversed by the write pointer this number increments modulo a predetermined number. This number makes the circular buffer appear longer than it really is and can be used to identify underruns. The buffer has application in a segmentation and reassembly device for ATM constant bit rate services.

Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

Abstract: The invention relates to a method for implementing a functional memory and to a memory arrangement. The memory is implemented as a directory structure comprising a tree-shaped hierarchy having nodes at several different hierarchy levels. In the directory structure, pointers are first added to nodes whose table contains a given first number of elements and which are width-compressed nodes. To maximize the performance of the functional trie structure, addition of a pointer to an individual width-compressed node is permitted until the number of pointers in the node corresponds to a given predetermined threshold value that is smaller than said first number. The width-compressed node is converted to a cluster of nodes made up by a parent node (N50) and separate child nodes (N51 . . . N54) as soon as the number of pointers to be accommodated in the width-compressed node exceeds said threshold value.

Abstract: A method for transferring one or more files is disclosed. The files are transferred from a host peer to a target peer in which respective message digests are calculated for a file on a host peer and a target peer. A comparison between the calculated digests is made prior to transmission of a file in order to establish whether the target peer possesses the file in question. Where it is found that the message digests are identical, it is assumed that the file is present on the target peer. This can be done in the event that it is suspected that a file to be transferred may already exist on the target peer, for example if the target peer already possesses a file of the same name as that to be transferred. If it is discovered that message digests calculated by the host peer and the target peer are identical, the file is not transmitted by the host peer, thereby preventing an unnecessary use of available bandwidth.

Abstract: A one-chip system large-scale integrated circuit comprises: a storage circuit in which a program has been stored; a processor circuit for processing an operation in accordance with the program using a program counter, a computing unit and a register; and a peripheral circuit, capable of sending and receiving a signal to and from the processor circuit using at least one functional block, for carrying out a predetermined logical operation in accordance with an input signal.

Abstract: A power saving type information processing apparatus is provided which is not expensive and can provide a high interruption performance without using an expensive and dedicated memory and a complicated software process. After an SDRAM setting register of an SDRAM controller outputs a SELF allowance signal for allowing SDRAM to transfer to a power saving mode from a normal operation mode, a WAITI command fetch detecting circuit outputs a WAITI command detecting signal. In this case, SDRAM is made to transfer to the power saving mode. If a CPU detects an external interruption while SDRAM is in the power saving mode, SDRAM is returned to the normal operation mode irrespective of settings of the SDRAM setting register.

Abstract: An address generator is provided for generating addresses needed to read out data from a memory. The address generator includes a first and a second latch circuits, and a first counter connected to each of the first and the second latch circuits. The address generator also includes a first and a second storages each of which is connected to the first counter. The address generator further includes a second counter connected to each of the first and the second storages.

Abstract: An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

Abstract: During a compressing portion, memory (20) is divided into cache line blocks (500). Each cache line block is compressed and modified by replacing address destinations of address indirection instructions with compressed address destinations. Each cache line block is modified to have a flow indirection instruction as the last instruction in each cache line. The compressed cache line blocks (500) are stored in a memory (858). During a decompression portion, a cache line (500) is accessed based on an instruction pointer (902) value. The cache line is decompressed and stored in cache. The cache tag is determined based on the instruction pointer (902) value.

Abstract: A memory device comprising an n-channel transistor and p-channel transistor, both transistors having a source, a drain and a gate, the source and drains of the transistors being connected in series and the gates of the transistors being connected together, with each transistor having a ferroelectric material separating the gate from the source and drain thereof. Preferably a single ferroelectric material acts as the ferroelectric material for both transistors and a single gate acts as the gate for both transistors. Beneficially the device comprises a single substrate having an n-type source, an n-type drain, a p-type source and a p-type drain formed in a surface thereof and a single area of the substrate which separates all of these regions from each other has intrinsic doping only. The invention also relates to a method of manufacturing such memory devices.

Abstract: An object of the invention, in a semiconductor circuit or, more particularly, in an LSI on which a DRAM and a logic circuit are merged, is to decrease the frequency of times of refreshing operations to thereby achieve both reduction in power consumption and prevention of deterioration in the performance of the logic circuit caused by an increase in the memory access time due to contention between refresh and DRAM access of the logic circuit.

Abstract: Disclosed is an information processing apparatus which ends application programs when a recording medium is pulled out. In step S1, it is determined whether or not a Memory Stick is loaded in a Memory Stick slot. If a Memory Stick is found loaded, the procedure goes to step S2. In step S2, a display program and a reading program are started. In step S3, it is determined whether or not the loaded Memory Stick is being accessed. If the loaded Memory Stick is found being accessed, then, in step S4, the Memory Stick is locked. In step S6, if the Memory Stick is found pulled out, then, in step S7, the display program and the reading program are ended.

Abstract: A non-volatile memory system having a memory controller, an array of memory cells and a memory operation manager. The operation manager carries out memory program, read and erase operation upon receipt of program, read and erase instruction from the controller, typically over a system bus. The address block circuitry is provided in the manager which is capable of performing an memory operation on a single address or on multiple addresses depending upon the state of the address block circuitry as determined by the controller. Multiple addresses can be generated based upon a single address provided by the controller so that sectors of the memory can be programmed or read thereby simplifying memory operations and reducing the overhead of the memory controller.

Abstract: A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-sector basis) rather than renaming an entire processor register. A register is divided into sectors such that the smallest accessible unit for an instruction in each register can be uniquely addressed and renamed. A register file is divided into sectors so that each process register can be uniquely addressed and renamed. The most significant sectors of the processor registers are used to hold pre-assigned values therein. Data previously loaded into processor register sectors is stored in the most significant sectors of the processor registers for possible future referencing and use. The method also includes establishing a sign-extend memory that includes at least one sign-extend bit in a sector status table.

Abstract: A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for controlling access to the memory; and at least one data buffer for buffering data to be written to or read from the memory. A burst controller is provided for issuing burst instructions to the memory access controller, and the memory access controller is responsive to such a burst instruction to transfer a plurality of data words between the memory and the data buffer in a single memory transaction. A burst instruction queue is provided so that such a burst instruction can be made available for execution by the memory access controller immediately after a preceding burst instruction has been executed.

Abstract: An apparatus for reproducing digital signals recorded on a disk having first and second recording surfaces. The digital signals are in the form of a data frame including a lead-in block and n data blocks. The lead-in block has a same format as the n data blocks. n block addresses are assigned to the n data blocks. Information identifying an area on the disk in which the n data blocks is recorded is assigned to the n data blocks. m data blocks (0<m<n) are recorded on the first recording surface, and remaining (n−m) data blocks are recorded on the second recording surface. The lead-in block is recorded at the head of the data frame, and includes information identifying an area on the disk in which the lead-in block is recorded, a number of recording surfaces, the block address of one of the m data blocks recorded last on the first recording surface, and the block address of a last one of the n data blocks in the data frame.

Abstract: A data storage managing apparatus is described which translates a host Input/Output (I/O) request into a standard form. Thus, I/O requests sent by different hosts using different protocols are treated in the same manner for accessing the data storage. The I/O request in the standard form is then normalized by adding a storage address. The normalized request is routed based on the storage address. Therefore, the present invention enables transparent communication between various types of hosts and various types of storage devices.

Abstract: A device generally comprising a memory array and a burst sequence generator. The memory array may be configured to store data. The burst sequence generator may be configured to generate a burst sequence in response to address information received by the device. The burst sequence may be configured to identify a plurality of locations for storing data in the memory array. The device may have a maximum operating current of 50 milliamps and/or a maximum standby current of about 25 microamps.

Abstract: A method and computer-readable medium for managing memory for complex objects returned from procedure calls are described. Memory for complex objects returned from procedure calls is allotted from memory pools, which are allocated on a “per-call” basis for complex objects. Complex objects allotted from different memory pools can have overlapping lifetimes. The memory used by the complex object is straightforwardly released by deallocating the memory pool. In one aspect, the memory management of complex objects is located in the called procedures, which may be an automatically generated client stub routine for a remote procedure call.

Abstract: The invention relates to a method of managing files. In this invention, a method of managing a file stored in an external memory device of a computer having an application that starts when it is read by the computer consists of a step of accepting an instruction for starting up the application, and a step of automatically deleting the application program from the external memory device when the started application terminates. This file managing method can automatically delete the application program from the external memory device when the started application terminates.

Abstract: A storage unit comprises a plurality of storage modules, each of which is dynamically assigned to and used as each area in a main storage (MS) or an extended storage (ES). The storage unit or a system controller has address arrays for MS and for ES which store information indicating which of the storage modules comprised in the storage unit each area in the MS and the ES corresponds to. When the contents of the MS/ES address arrays are rewritten to change a storage module belonging to the ES to a storage module belonging to the MS, a page-in operation is realized without executing an actual data move operation. Similarly, a page-out operation is realized without executing an actual data move operation by changing a storage module belonging to the MS to a storage module belonging to the ES.

Abstract: An optical disk reproducing apparatus for reproducing digital signals in the form of a data frame including a lead-in block and data blocks from an optical disk including at least first and second recording surfaces each being readable from a same side of the optical disk. The data blocks include block addresses and data, and are recorded on the first and second recording surfaces. The lead-in block is recorded at a head of the data frame and includes disk information relating to a number of data blocks recorded on the first and second recording surfaces.

Abstract: A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.

Abstract: A computer system or computer system main memory is provided. The computer system includes a secondary memory and a buffer. The buffer is one having a faster access time than the secondary memory, and data placed within the buffer can be controlled by a control block configured with a control field and a byte count value of data bytes transferred during a DMA cycle, or a chain of DMA cycles. A counter may be used to increment the byte count within one or more control blocks during transfer of data bytes from secondary memory to the buffer. A requester is coupled to forward a read request that is serviced from the buffer if an address of the read request is included within an address incremented by the byte count. Both the control blocks and the buffer can be contained within a main memory local to the requester.

Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: Systems and methods consistent with the invention write and read data cells to and from a bank of cell buffer memories. The system includes a plurality of memory units for storing data cells. An address memory outputs a memory address and a memory selecting unit selects one of the plurality of memory units based on the outputted memory address. The system then performs a read or write operation at the outputted memory address of the selected memory unit. The system may write data cells to one memory unit while at the same time reading data cells from one of the other memory units.

Abstract: A system for accessing control and status registers for a device within a computer system. These control and status registers are used to control and configure the device and to read status information from the device. The system operates by serially shifting an index into an index register within the device. This index specifies a target register to be accessed within the control and status registers. During a write operation to the target register, the system serially shifts a data value into a data register within the device, and then moves the data value from the data register into the target register. During a read operation from the target register, the system loads a value into the data register from the target register, and serially shifts the value from the data register to a location outside the device to complete the read operation.

Abstract: A memory control unit is coupled during use to a system bus for receiving memory addresses therefrom. The memory control unit is further coupled during use to one or more memory units by a second bus that includes a plurality of signal lines for transmitting, during a memory access cycle, a memory address to the one or more memory units. Each of the one or more memory units includes a plurality of semiconductor memory devices having a plurality of addressable memory storage locations. The memory control unit further includes circuitry that is coupled to and responsive to a signal asserted on the second bus by one of the memory units selected by the transmitted memory address. The asserted signal indicates an access speed of the selected memory unit, and specifies a duration of the memory access on an access-by-access basis so as to make a duration of the memory access cycle compatible with the access speed of at least the semiconductor memory devices of the selected memory unit.

Abstract: A cache memory is provided with a tag memory for storing tag information and a column switch having an XOR calculation functions XOR calculation for judging whether the tag information and an address match is performed on every bit on a signal having a small amplitude on a bit line, and a high speed logic calculation can be realized, thus, there is an advantage that a cache memory capable of attaining a shorter access time can be realized.

Abstract: A method and apparatus for processing pipelined command packets in a packetized memory device. The command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution. The command units each include a latch for storing a command packet, a counter, and a start command generator. The counter is preloaded with a count corresponding to the timing that the command is received at a location within the memory device. The counter begins counting responsive to a flag bit received with the command packet. The start command generator receives the count of the counter, and decodes different counts depending on the type of command (e.g., a “read” or a “write”) and the speed of a clock signal that is used to control the operation of the memory device. When the start command generator decodes a count, it latches command bits of the applied command packet and generates a start command signal.

Abstract: A method and system for re-using special purpose registers as general purpose registers utilized a special variable type to indicate that a variable may safely be stored in a special purpose register. A loader program maintains the table indicating the availability of special purpose registers for variable storage and loads a variable of the special type to an available special purpose register.

Abstract: A flexible magnetic disk drive is disclosed which is linked to a computer via a universal serial bus interface having firmware held on a read-only memory. In order to facilitate the upgrading of the firmware, an electrically erasable, programmable ROM is employed for firmware storage. Each new firmware version is issued in the form of a flexible magnetic disk which may be loaded in the disk drive just like an ordinary data disk, only with the disk drive disconnected from the computer as far as data transmission is concerned. The EEPROM is preprogrammed to identify the loaded firmware disk, erase the old firmware version on the ROM, and write the new version thereon. In another embodiment a self-testing program disk is employed in place of the firmware disk, for performing a set of tests on the disk drive including the interface. The tests are conducted automatically as the self-testing program disk is loaded in the disk drive, again with the disk drive disconnected from the computer.

Abstract: A memory management system for random access memories employs a novel B-tree structure to map physical memory locations to logical addresses. In the preferred arrangement each key in the tree structure contains the physical address corresponding to the logical address identifying the key and also contains the size of the data block at that address. The invention also provides a novel arrangement for updating B-trees in response to changes in the keys. The tree buckets containing modified keys are recorded in storage locations other than the locations containing the keys prior to modification. Thus, until the modification of the tree is complete, the system contains a record of the entire tree structure prior to the beginning of the modification.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more “planes.” Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.