Abstract: A volume migration method for causing to carry out a migration from a first volume manager to a second volume, includes: by causing the first volume manager to carry out actual accesses, obtaining information of correspondence, by the first volume manager, between logical volume offsets and physical blocks on a physical medium; judging, based on the obtained information of the correspondence, whether or not an exceptional data layout is carried out; and when it is judged that the exceptional data layout is not carried out, updating only a header area on the physical medium for the second volume manager. Incidentally, the aforementioned obtaining is carried out by using a program module for blocking access by the first volume manager to the physical medium. Thus, when only the header area is updated after it is confirmed the exceptional data layout is not made, the high-speed volume migration becomes possible.

Abstract: A data stream dispatching method for a memory storage apparatus having a non-volatile memory module and a smart card chip is provided. The method includes configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses is used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit into a buffer memory. The method further includes when a logical block address corresponding to a read command issued by a host system is one of the specific logical block addresses and the response data unit is stored in the buffer memory, transmitting the response data unit to the host system by aligning an access unit. Thereby, the host system can correctly receive the response data unit from the smart card chip.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method includes receiving an identifier, receiving output from a command line utility, and storing the command line utility output in a system storage at a location identified by the identifier. In one illustrative embodiment, command line utility output is stored in a system registry database. In another illustrative embodiment, command line utility output is stored in a shared system memory. The method may be stored in any media that is readable and executable by a computer system.

Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Abstract: A system, a controller, and a method for transmitting and distributing a data stream from a host to a storage device having a non-volatile memory and a chip are provided. A specific mark is added into a data stream which is transmitted from the host to the storage device, such that the data stream can be dispatched to the chip by transmitting a write command. Then, a response message generated by the chip can be received inerrably by executing a plurality of read commands.

Abstract: Herein disclosed a data delivery system including an information processing apparatus and a terminal apparatus. The terminal apparatus has a first attachment unit, a first writing unit, a first reading unit, a decoding unit, a storage unit, and a first control unit. The information processing apparatus has a second attachment unit, a second writing unit, a second reading unit, and a second control unit.

Abstract: A cold boot test system and method can control an electronic device to perform a cold boot process to test whether the electronic device is operable. The method sets time parameters for a test period of the cold boot process, drives a data communication interface of a computer to generate a period control signal according to the time parameters, and sends the period control signal to a controller via the data communication interface. The method further transfers the period control signal to the electronic device by controlling a power switch to switch on and switch off, controls the electronic device to execute the cold boot process to generate test information correspondingly. In addition, the method obtains the test information from the electronic device, and displays the test information on a display screen of the computer upon the condition that the cold boot process is abnormal.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: Embodiments of the present technical solution relate to the technique field of storage, and disclose a server and a method for the server to access a volume. The method comprises: determining, from a first list, a block that needs to be accessed according to an access offset of a volume that needs to be accessed; determining, from a second list, a storage controller corresponding to the block that needs to be accessed according to the determined block; and sending a data reading request or a data writing request to the storage controller corresponding to the block that needs to be accessed to process. Embodiments of the present invention can reduce time delay when the data reading request or the data writing request of the server reaches the block that needs to be accessed.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.

Abstract: An approach is provided to identifying cache extension sizes that correspond to different partitions that are running on a computer system. The approach extends a first hardware cache associated with a first processing core that is included in the processor's silicon substrate with a first memory allocation from a system memory area, with the system memory area being external to the silicon substrate and the first memory allocation corresponding to one of the plurality of cache extension sizes that corresponds to one of the partitions that is running on the computer system. The approach further extends a second hardware cache associated with a second processing core also included in the processor's silicon substrate with a second memory allocation from the system memory area with the second memory allocation corresponding to another of the cache extension sizes that corresponds to a different partitions that is being executed by the second processing core.

Abstract: According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-be-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register.

Abstract: A method and system for identifying a NAND-Flash without reading a device ID. The method includes: executing an identification flow for setting a first page of a block as a target block, utilizing a combinations table to query a target block, evaluating a result by comparing a identifying information in the target block with the combinations table, trying all combinations in the combinations table until correctly identifying the NAND-Flash by having a positive match result or returning an error if none of the combinations match.

Abstract: A method, apparatus and system enable offloading of encryption on partitioned platforms. More specifically, a partitioned platform may include a user partition for user applications, including a Virtual Private Network (“VPN”) application capable to creating a VPN connection for secure packet transmission. The partitioned platform may additionally comprise a dedicated partition including security agents to examine packets transmitted to/received by the dedicated partition. The dedicated partition may be assigned the Network Interface Card (“NIC”) on the host, i.e., all network traffic coming into or leaving the platform may be routed via the dedicated partition. In one embodiment of the invention, a driver in the user partition may offload cryptographic tasks to the dedicated partition, where clear packets may be examined by security agents, then encrypted prior to transmission.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.

Abstract: A system, apparatus, and method dynamically manages logical path resources by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.

Abstract: Example embodiments for providing enhanced addressability for a serial flash memory device may comprise providing an extended addressing mode to enable access to a larger range of memory locations.

Abstract: A system including a plurality of NAND flash memory devices each having a NAND flash interface, where the NAND flash interface of each NAND flash memory device includes an 8-bit data bus, and a memory controller configured to exchange data with the plurality of NAND flash memory devices via the 8-bit data bus. The memory controller is further configured to select a first NAND flash memory device of the plurality of NAND flash memory devices, without using a Chip Enable signal of the NAND flash interface, by transmitting, on the 8-bit data bus, an identification byte identifying the first NAND flash memory device. The memory controller is further configured to transmit, on the 8-bit data bus, a command byte to the first NAND flash memory device. The first NAND flash memory device is configured to perform an operation indicated by the command byte.

Abstract: In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed.

Abstract: A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.

Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed.

Abstract: A method of managing memory storage space and a computer system using the same uses a computer including a storage device and an expansion slot. The method has the steps of: detecting whether there is a memory card in the expansion slot; combining the storage space of the storage device and the memory card to form a combined storage space; and using application software to manage the combined storage space. At least one file stored in the combined storage space may be selected to move between the storage device and the memory card via the application software.

Abstract: A method to speed up access to an external storage device for accessing to the external storage device comprises the steps of: (a) during startup of a computer, setting up part of a physical memory of the computer as a cache memory for use by the external storage device, in the form of a continuous physical memory area outside the physical memory area that is managed by an operating system of the computer; (b) upon detection of a request to write data to the external storage device, writing the data to the cache memory; and (c) sending the data written in the cache memory to the external storage device to be saved therein.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: A storage device includes a drive selection section (1), a hard disk drive (HDD) (2), and a non-volatile memory drive (3). When an instruction such as a data I/O instruction is issued from a host such as a CPU (5) and an ATA controller (6) to the hard disk drive (HDD) (2), the drive selection section (1) receives the address value. If the address value is included in the address space predefined, the non-volatile memory drive (3) is made to execute the instruction. Otherwise, the hard disk drive (HDD) (2) is made to execute the instruction.

Abstract: A method for storing files in a storage device includes the following steps. The storage device is divided into an original partition and a system partition. A plurality of original files is installed in the original partition. A shortcut is established in the system partition pointing to a first original file of the original files. The first original file can be executed by activating the shortcut.

Abstract: Provided are systems and methods to communicate data transfer of data between a disk device and an external storage device. A host can generate a control command to communicate with an external storage device, and a disk device to receive the control command from a host to identify and communicate with an external storage device when connected to the external storage device and to configure the external storage device by assigning an ID code to each storage area of the external storage device.

Abstract: An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by the central processing unit, and a unit that is selected from a plurality of units. An identification signal generating unit generates identification data indicating a type of the unit. An exclusive OR unit allocates an exclusive OR data of an address data for the central processing unit to access the memory and the identification data to the memory.

Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A migration destination storage creates an expansion device for virtualizing a migration source logical unit. A host computer accesses an external volume by way of an access path of a migration destination logical unit, a migration destination storage, a migration source storage, and an external volume. After destaging all dirty data accumulated in the disk cache of the migration source storage to the external volume, an expansion device for virtualizing the external volume is mapped to the migration destination logical unit.

Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

Abstract: An approach is provided for providing persistent computations. A persistent computation manager determines at least one non-volatile memory space of a device. The persistent computation manager also determines at least one other non-volatile memory space of at least one other device. The persistent computation manager further determines to form a persistent memory address space based, at least in part, on the at least one non-volatile memory space and the at least one other non-volatile memory space.

Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.

Abstract: Disclosed is a method and a SAS controller device that abstract access from one or more virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller (i.e., unique for the SAS controller such that other replicates/clones on other virtual ports have a different SAS address).

Abstract: An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

Abstract: In a personal computing system function calls, formatted in 16-bit format for a 16-bit interface to the firmware, are communicated through an operating system providing a System Management Interrupt (SMI) interface to the firmware. An SMI function call in SMI format is generated and sent to an SMI Interface Wrapper module between the operating system and the firmware. The SMI function call is received over the SMI interface at the SMI Interface Wrapper. In the SMI Interface Wrapper, function data from the SMI function call is extracted to provide function call data. A 16-bit function call with the function call data is generated by the SMI Interface Wrapper and passed to the firmware.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table used by the virtualization software wherein at least a portion of the guest page table and the shadow page table share computer memory; wherein: machine pages have a predetermined size; and the virtualization software maps guest OS physical pages to machine pages at a predetermined alignment.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A registered dual in-line memory module is configured with multiple random access memory chips and a DRAM register configured to receive address and control signals from a memory controller. The DRAM register distributes the address and control signals to the random access memory chips, thereby providing the memory controller access to the chips. The module further includes a control register configured to store control bits for setting operating modes of the registered dual in-line memory module. The control bits are software programmable using signals received from the memory controller.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: It is recognized that an attached USB memory is an unanalyzable USB memory. Then, disconnect setting is made. A USB connection process is performed. A PC is instructed through a connection line to establish USB connection. The PC recognizes that the attached device is a USB-connected MFP. The PC acquires data control information of the MFP. The MFP then transfers, through the connection line, the data control information output from the USB memory.

Abstract: A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.