Abstract: A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.

Abstract: Provided are methods and systems for providing users with a cluster of virtual machines (VMs) on-demand, whereby a group of VMs are provisioned together. Virtual Cluster as a Service (VClaaS) relaxes many restrictions on virtualizing VMs and provides performance benefits at the same or similar encapsulations and security measures that Infrastructure as a Service (IaaS) typically provides. The VClaaS system enables users to provision an entire cluster of VMs at a time, and also allows for relaxing the isolation barrier between the machines while maintaining the encapsulation barrier for the cluster as a whole, thereby providing users with improved networking, caching, and scheduling experiences.

Abstract: A method for communication between two clients via a server in a network using OPC Unified Architecture (OPC-UA), wherein a virtual server object that provides a server functionality to a first of two clients is implemented in the server by making available to the first client a virtual address space in an address space of the server, and a process for generating and modifying virtual server nodes in said virtual address space. The server allows the second client to access virtual server nodes in the virtual address space and informs the first client each time that the second client accesses a virtual server node in the virtual address space.

Abstract: Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.

Abstract: A storage device includes a primary storage extension chip, a plurality of secondary storage extension chips, and a plurality of resistors. Each of the storage extension chips includes two data pins, a plurality of general purpose input/output (GPIO) pins, and a firmware. Each of the GPIO pins is connected to a power terminal through one resistor, and is grounded through a resistor, for setting a firmware version number of storage extension chips. The primary storage extension chip determines whether the version number of each secondary storage extension chip is same as that of the primary storage extension chip. If the version number is different from that of the primary storage extension chip, the firmware version number of the primary storage extension chip is applied to the secondary storage extension chip.

Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.

Abstract: A method, computer-readable storage medium and computer system for controlling a storage system, the storage system comprising a plurality of logical storage volumes, the method comprising: monitoring, for each of the logical storage volumes, one or more load parameters; receiving, for each of the logical storage volumes, one or more load parameter threshold values; comparing, for each of the logical storage volumes, the first load parameter values of said logical storage volume with the corresponding one or more load parameter threshold values; in case at least one of the first load parameter values of one of the logical storage volumes violates the load parameter threshold value it is compared with, automatically executing a corrective action.

Abstract: Methods, apparatuses, and systems for allowing a single-die preamp to act as two or more virtual preamps for reading or writing data through multiple heads or elements concurrently. A selection register of a preamplifier is set to enable access to a primary register map. Values of registers in the primary register map are set to program a primary preamp channel for performing read or write operations to a first head. The selection register is then set to enable access to a secondary register map, and values of registers in the secondary register map are set to program a secondary preamp channel for performing read or write operations to a second head. Read or write operations can be performed to the first head through the primary preamp channel at a same time that read or write operations are performed to the second head through the second preamp channel.

Abstract: A method, system, and computer program product to verify serialization of storage frames within an address space via multi-threaded programs is described. The method includes dynamically scaling a number of units of work based on a number of available processors, each of the units of work configured to execute actions, and dynamically scaling an amount and page size of virtual storage accessed by each of the units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage pages and accessing storage pages corresponding with the respective different types of virtual storage pages associated with the different frame sizes and attributes and performing a respective action, and verifying, for each of the units of work performing the respective action, a state and data content of the storage pages.

Abstract: A disclosed method includes: specifying an activity to be executed, based on process definition that includes plural activities, and that includes a sequence of transitions between activities, wherein each activity includes information representing a device that is operated through a network; first determining, based on the sequence of the transitions, whether or not the specified activity is an initial operation for a certain device whose information is included in the specified activity; and obtaining an access right to the certain device, when determining that the specified activity is the initial operation for the certain device.

Abstract: Resources of an address space are managed in dynamically sized ranges, extents, sets, and/or blocks. The address space may be divided into regions, each corresponding to a different, respective allocation granularity. Allocating a block within a first region of the address space may comprise allocating a particular number of logical addresses (e.g., a particular range, set, and/or block of addresses), and allocating a block within a different region may comprise allocating a different number of logical addresses. The regions may be configured to reduce the metadata overhead needed to identify free address blocks (and/or maintain address block allocations), while facilitating efficient use of the address space for differently sized data structures.

Abstract: A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.

Abstract: A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.

Abstract: Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates.

Abstract: Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.

Abstract: An aspect of the invention is directed to a storage management computer for managing offloading of storage workload between a storage controller of a storage system and one or more host computers. The storage management computer comprises: a memory; and a controller operable to request a virtual machine management computer to register the storage controller as a host computer, and to send, to the virtual machine management computer, storage processes information of storage processes in the storage system which can be offloaded as virtual machines in order for the virtual machine management computer to register the storage processes as virtual machines.

Abstract: A path is formed between a host computer and storage apparatuses without depending on the configuration of the host computer and a network and a plurality of volumes having a copy function are migrated between storage apparatuses while keeping the latest data.

Abstract: A disk drive is disclosed that utilizes sorted serpentine mapping of data tracks. In one embodiment, a plurality of physical heads of the disk drive is mapped to a plurality of logical heads. The plurality of logical heads is sorted according to the respective data rates of the physical heads, such as in the order of decreasing data rates. Data tracks are mapped using sorted serpentine mapping that utilizes the sorted order of the logical heads. Improved performance can thereby be attained.

Abstract: A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.

Abstract: A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.

Abstract: The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite.

Abstract: This disclosure proposes techniques for demand paging for an IO device (e.g., a GPU) that utilize pre-fetch and pre-back notification event signaling to reduce latency associated with demand paging. Page faults are limited by performing the demand paging operations prior to the IO device actually requesting unbacked memory.

Abstract: Contiguous regions of physical memory may be reserved for user-space programs through a boot time parameter that specifically identifies the memory region to be reserved. In an implementation, the boot time parameter includes first and second values that are used to define a starting and ending address of the memory region to be reserved. The reserved memory is accessible by the operating system kernel storage and networking stacks so that the user-space programs can use services provided by the kernel storage and networking stacks.

Abstract: For efficient issue of a superscalar instruction a circuit is employed which retrieves an instruction of each instruction code type other than a prefix based on a determination result of decoders for determining instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant. When an instruction of a target code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target code type as prefix code candidates. When an instruction of a target code type cannot be detected at the rear end of the instruction units, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.

Abstract: A system, method, and computer program product for providing validation of the compliance of a trusted host environment with a requirement of a virtual machine (VM). The system includes: a store component for cryptographically storing configuration data associated with the trusted host environment in at least one cryptographic data structure; a send component, responsive to the store component storing the configuration data, for sending the at least one cryptographic data structure to a control component; an analyze component, responsive to the control component receiving the at least one cryptographic data structure, for analyzing the at least one cryptographic data structure; a compare component, responsive to the analyze component determining the configuration data, for comparing the configuration data with the requirement; and a verify component, responsive to the compare component determining that the configuration data matches the requirement, for allowing verification of the VM.

Abstract: An electronic apparatus is disclosed. The electronic apparatus comprises a random access memory (RAM), a read-only memory (ROM) and a processing unit. The RAM stores a call transfer table, wherein the call transfer table comprising at least one transferred address in the RAM. The ROM stores at least one code to call one address of the call transfer table. The processing unit executes the code in the ROM and reads the transfer table accordingly, then transfers to run the data in the transferred address of the RAM.

Abstract: A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip.

Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.

Abstract: A system on a chip (SOC) includes a master module, a first swapping module, and a switch module. The master module is configured to generate a transaction request, the transaction request including an address field including an address, the address corresponding to a first slave module associated with the transaction request, and a plurality of interface select bits corresponding to a desired one of a plurality of ports of the first slave module. The first swapping module is configured to swap, in the transaction request, the plurality of interface select bits with selected bits of the address in the address field. The switch module is configured to route the transaction request to the desired one of the plurality of ports based on the address.

Abstract: Various embodiments for managing data in a computing storage environment by a processor device are provided. In one such embodiment, by way of example only, an extender storage pool system is configured for at least one of a source and a target storage pool to expand an available storage capacity for the at least one of the source and the target storage pool. A most recent snapshot of the data is sent to the extender storage pool system. The most recent snapshot of the data is stored on the extender storage pool system as a last replicated snapshot of the data.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Abstract: Disclosed is a method and apparatus for a storage system comprising at least one mobile random access storage device capable of storing first or second data. At least one docking station is associated with an address wherein the address is identifiable by at least one host computer. A first and second sub-address is associated with the at least one docking station wherein the first and second sub-addresses are identifiable by the at least one host computer. The first sub-address corresponds to a first virtual device adapted for storing the first data on a first virtual media. The second sub-address corresponds to a second virtual device adapted for storing the second data on a second virtual media wherein the second virtual media is a different media type from the first virtual media.

Abstract: In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable circuit module is configured to receive, from a host device, information associated with a search request. The reprogrammable circuit module is configured to change from a first configuration to a second configuration in response to receiving the information. The reprogrammable circuit module is configured to retrieve at least a portion of the data stored at the set of memory modules associated with the second configuration. The reprogrammable circuit module is configured to generate a search result based on the portion of the data, and transmit the search result to the host device.

Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. A logical block address (LBA) is mapped to a data sector on the disk. During a bias interval following the start of a host boot operation, a biased migration policy is executed that increases a likelihood of migrating the LBA to the NVSM. After the bias interval a normal migration policy is executed.

Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.

Abstract: An automation device comprising a first functional unit, a second functional unit, a first network connection for connection to a first data network and a bus master unit for connecting a peripheral component. The first functional unit includes a first interface unit that is assigned a first network address, and the second functional unit includes a second interface unit that is assigned a second network address. A partitioning device can be used to logically partition an address space of the peripheral component, and a first address space can be directly assigned, as a partitioned part of the address space, to a superordinate computation unit that can be connected through the first network connection.

Abstract: System, apparatus, and methods for dynamically managing logical path resources are provided. The logical path resources are managed by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.

Abstract: A method for performing direct memory access includes obtaining, by a application executing on a host, a kernel address space identifier of a first driver kernel memory. The application sends the kernel address space identifier to a second device driver. The second device driver obtains, using the kernel address space identifier, a cookie structure binding the first driver kernel memory to a second device driver address space for the first driver kernel memory. The application sends a request for a direct memory access operation. The request includes a location identifier of a location storing a data object in the first driver kernel memory. Based on the cookie structure, the second device driver performs, using the location identifier, the direct memory access operation to transfer the data object from the first driver kernel memory to a second driver kernel memory.

Abstract: To provide a technology of increasing the number of ranks of a memory module with a small change in architecture. A memory control device accessing a memory module having a plurality of ranks, includes an interface unit having selection signal lines via which to flow selection signals for selecting the ranks and address signal lines via which to flow address signals specifying addresses on the rank, and a control unit transmitting the signal for selecting the rank via part of the address signal line and via the selection signal line.

Abstract: Various embodiments for managing data in a computing storage environment by a processor device are provided. In one such embodiment, by way of example only, an extender storage pool system is configured for at least one of a source and a target storage pool to expand an available storage capacity for the at least one of the source and the target storage pool. A most recent snapshot of the data is sent to the extender storage pool system. The most recent snapshot of the data is stored on the extender storage pool system as a last replicated snapshot of the data.

Abstract: According to one aspect of the present disclosure, a method and technique for using processor registers for extending a cache structure is disclosed. The method includes identifying a register of a processor, identifying a cache to extend, allocating the register as an extension of the cache, and setting an address of the register as corresponding to an address space in the cache.

Abstract: Machine-readable media, methods, apparatus and system are described. In some embodiments, a virtual machine monitor of a computer platform may comprise a service virtual machine created by the virtual machine monitor partitioning an underlying hardware machine to support execution of a plurality of overlying guest operating systems, wherein the plurality of guest operating systems comprise a guest operating system complying with a non-native guest system architecture different from a host system architecture with which the hardware machine complies. The service virtual machine may further comprise a translation layer to translate instructions from the guest operating system complying with the non-native guest system architecture into instructions complying with the host system architecture.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: According to an aspect of an embodiment, a disk drive diagnosis apparatus is included in a RAID system in which a RAID control unit and a drive enclosure that encloses a disk drive are interconnected via a fabric switch. The apparatus comprises a virtual login processing unit configured to virtually execute a login process for a fabric switch of a disk drive and a control unit configured to notify the RAID control unit of a result of the virtual login process and disconnect from a connection line for the RAID control unit a disk drive that has not normally performed the virtual login process relative to the drive enclosure.

Abstract: In one of the storage control apparatuses in the remote copy system which performs asynchronous remote copy between the storage control apparatuses, virtual logical volumes complying with Thin Provisioning are adopted as journal volumes to which journals are written. The controller in the one of the storage control apparatuses assigns a smaller actual area based on the storage apparatus than in case of assignment to the entire area of the journal volume, and adds a journal to the assigned actual area. If a new journal cannot be added, the controller performs wraparound, that is, overwrites the oldest journal in the assigned actual area by the new journal.

Abstract: A network storage system may receive the contents of a storage device attached to a client device to the network storage system. The network storage system may then redirect access to the contents of the client device to the network storage system. The storage device may then be removed or repurposed. Storage device management may be performed by the client device or the network storage system. A policy may be used to define under what circumstances the contents of a storage device may be moved to a network storage system, or data movement may be initiated by a user. Any access permissions or other metadata associated with files on the original storage device can be preserved.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.

Abstract: A memory compiler to generate a set of memories is based on a subtraction approach from a set of templates (memory templates), including at least one layout database and auxiliary design databases, by software. The software can be based on general-purpose programming language or a layout-specific language. The compiled memories can be generated by reducing the memory array sizes in row and/or column directions by moving, deleting, adding, sizing, or stretching the layout objects, and disabling the high order addresses, etc. from the memory template by software. The new auxiliary design databases, such as layout phantom, behavior model, synthesis view, placement-and-routing view or datasheet, can also be generated by modifying some parameters from the memory template by software. One-time programmable memory using junction diode, polysilicon diode, or isolated active-region diode as program selector in a cell can be generated accordingly.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.