Addressing Extended Or Expanded Memory Patents (Class 711/2)
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Patent number: 10353722Abstract: A computer system has: a virtual machine operating on a physical machine; and a management block operating on the physical machine and managing the virtual machine. The virtual machine has a specific function processing module that performs specific function processing with respect to a packet for transmission and a received packet. The management block has a virtual switch that relays a packet transmitted and received by the virtual machine. The virtual switch has an offload processing block that performs the specific function processing if the specific function processing is offloaded to the management block. If the specific function processing is offloaded from the virtual machine to the management block, the specific function processing module notifies the management block of processing information required for the specific function processing, and the offload processing block executes the specific function processing based on the processing information received from the virtual machine.Type: GrantFiled: May 23, 2011Date of Patent: July 16, 2019Assignee: NEC CORPORATIONInventors: Shuichi Karino, Akira Tsuji
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Patent number: 10339065Abstract: Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.Type: GrantFiled: December 1, 2016Date of Patent: July 2, 2019Assignee: Ampere Computing LLCInventors: Ankit Jindal, Pranavkumar Sawargaonkar, Keyur Chudgar
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Patent number: 10324867Abstract: Devices, systems, and methods for implementing a scalable extended basic input/output system (BIOS) region that increases the BIOS footprint of a system, are provided and described. In addition to a traditional BIOS region located in the memory mapped input/output (MMIO) low region, an extended BIOS region is initialized in a MMIO area of the system address map, where both regions are accessed by MMIO access requests.Type: GrantFiled: April 7, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Sivakumar Radhakrishnan, Mahesh S. Natu, Zhenyu Zhu, Malay Trivedi, Randall L. Albion, Chris Ruffin
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Patent number: 10216679Abstract: A migration of a program executing entity between a plurality of processors can be efficiently performed. A semiconductor device 1 includes a first processor 10, a second processor 20, and an external register 4 provided outside the processors. The first processor 10 includes a control circuit 12, an arithmetic circuit 14, and an internal storage circuit 16 provided inside the first processor 10. The second processor 20 includes a control circuit 22, an arithmetic circuit 24, and an internal storage circuit 26 provided inside the second processor 20. The control circuits 12 and 22 control execution of a program. The arithmetic circuits 14 and 24 perform an operation related to the program by using the external register 4. The external register 4 stores operation data related to the operation performed in the arithmetic circuits 14 and 24. The internal storage circuits 16 and 26 store execution state data regarding an execution state of the program.Type: GrantFiled: March 21, 2016Date of Patent: February 26, 2019Assignee: Renesas Electronics CorporationInventor: Makoto Sato
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Patent number: 10198203Abstract: A memory system includes a table storing a plurality of entries, where each entry is associated with a different logical block address (LBA), a plurality of memory devices, channels, and ways, where each memory device is connected to one of the channels ways and to one of the ways, and a memory controller configured to receive an LBA and data from a host, execute a plurality of pseudo-random functions on the received LBA to generate a plurality of slot indexes, select one of the slot indexes, write the data to one of the memory devices identified by the selected one slot index, and update a corresponding one of the entries to include the selected one slot index.Type: GrantFiled: November 15, 2016Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Michael Erlihson, Shmuel Dashevsky, Elona Erez, Guy Inbar, Jun Jin Kong, Keon Soo Ha
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Patent number: 10133883Abstract: A method, system, and computer program product for safeguarding nonvolatile storage (NVS) data by a processor in communication with a memory device following a power loss event is provided. A first portion of the NVS data is encrypted using a first buffer module. Subsequently the first portion of the NVS data is transferred to at least one shared storage device, while a second portion of the NVS data is simultaneously encrypted using a second buffer module. The second portion of the NVS data is subsequently transferred to the at least one shared storage device.Type: GrantFiled: February 9, 2009Date of Patent: November 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Ray Kahler, Anjul Mathur, Richard Anthony Ripberger
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Patent number: 10126959Abstract: System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface.Type: GrantFiled: July 31, 2015Date of Patent: November 13, 2018Assignee: SANDISK TECHNOLOGIES LLCInventor: Alan W. Sinclair
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Patent number: 10120572Abstract: A computing device includes a first processor; a second processor; a network interface communicably coupling the first and second processors to a network; an interface bus communicably coupling the first processor to the second processor; a first interface communicably coupling the second processor to the interface bus; a second interface communicably coupling the second processor to the interface bus, the second interface being separate from the first interface, wherein the second interface is configured to provide the second processor with management functionality over one or more hardware components of the computing device; and storage means communicably coupled to the second processor, wherein the second processor regulates access of the first processor to the storage means.Type: GrantFiled: March 22, 2016Date of Patent: November 6, 2018Inventor: Keicy Chung
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Patent number: 10062745Abstract: A method of forming an array of capacitors comprises forming elevationally-extending and longitudinally-elongated capacitor electrode lines over a substrate. Individual of the capacitor electrode lines are common to and a shared one of two capacitor electrodes of individual capacitors longitudinally along a line of capacitors being formed. A capacitor insulator is formed over a pair of laterally-opposing sides of and longitudinally along individual of the capacitor electrode lines. An elevationally-extending conductive line is formed over the capacitor insulator longitudinally along one of the laterally-opposing sides of the individual capacitor electrode lines. The conductive line is cut laterally through to form spaced individual other of the two capacitor electrodes of the individual capacitors. Other methods are disclosed, including structures independent of method of manufacture.Type: GrantFiled: January 9, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventor: Durai Vishak Nirmal Ramaswamy
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Patent number: 10061528Abstract: Example methods are provided to perform disk assignment for multiple distributed computing clusters in a virtualized computing environment. The method may include determining whether disk assignment is required for a host to support a first virtualized computing instance from a first distributed computing cluster and a second virtualized computing instance from a second distributed computing cluster. The method may also include migrating first data placed on one or more second disks to one or more first disks, reassigning the one or more second disks from the first virtualized computing instance to the second virtualized computing instance, and placing second data on the one or more second disks. The first data may be for access by the first virtualized computing instance to execute a first distributed computing application, and the second data may be for access by the second virtualized computing instance to execute a second distributed computing application.Type: GrantFiled: May 22, 2016Date of Patent: August 28, 2018Assignee: VMWARE, INC.Inventors: Binbin Zhao, Yonghua Lin Lin
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Patent number: 10037299Abstract: A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.Type: GrantFiled: August 29, 2017Date of Patent: July 31, 2018Assignee: Mellanox Technologies Ltd.Inventors: Carl G. Ramey, Christopher D. Metcalf
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Patent number: 9875082Abstract: Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.Type: GrantFiled: August 7, 2015Date of Patent: January 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael K. Gschwind
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Patent number: 9778945Abstract: Systems and methods for providing mode-dependent virtual machine (VM) function code. An example method may comprise: detecting, by a hypervisor executing by a processing device of a host computer system, a transition to a first execution mode by a guest operating system (OS) executing on the host computer system, wherein the first execution mode is characterized by at least one of: a first physical address size or a first general purpose register size; and responsive to the detecting, enabling a virtual machine (VM) function to be executed by the guest OS in the first execution mode.Type: GrantFiled: February 10, 2015Date of Patent: October 3, 2017Assignee: Red Hat Israel, Ltd.Inventor: Michael Tsirkin
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Patent number: 9727451Abstract: Methods and systems for implementing improved partitioning and virtualization in a multi-host environment are provided. According to one embodiment, multiple devices, including CPUs and peripherals, coupled with a system via an interconnect matrix/bus are associated with a shared memory logically partitioned into multiple domains. A first domain is associated with a first set of the devices and a second domain is associated with a second set of the devices. A single shared virtual map module (VMM), maps a memory access request to an appropriate partitioned domain of the memory to which the originating device has been assigned based on an identifier associated with the device and further based on they type of memory access. The VMM causes a memory controller to perform memory access on behalf of the device by outputting a physical address based on the identified domain and the virtual address specified by the request.Type: GrantFiled: March 28, 2014Date of Patent: August 8, 2017Assignee: Fortinet, Inc.Inventors: Xu Zhou, Zengli Duan, Ziyu Huang
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Patent number: 9715342Abstract: A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.Type: GrantFiled: July 5, 2016Date of Patent: July 25, 2017Assignee: XITORE, INC.Inventor: Mike Hossein Amidi
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Patent number: 9678778Abstract: Provided are methods and systems for providing users with a cluster of virtual machines (VMs) on-demand, whereby a group of VMs are provisioned together. Virtual Cluster as a Service (VClaaS) relaxes many restrictions on virtualizing VMs and provides performance benefits at the same or similar encapsulations and security measures that Infrastructure as a Service (IaaS) typically provides. The VClaaS system enables users to provision an entire cluster of VMs at a time, and also allows for relaxing the isolation barrier between the machines while maintaining the encapsulation barrier for the cluster as a whole, thereby providing users with improved networking, caching, and scheduling experiences.Type: GrantFiled: May 7, 2014Date of Patent: June 13, 2017Assignee: Google Inc.Inventor: Lamia Youseff
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Patent number: 9667743Abstract: A method for communication between two clients via a server in a network using OPC Unified Architecture (OPC-UA), wherein a virtual server object that provides a server functionality to a first of two clients is implemented in the server by making available to the first client a virtual address space in an address space of the server, and a process for generating and modifying virtual server nodes in said virtual address space. The server allows the second client to access virtual server nodes in the virtual address space and informs the first client each time that the second client accesses a virtual server node in the virtual address space.Type: GrantFiled: May 31, 2012Date of Patent: May 30, 2017Assignee: Siemens AktiengesellschaftInventors: Frank Volkmann, Markus Erlmann, Christian Hock
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Patent number: 9658821Abstract: Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.Type: GrantFiled: September 29, 2014Date of Patent: May 23, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael K. Gschwind
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Patent number: 9632791Abstract: Techniques are disclosed relating to a cache for patterns of instructions. In some embodiments, an apparatus includes an instruction cache and is configured to detect a pattern of execution of instructions by an instruction processing pipeline. The pattern of execution may involve execution of only instructions in a particular group of instructions. The instructions may include multiple backward control transfers and/or a control transfer instruction that is taken in one iteration of the pattern and not taken in another iteration of the pattern. The apparatus may be configured to store the instructions in the instruction cache and fetch and execute the instructions from the instruction cache. The apparatus may include a branch predictor dedicated to predicting the direction of control transfer instructions for the instruction cache. Various embodiments may reduce power consumption associated with instruction processing.Type: GrantFiled: January 21, 2014Date of Patent: April 25, 2017Assignee: Apple Inc.Inventors: Muawya M. Al-Otoom, Ian D. Kountanis, Ronald P. Hall, Michael L. Karm
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Patent number: 9632719Abstract: A storage device includes a primary storage extension chip, a plurality of secondary storage extension chips, and a plurality of resistors. Each of the storage extension chips includes two data pins, a plurality of general purpose input/output (GPIO) pins, and a firmware. Each of the GPIO pins is connected to a power terminal through one resistor, and is grounded through a resistor, for setting a firmware version number of storage extension chips. The primary storage extension chip determines whether the version number of each secondary storage extension chip is same as that of the primary storage extension chip. If the version number is different from that of the primary storage extension chip, the firmware version number of the primary storage extension chip is applied to the secondary storage extension chip.Type: GrantFiled: June 29, 2015Date of Patent: April 25, 2017Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jiing-Shyang Jang, Hsin-Ting Ke, Meng-Liang Yang
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Patent number: 9626105Abstract: A method, computer-readable storage medium and computer system for controlling a storage system, the storage system comprising a plurality of logical storage volumes, the method comprising: monitoring, for each of the logical storage volumes, one or more load parameters; receiving, for each of the logical storage volumes, one or more load parameter threshold values; comparing, for each of the logical storage volumes, the first load parameter values of said logical storage volume with the corresponding one or more load parameter threshold values; in case at least one of the first load parameter values of one of the logical storage volumes violates the load parameter threshold value it is compared with, automatically executing a corrective action.Type: GrantFiled: October 9, 2012Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Christian Bolik, Uwe Fiebrich-Kandler, Dietmar Noll
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Patent number: 9607632Abstract: Methods, apparatuses, and systems for allowing a single-die preamp to act as two or more virtual preamps for reading or writing data through multiple heads or elements concurrently. A selection register of a preamplifier is set to enable access to a primary register map. Values of registers in the primary register map are set to program a primary preamp channel for performing read or write operations to a first head. The selection register is then set to enable access to a secondary register map, and values of registers in the secondary register map are set to program a secondary preamp channel for performing read or write operations to a second head. Read or write operations can be performed to the first head through the primary preamp channel at a same time that read or write operations are performed to the second head through the second preamp channel.Type: GrantFiled: February 16, 2016Date of Patent: March 28, 2017Assignee: Seagate Technology LLCInventors: Robert Matousek, Thomas Lee Schick, Jon David Trantham
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Patent number: 9606732Abstract: A method, system, and computer program product to verify serialization of storage frames within an address space via multi-threaded programs is described. The method includes dynamically scaling a number of units of work based on a number of available processors, each of the units of work configured to execute actions, and dynamically scaling an amount and page size of virtual storage accessed by each of the units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage pages and accessing storage pages corresponding with the respective different types of virtual storage pages associated with the different frame sizes and attributes and performing a respective action, and verifying, for each of the units of work performing the respective action, a state and data content of the storage pages.Type: GrantFiled: May 28, 2014Date of Patent: March 28, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alfred F. Foster, Charles E. Mari, Robert Miller, Jr., Harris M. Morgenstern, Thomas F. Rankin, Elpida Tzortzatos
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Patent number: 9596133Abstract: A disclosed method includes: specifying an activity to be executed, based on process definition that includes plural activities, and that includes a sequence of transitions between activities, wherein each activity includes information representing a device that is operated through a network; first determining, based on the sequence of the transitions, whether or not the specified activity is an initial operation for a certain device whose information is included in the specified activity; and obtaining an access right to the certain device, when determining that the specified activity is the initial operation for the certain device.Type: GrantFiled: May 31, 2013Date of Patent: March 14, 2017Assignee: FUJITSU LIMITEDInventor: Ryuichi Kawahara
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Patent number: 9563555Abstract: Resources of an address space are managed in dynamically sized ranges, extents, sets, and/or blocks. The address space may be divided into regions, each corresponding to a different, respective allocation granularity. Allocating a block within a first region of the address space may comprise allocating a particular number of logical addresses (e.g., a particular range, set, and/or block of addresses), and allocating a block within a different region may comprise allocating a different number of logical addresses. The regions may be configured to reduce the metadata overhead needed to identify free address blocks (and/or maintain address block allocations), while facilitating efficient use of the address space for differently sized data structures.Type: GrantFiled: April 17, 2013Date of Patent: February 7, 2017Assignee: SanDisk Technologies LLCInventors: David Flynn, Nick Piggin, Nisha Talagala
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Patent number: 9548091Abstract: A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.Type: GrantFiled: April 8, 2015Date of Patent: January 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Hee Shin, Sang-Jhun Hwang, Young-Man Ahn
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Patent number: 9519430Abstract: A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.Type: GrantFiled: May 28, 2014Date of Patent: December 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alfred F. Foster, Robert Miller, Jr., Thomas F. Rankin
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Patent number: 9471322Abstract: Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates.Type: GrantFiled: February 12, 2014Date of Patent: October 18, 2016Assignee: Apple Inc.Inventors: Conrado Blasco, Ian D. Kountanis
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Patent number: 9436466Abstract: Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.Type: GrantFiled: April 8, 2014Date of Patent: September 6, 2016Assignee: IXYS Intl LimitedInventor: Gyle D. Yearsley
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Patent number: 9400664Abstract: An aspect of the invention is directed to a storage management computer for managing offloading of storage workload between a storage controller of a storage system and one or more host computers. The storage management computer comprises: a memory; and a controller operable to request a virtual machine management computer to register the storage controller as a host computer, and to send, to the virtual machine management computer, storage processes information of storage processes in the storage system which can be offloaded as virtual machines in order for the virtual machine management computer to register the storage processes as virtual machines.Type: GrantFiled: December 20, 2012Date of Patent: July 26, 2016Assignee: HITACHI, LTD.Inventors: Masayuki Sakata, Akio Nakajima, Akira Deguchi
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Patent number: 9292211Abstract: A path is formed between a host computer and storage apparatuses without depending on the configuration of the host computer and a network and a plurality of volumes having a copy function are migrated between storage apparatuses while keeping the latest data.Type: GrantFiled: March 2, 2011Date of Patent: March 22, 2016Assignee: Hitachi, Ltd.Inventors: Hideo Saito, Yoshiaki Eguchi, Masayuki Yamamoto, Akira Yamamoto
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Patent number: 9213493Abstract: A disk drive is disclosed that utilizes sorted serpentine mapping of data tracks. In one embodiment, a plurality of physical heads of the disk drive is mapped to a plurality of logical heads. The plurality of logical heads is sorted according to the respective data rates of the physical heads, such as in the order of decreasing data rates. Data tracks are mapped using sorted serpentine mapping that utilizes the sorted order of the logical heads. Improved performance can thereby be attained.Type: GrantFiled: December 16, 2011Date of Patent: December 15, 2015Assignee: Western Digital Technologies, Inc.Inventor: William B. Boyle
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Patent number: 9190173Abstract: A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.Type: GrantFiled: March 30, 2012Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Darshan Kobla, David Zimmerman, John C. Johnson, Vimal K. Natarajan
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Patent number: 9182993Abstract: A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.Type: GrantFiled: May 31, 2005Date of Patent: November 10, 2015Assignee: BROADCOM CORPORATIONInventors: Genkun Jason Yang, Ramkumar Prakasam
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Patent number: 9170740Abstract: The present invention is a system and method which allows for a VTL system that supports thin provisioning to implicitly unmap unused storage. Such unmap operations may occur even though the VTL system does not receive any explicit unmap requests from its initiators. For example, if a system administrator knows that once a virtual tape drive of the VTL system has been partially overwritten, all previously written data sets on that virtual tape drive will never again be accessed, the system administrator may configure the VTL system so that it unmaps the entire remainder of the virtual tape drive on the first data overwrite.Type: GrantFiled: August 6, 2010Date of Patent: October 27, 2015Assignee: NetApp, Inc.Inventors: Ross Zwisler, Brian McKean, Kevin Kidney
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Patent number: 9134954Abstract: This disclosure proposes techniques for demand paging for an IO device (e.g., a GPU) that utilize pre-fetch and pre-back notification event signaling to reduce latency associated with demand paging. Page faults are limited by performing the demand paging operations prior to the IO device actually requesting unbacked memory.Type: GrantFiled: September 10, 2012Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Colin Christopher Sharp, David Rigel Garcia Garcia, Eduardus A. Metz
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Patent number: 9128625Abstract: Contiguous regions of physical memory may be reserved for user-space programs through a boot time parameter that specifically identifies the memory region to be reserved. In an implementation, the boot time parameter includes first and second values that are used to define a starting and ending address of the memory region to be reserved. The reserved memory is accessible by the operating system kernel storage and networking stacks so that the user-space programs can use services provided by the kernel storage and networking stacks.Type: GrantFiled: March 26, 2012Date of Patent: September 8, 2015Assignee: EMC CORPORATIONInventor: Anand Ananthabhotla
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Patent number: 9116688Abstract: For efficient issue of a superscalar instruction a circuit is employed which retrieves an instruction of each instruction code type other than a prefix based on a determination result of decoders for determining instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant. When an instruction of a target code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target code type as prefix code candidates. When an instruction of a target code type cannot be detected at the rear end of the instruction units, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head.Type: GrantFiled: March 1, 2013Date of Patent: August 25, 2015Assignee: Renesas Electronics CorporationInventor: Fumio Arakawa
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Patent number: 9081600Abstract: A system, method, and computer program product for providing validation of the compliance of a trusted host environment with a requirement of a virtual machine (VM). The system includes: a store component for cryptographically storing configuration data associated with the trusted host environment in at least one cryptographic data structure; a send component, responsive to the store component storing the configuration data, for sending the at least one cryptographic data structure to a control component; an analyze component, responsive to the control component receiving the at least one cryptographic data structure, for analyzing the at least one cryptographic data structure; a compare component, responsive to the analyze component determining the configuration data, for comparing the configuration data with the requirement; and a verify component, responsive to the compare component determining that the configuration data matches the requirement, for allowing verification of the VM.Type: GrantFiled: December 19, 2011Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: David N. Mackintosh, James W. Walker, James C. Whitson
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Patent number: 9037773Abstract: An electronic apparatus is disclosed. The electronic apparatus comprises a random access memory (RAM), a read-only memory (ROM) and a processing unit. The RAM stores a call transfer table, wherein the call transfer table comprising at least one transferred address in the RAM. The ROM stores at least one code to call one address of the call transfer table. The processing unit executes the code in the ROM and reads the transfer table accordingly, then transfers to run the data in the transferred address of the RAM.Type: GrantFiled: December 16, 2008Date of Patent: May 19, 2015Assignee: MEDIATEK INC.Inventors: Hsin-Chung Yeh, Cheng Huang Wu
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Publication number: 20150113198Abstract: A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip.Type: ApplicationFiled: December 29, 2014Publication date: April 23, 2015Inventors: Yansong Li, Yulin Zheng
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Patent number: 8972641Abstract: It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address, which slaves may be addressed using the assigned address in the standard or in the expanded addressing mode. Thus, in a field device, it is possible to provide slaves having different profiles, via which different data types may be exchanged. Furthermore, a method is provided, with which a field device having different slaves is able to be addressed in a simple manner while avoiding double addressing.Type: GrantFiled: May 16, 2007Date of Patent: March 3, 2015Assignee: Sew-Eurodrive GmbH & Co. KGInventors: Wolfgang Kropp, Andreas Schiff
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Patent number: 8949474Abstract: A system on a chip (SOC) includes a master module, a first swapping module, and a switch module. The master module is configured to generate a transaction request, the transaction request including an address field including an address, the address corresponding to a first slave module associated with the transaction request, and a plurality of interface select bits corresponding to a desired one of a plurality of ports of the first slave module. The first swapping module is configured to swap, in the transaction request, the plurality of interface select bits with selected bits of the address in the address field. The switch module is configured to route the transaction request to the desired one of the plurality of ports based on the address.Type: GrantFiled: November 16, 2012Date of Patent: February 3, 2015Assignee: Marvell International Ltd.Inventors: Ian Swarbrick, Joseph Jun Cao, Jun Zhu
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Patent number: 8924622Abstract: Various embodiments for managing data in a computing storage environment by a processor device are provided. In one such embodiment, by way of example only, an extender storage pool system is configured for at least one of a source and a target storage pool to expand an available storage capacity for the at least one of the source and the target storage pool. A most recent snapshot of the data is sent to the extender storage pool system. The most recent snapshot of the data is stored on the extender storage pool system as a last replicated snapshot of the data.Type: GrantFiled: March 20, 2014Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Juan A. Coronado, Christina A. Lara, Lisa R. Martinez
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Patent number: 8904096Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.Type: GrantFiled: August 9, 2013Date of Patent: December 2, 2014Assignee: Sony CorporationInventors: Toshiyuki Nishihara, Yoshio Sakai
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Patent number: 8843725Abstract: Disclosed is a method and apparatus for a storage system comprising at least one mobile random access storage device capable of storing first or second data. At least one docking station is associated with an address wherein the address is identifiable by at least one host computer. A first and second sub-address is associated with the at least one docking station wherein the first and second sub-addresses are identifiable by the at least one host computer. The first sub-address corresponds to a first virtual device adapted for storing the first data on a first virtual media. The second sub-address corresponds to a second virtual device adapted for storing the second data on a second virtual media wherein the second virtual media is a different media type from the first virtual media.Type: GrantFiled: September 19, 2005Date of Patent: September 23, 2014Assignee: Spectra Logic CorporationInventors: Matthew Thomas Starr, Richard Douglas Rector, Nathan Christopher Thompson
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Patent number: 8838873Abstract: In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable circuit module is configured to receive, from a host device, information associated with a search request. The reprogrammable circuit module is configured to change from a first configuration to a second configuration in response to receiving the information. The reprogrammable circuit module is configured to retrieve at least a portion of the data stored at the set of memory modules associated with the second configuration. The reprogrammable circuit module is configured to generate a search result based on the portion of the data, and transmit the search result to the host device.Type: GrantFiled: June 25, 2012Date of Patent: September 16, 2014Assignee: Data Design CorporationInventors: John J. Giganti, Andrew Huo, Richard A. Baum, John M. Cavallo, Timothy P. Bresnan, Charles A. Moses, Madhu Siddalingaiah
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Patent number: 8832360Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.Type: GrantFiled: May 24, 2013Date of Patent: September 9, 2014Assignee: Micron Technology, Inc.Inventor: Dean Klein
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Patent number: 8825976Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. A logical block address (LBA) is mapped to a data sector on the disk. During a bias interval following the start of a host boot operation, a biased migration policy is executed that increases a likelihood of migrating the LBA to the NVSM. After the bias interval a normal migration policy is executed.Type: GrantFiled: September 28, 2010Date of Patent: September 2, 2014Assignee: Western Digital Technologies, Inc.Inventor: Brian E. Jones
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Patent number: 8812756Abstract: A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.Type: GrantFiled: October 1, 2010Date of Patent: August 19, 2014Assignee: Phison Electronics Corp.Inventor: Ching-Wen Chang