Segment Or Page Table Descriptor Patents (Class 711/208)
  • Patent number: 10666754
    Abstract: An information handling system includes first and second servers, and a storage controller. The storage controller to initialize a first virtual function for the first server, to initialize a second virtual function for the second server, to assign equal amounts of a first portion of a memory to the first and second virtual functions, to profile an input/output workload of the first and second virtual functions, to allocate amounts of a second portion of the memory to the first and second virtual functions based on a first input/output profile of each of the virtual functions, and to allocate a remaining portion of the memory as a global section of the memory for use by any of the virtual functions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: May 26, 2020
    Assignee: Dell Products, L.P.
    Inventors: Kiran K. Devarapalli, Chandrashekar Nelogal, Krishnaprasad Koladi
  • Patent number: 10628072
    Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.
    Type: Grant
    Filed: November 4, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongyan Jiang, Qiang Peng, Hongzhong Zheng
  • Patent number: 10620687
    Abstract: Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan M. Eastep, Richard J. Greco, Federico Ardanaz
  • Patent number: 10552230
    Abstract: A hypervisor of a source host receives a request to migrate a group of virtual machines that provide network function virtualization support (NFV) from the source host to a destination host. The hypervisor of the source host determines that a first virtual machine of the group of virtual machines being migrated to the destination host shares a memory space on the source host with the group of virtual machines on the source host. Upon receiving a request from a second virtual machine of the group of virtual machines on the source host to access a first memory page of the shared memory space on the source host that has been migrated to the destination host, the hypervisor of the source host initiates migration of the second virtual machine to the destination host.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: February 4, 2020
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael S. Tsirkin, David A. Gilbert
  • Patent number: 10552131
    Abstract: Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Clarence Siu Yeen Dang, Arun Upadhyaya Kishan
  • Patent number: 10503660
    Abstract: An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 10, 2019
    Assignee: Arm Limited
    Inventors: Abhishek Raja, Michael Filippo
  • Patent number: 10489335
    Abstract: The invention introduces an apparatus for accessing a memory card to at least include a host interface and a processing unit. The processing unit is arranged to operably inspect whether a logical block length utilized in a memory card inserted into a card reader can be supported by a host; and reply to the host with sense data that advises the host not to perform a subsequent write into the memory card through the host interface in response to a request sense command when the logical block length utilized in the memory card cannot be supported by the host.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 26, 2019
    Assignee: SILICON MOTION, INC.
    Inventors: Wen-Han Chen, Hsing-Lang Huang, Guo-Rung Huang
  • Patent number: 10331360
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10324857
    Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Joseph Nuzman, Raanan Sade, Igor Yanover, Ron Gabor, Amit Gradstein
  • Patent number: 10216961
    Abstract: An administrator may set restrictions related to the operation of a virtual machine (VM), and virtualization software enforces such restrictions. There may be restrictions related to the general use of the VM, such as who may use the VM, when the VM may be used, and on what physical computers the VM may be used. There may be similar restrictions related to a general ability to modify a VM, such as who may modify the VM. There may also be restrictions related to what modifications may be made to a VM, such as whether the VM may be modified to enable access to various devices or other resources. There may also be restrictions related to how the VM may be used and what may be done with the VM. Information related to the VM and any restrictions placed on the operation of the VM may be encrypted to inhibit a user from circumventing the restrictions.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 26, 2019
    Assignee: VMware, Inc.
    Inventors: Matthew David Ginzton, Matthew B. Eccleston, Srinivas Krishnamurti, Gerald C. Chen, Nick Michael Ryan
  • Patent number: 10176028
    Abstract: A computer program product, system, and method are provided for upgrading a kernel or kernel module with a configured persistent. A persistent memory memory space is configured in the memory to store application data from applications in user mode. A kernel executing in the memory is prevented from accessing the persistent memory space. A service is called to load an updated kernel in the memory to replace the kernel, wherein the applications have access to the persistent memory space after the updated kernel is loaded. The service may comprise a kernel execution mechanism that directly loads the updated kernel into the memory without a full reboot of the computer system. An extended memory kernel service may be loaded during a boot operation to reserve the persistent memory space as an extended memory space for use by the applications and prevent the kernel from accessing the persistent memory space.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lior Chen, Alex Friedman, Constantine Gavrilov, Aharon Novogrodski, Alex Snast
  • Patent number: 10108553
    Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 23, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yao Liu, Licheng Chen, Zehan Cui, Mingyu Chen
  • Patent number: 9772802
    Abstract: An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 9740439
    Abstract: Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The solid-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michele M. Franceschini, Ashish Jagmohan
  • Patent number: 9720762
    Abstract: Systems and methods for clearing bank descriptors for reuse by gate banks without requiring a system reboot are described. In some embodiments, information regarding a bank descriptor of a memory system may be obtained. From the information, a determination may be made as to whether the bank descriptor describes a common bank. When the bank descriptor describes a common bank, the bank descriptor can be updated to no longer describe the common bank.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 1, 2017
    Assignee: Unisys Corporation
    Inventors: Brian L McElmurry, Edward Kujawa, Sandra Wierdsma
  • Patent number: 9626298
    Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David Craddock, Thomas A. Gregg, Dan F. Greiner, Eric N. Lais
  • Patent number: 9584628
    Abstract: A data transmission system for transmitting a data file from a server to a client device includes a processor, a memory and a network interface device. The memory includes a user space and a kernel space. The data file is stored in the kernel space. The processor receives a transmission request from the client device for transmitting the data file. The processor maps a set of virtual addresses corresponding to the data file to the user space as a mapped data file, and stores a set of physical addresses corresponding to the set of virtual addresses in a set of meta-buffers of a socket created in the user space. The network interface device retrieves the data file from the kernel space based on the set of physical addresses from the set of meta-buffers, and transmits the data file to the client device.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 28, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Arun Pathak, Hemant Agrawal, Sahil Malhotra
  • Patent number: 9430329
    Abstract: Apparatus and method for data integrity management in a data storage device. In accordance with some embodiments, a controller transfers user data blocks between a host device and a main memory. Each user data block has an associated logical address. A data integrity manager generates and stores a verification code for each user data block in a table structure in a local memory. The data integrity manager uses the verification code to independently verify a most current version of a selected user data block is being retrieved by the controller from the main memory during a host read request.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: August 30, 2016
    Assignee: Seagate Technology LLC
    Inventor: Jon David Trantham
  • Patent number: 9164884
    Abstract: A display controller is provided that includes a processing unit configured to process input data, a memory unit configured to store some of the processed input data before a transition signal is enabled, a memory management unit configured to map consecutive virtual addresses of an image displayed on a display panel to physical addresses of data stored in the memory unit, and a control unit configured to control the processing unit and the memory management unit in response to a control signal and configured to provide a range of virtual addresses designated by the transition signal in response to enablement of the transition signal such that the image is displayed on the display panel.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 20, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hun Han, Kyong-Ho Cho
  • Patent number: 9081724
    Abstract: A method of protecting digital data stored in a storage medium. The method comprises providing a first and a second addressable storage region in the storage medium, and selector means for selectively indicating one of the first and the second addressable storage regions as active; storing the digital data in the first addressable storage region of the storage medium, wherein the digital data stored in the first addressable storage region is stored encrypted with a first encryption key; and causing the selector means to indicate the first addressable storage region as being active; and, responsive to a trigger event, copying the digital data from the first to the second addressable storage region, wherein the digital data stored in the second addressable storage region is stored encrypted with a second encryption key; and causing the selector means to indicate the second addressable storage region as being active.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: July 14, 2015
    Assignee: ST-ERICSSON SA
    Inventors: Nicolas Anquet, Hervé Sibert
  • Patent number: 9015437
    Abstract: The present disclosure provides a system and method for implementing extensible hardware configuration using memory. A memory containing an Info Block is provided. The Info Block contains a set of descriptors, which comprises an address part and a data part. The OTP Engine reads each valid descriptor stored in the Info Block, and writes the data in the data part into the memory location specified by the address part. The OTP Engine interacts with the Info Block by accessing the Info Block Controller registers via the central system bus.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 21, 2015
    Assignee: SMSC Holdings S.A.R.L.
    Inventors: Alan Berenbaum, Uri Segal
  • Patent number: 9015400
    Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Zeng, Azzedine Touzni, Tzung Ren Tzeng, Phil J. Bostley
  • Patent number: 9009386
    Abstract: A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Hatfield, Wenjeng Ko, Lei Liu
  • Patent number: 9003161
    Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Hatfield, Wenjeng Ko, Lei Liu
  • Patent number: 8990422
    Abstract: Systems, apparatusses, and methods are disclosed for transmission control protocol (TCP) segmentation offload (TSO). A hardware TSO engine is capable of handling segmentation of data packets and consequent header field mutation of hundreds of flows simultaneously. The TSO engine generates data pointers in order to “cut up” the payload data of a data packet, thereby creating multiple TCP segments. Once the data of the data packet has been fetched, the TSO engine “packs” the potentially-scattered chunks of data into TCP segments, and recalculates each TCP segment's internet protocol (IP) length, IP identification (ID), IP checksum, TCP sequence number, and TCP checksum, as well as modifies the TCP flags. The TSO engine is able to rapidly switch contexts, and share the control logic amongst all flows.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: March 24, 2015
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Ozair Usmani, Kaushik Kuila
  • Patent number: 8972648
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi Kumar, Shailaja Mallya
  • Patent number: 8972647
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 8954697
    Abstract: A system configures page tables to cause an operating system to copy original page data in a data store when any one of the application processes makes a first write request for the original page data. The system detects a page fault from a memory management unit receiving a first write request from one of the application processes and creates the copy in physical memory to allow the application process to modify the page data copy. The other application processes have read access to the original page data. The system replaces the original page data in the data store with the page data copy in response to receiving a first synchronization request from the application process and updates a page table for one of the other application processes to configure access to the replaced page data in response to receiving a second synchronization request from the one other application process.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Red Hat, Inc.
    Inventors: Neil R. T. Horman, Eric L. Paris, Jeffrey T. Layton
  • Patent number: 8954710
    Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: February 10, 2015
    Assignee: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller
  • Patent number: 8949571
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: November 3, 2013
    Date of Patent: February 3, 2015
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg
  • Patent number: 8938572
    Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: January 20, 2015
    Assignee: Amazon Technologies, Inc.
    Inventor: Pradeep Vincent
  • Publication number: 20150019834
    Abstract: A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Gabriel H. Loh, James M. O'Connor
  • Patent number: 8898423
    Abstract: A data storage system is disclosed that utilizes a high performance caching architecture. In one embodiment, the caching architecture utilizes a cache table, such as a lookup table, for referencing or storing host data units that are cached or are candidates for being cached in the solid-state memory. Further, the caching architecture maintains a segment control list that specifies associations between particular cache table entries and particular data segments. Such separation of activities related to the implementation of a caching policy from activities related to storing cached data and candidate data provides robustness and scalability while improving performance.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: November 25, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chandra M. Guda, Michael Ainsworth, Choo-Bhin Ong, Marc-Angelo P. Carino
  • Publication number: 20140304489
    Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventors: John Colgrove, John Hayes, Ethan Miller
  • Patent number: 8856489
    Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 7, 2014
    Assignee: PURE Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller, Feng Wang
  • Patent number: 8843727
    Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: September 23, 2014
    Assignee: Intel Corporation
    Inventors: Ioannis Schoinas, Gilbert Neiger, Rajesh Madukkarumukumana, Ku-jei King, Richard Uhlig, Achmed Rumi Zahir, Koichi Yamada
  • Patent number: 8832351
    Abstract: In a computing system including a processor and virtualization software including a guest operating system (OS) that utilizes a guest domain access control register (DACR) containing domain access information and guest page tables including first level page tables (L1 page tables) and second level page tables (L2 page tables), which guest page tables contain: (a) domain identifiers used to obtain domain access information from the guest DACR and (b) access permission information, wherein the domain access information and the access permission information are combined to provide an effective guest access permission, in accordance with one embodiment, a method for providing shadow page tables and processor DACR settings that virtualize processor memory protection includes: the virtualization software providing a shadow page table wherein: (a) domain identifiers in the shadow page table are used to identify domain access information in the processor DACR that are mapped from the domain access information in the
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 9, 2014
    Assignee: VMware, Inc.
    Inventors: Harvey Tuch, Prashanth P. Bungale, Scott W. Devine, Lawrence S. Rogel
  • Patent number: 8819393
    Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey O. Blandy, Janet R. Easton, Lisa C. Heller, William A. Holder, Damian L. Osisek, Gustav E. Sittmann, Richard P. Tarcza, Leslie W. Wyman
  • Patent number: 8806175
    Abstract: A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash table system comprises inserting the entry into the first hash table, and, when the first hash table reaches a threshold load factor, flushing entries into the second hash table. Flushing the first hash table into the second hash table may comprise sequentially flushing the first hash table segments into corresponding second hash table segments. When looking up a key/value pair corresponding to a selected key in the hash table system, the system checks both the first and second hash tables for values corresponding to the selected key. The first and second hash tables may be divided into hash table segments and collision policies may be implemented within the hash table segments.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: August 12, 2014
    Assignee: Longsand Limited
    Inventors: Peter D. Beaman, Robert S. Newson, Tuyen M. Tran
  • Patent number: 8799622
    Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: August 5, 2014
    Assignee: Silicon Motion Inc.
    Inventors: Chun-Kun Lee, Tsai-Cheng Lin
  • Patent number: 8793428
    Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: July 29, 2014
    Assignee: VMware, Inc.
    Inventors: Qasim Ali, Raviprasad Mummidi, Kiran Tati
  • Patent number: 8782338
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Publication number: 20140189286
    Abstract: A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data.
    Type: Application
    Filed: August 16, 2013
    Publication date: July 3, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: HUNG-SHENG CHANG, CHENG-YUAN WANG, HSIANG-PANG LI, YUAN-HAO CHANG, PI-CHENG HSIU, TEI-WEI KUO
  • Patent number: 8719543
    Abstract: Systems and methods are provided that utilize non-shared page tables to allow an accelerator device to share physical memory of a computer system that is managed by and operates under control of an operating system. The computer system can include a multi-core central processor unit. The accelerator device can be, for example, an isolated core processor device of the multi-core central processor unit that is sequestered for use independently of the operating system, or an external device that is communicatively coupled to the computer system.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 6, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patryk Kaminski, Thomas Woller, Keith Lowery, Erich Boleyn
  • Patent number: 8706947
    Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 22, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Pradeep Vincent
  • Patent number: 8688952
    Abstract: An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Kimura
  • Patent number: 8683174
    Abstract: A storage system comprises a storage apparatus which includes a processor, storage disks, and a memory storing a page mapping table, a page mapping program, and a page-filename mapping program. A file system manages a file tree of files with filenames. The page mapping table specifies a relationship between data volumes in the storage apparatus and the storage disks and the file system, the data volumes each including pages, each page including segments, each segment including sectors. The file tree has for each storage apparatus a hierarchy of directories and files based on relationships among the data volumes, the pages, and the segments. The page mapping program and the page-filename mapping program are executable by the processor to specify, by page, a location of data contained in the I/O request by referring to the page mapping table and the file tree.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Matsuzawa, Yasunori Kaneda
  • Patent number: 8645664
    Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: February 4, 2014
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller, Feng Wang
  • Publication number: 20140032875
    Abstract: The method of the present inventive concept is configured to utilize Operating System data structures related to memory-mapped binaries to reconstruct processes. These structures provide a system configured to facilitate the acquisition of data that traditional memory analysis tools fail to identify, including by providing a system configured to traverse a virtual address descriptor, determine a pointer to a control area, traverse a PPTE array, copy binary data identified in the PPTE array, generate markers to determine whether the binary data is compromised, and utilize the binary data to reconstruct a process.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Inventor: James Butler
  • Publication number: 20140019711
    Abstract: A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a dispersed storage device for receiving a request relating to a data object stored in the dispersed storage network and determining a virtual memory address assigned to the data object. The virtual memory address is within a virtual memory address range of the virtual address space that is allocated to a vault associated with a user of the data object. The virtual memory address is further assigned to a data slice of a plurality of data slices of the data object. The dispersed storage device uses the virtual memory address to determine an identifier of a storage unit within the dispersed storage network that has the data slice stored therein.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Applicant: Cleversafe, Inc.
    Inventors: Wesley Leggette, Greg Dhuse, Andrew Baptist, S. Christopher Gladwin