Abstract: A permissions model for a processor in which permissions are based on the instruction group of an instruction. These permissions may be stored in permissions tables and indexed using the program counter of the instruction. The permissions may identify which of a plurality of instruction groups of an instruction set architecture (ISA) of a processor are permitted to execute from that program counter value. Accordingly, the instruction group of the instruction can be compared to the permitted instruction groups to determine if the instruction has execution permission. In some cases, the instruction-group-based permissions are secondary execution privileges; additional primary execution permissions that are determined using the program counter may also be used.

Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.

Abstract: A page table structure for address translation may include a relative type of page table entry, for which an address pointer to a next-level page table entry or a translated address may be specified using a relative offset value indicating an offset of the address pointer relative to a reference-point base address.

Abstract: Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on the determined memory allocation pattern.

Abstract: A method including configuring a VPN server to receive, from a user device during an established VPN connection between the VPN server and the user device, a data request for the VPN server to retrieve data of interest from a host device; configuring the VPN server to transmit, to the host device during the established VPN connection, a query to retrieve the data of interest based at least in part on utilizing a first exit IP address; and configuring the VPN server to retransmit, to the host device during the established VPN connection, the query to retrieve the data of interest based at least in part on utilizing a second exit IP address when the first exit IP address is blocked by the host device is disclosed. Various other aspects are contemplated.

Abstract: A unified memory address translation system includes a translation queue module configured to receive different modes of translation requests for a real address (RA) of a physical memory. A translation cache (XLTC) interface is configured to receive successful translation results for previous requests for an RA and provide the previous successful translation result to the translation queue module. A plurality of page table entry group (PTEG) search modules are coupled to the translation queue module. A unified translation walk address generation (UTWAG) module is configured to provide a translation support for each mode of the different modes of translation request. A memory interface is coupled between the UTWAG and the physical memory.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: Embodiments bypass Address Space Layout Randomization (ASLR) executed on a web server that implements a web function. Embodiments, from a client remote from the web server, construct a stack layout of the web function. Embodiments identify memory locations of the stack layout that are writable and read a currently stored library instruction address of a library at the identified memory locations. Embodiments then iteratively increment the currently stored library instruction address by one and overwriting the identified memory locations until a remote shell is successfully spawned or another malicious instruction is executed.

Abstract: Systems, apparatuses, and methods for limiting translation lookaside buffer (TLB) searches using active page size are described. A TLB stores virtual-to-physical address translations for a plurality of different page sizes. When the TLB receives a command to invalidate a TLB entry corresponding to a specified virtual address, the TLB performs, for the plurality of different pages sizes, multiple different lookups of the indices corresponding to the specified virtual address. In order to reduce the number of lookups that are performed, the TLB relies on a page size presence vector and an age matrix to determine which page sizes to search for and in which order. The page size presence vector indicates which page sizes may be stored for the specified virtual address. The age matrix stores a preferred search order with the most probable page size first and the least probable page size last.

Abstract: A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.

Abstract: Disclosed herein are system, method, and computer program product embodiments for storing an object onto a first or second page. An embodiment operates by receiving the object and determining that the first page has sufficient unused space for storing at least one byte of the object. Thereafter, a data block of the object is created to comprise at least one byte of the object. The data block is then stored on the first page or the second page, and a location of the object's first data block is recorded. Thereafter, a pointer corresponding to the location of the object's first data block for loading the object is provided.

Abstract: A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.

Abstract: A memory address translation system includes a translation requestor module configured to provide translation requests from a virtual address to a real address of a physical memory. A translation cache module is configured to receive the translation request from the translation requestor module. A sleep and wake control module is configured to compare the received VA to VA's of all presently active table walks of the table walk machines. Upon determining that there is an address match in a given table walk machine, the translation request is sent with an identification number (ID) to the translation requestor module, to be put to sleep. Each table walk machine is configured to provide a wake-up signal having an ID to the translation requestor module upon completion of its translation level, thereby triggering a waking up and processing of a presently sleeping translation request, to provide parallel translation table walks.

Abstract: Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry).

Abstract: A communication gateway for communicating data frames for a motor vehicle, the gateway being intended to be connected to a plurality of electronic control units in order to exchange data frames, the gateway including: as many management modules as there are electronic control units; a memory in which are stored a lookup table including an index list, with each of the indices of which is associated a memory space, a level-zero addressing table, a level-one addressing table, a level-two addressing table and an address table of levels; a space manager for managing spaces of the lookup table that is configured to determine a free index in the lookup table, and when a memory space of the lookup table is freed or is filled, to modify the byte stored in each memory region of each addressing table associated with the index.

Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.

Abstract: In a distribution matching circuit, output data of a plurality of LUTs forming a hierarchical tree structure sequentially designates a combination of signal point groups in a signal space managed by an LUT in an immediately lower level, and signal point information after distribution matching is output for each LUT in the lowermost level.

Abstract: A method for updating block addresses is provided. The method includes overwriting content of a first data block referenced by a first logical block address (LBA) with updated content. Prior to overwriting, the content of the first data block is stored in a first physical block corresponding to a first physical block address (PBA), a logical map maps the first LBA to a first middle block address (MBA), and a middle map maps the first MBA to the first PBA. After overwriting, the updated content of the first data block is stored in a second physical block corresponding to a second PBA and, in response to the overwriting, the middle map is updated to map the first MBA to the second PBA instead of the first PBA.

Abstract: An apparatus comprises processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; and a memory protection unit (MRU) comprising permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system. The memory protection table comprises memory protection entries each specifying access permissions for a corresponding address region of variable size within an address space, where the variable size can be a number of bytes other than a power of 2.

Abstract: Process address space identifier virtualization uses hardware paging hint.

Abstract: Examples disclosed herein relate to performing a verification check in response to receiving notification. A computing system includes a host processor, memory coupled to the host processor, and a device separate from the host processor capable of accessing the memory. The host processor has a page table base register. The host processor is configured to send a notification to the device when the page table base register changes. The device performs a verification check in response to receiving the notification.

Abstract: Disclosed is a method and system for managing execution of processes on a cluster of processing devices by a supervising device. The method comprises receiving memory consumption information from each of a processing devices executing a plurality of processes. The method further comprises receiving information related to swapping of a new process from at least one processing device of the processing devices while memory available on the at least one processing device is insufficient to execute the new process. The method further comprises terminating either the new process being swapped or a process executing on the at least one processing device. The method further comprises instructing another processing device having sufficient memory available for execution of the new process being swapped or the process executing on the at least one processing device, whichever is terminated on the at least one processing device.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

Abstract: An administrator may set restrictions related to the operation of a virtual machine (VM), and virtualization software enforces such restrictions. There may be restrictions related to the general use of the VM, such as who may use the VM, when the VM may be used, and on what physical computers the VM may be used. There may be similar restrictions related to a general ability to modify a VM, such as who may modify the VM. There may also be restrictions related to what modifications may be made to a VM, such as whether the VM may be modified to enable access to various devices or other resources. There may also be restrictions related to how the VM may be used and what may be done with the VM. Information related to the VM and any restrictions placed on the operation of the VM may be encrypted to inhibit a user from circumventing the restrictions.

Abstract: A hardware device architecture is described that improves security and flexibility in access to hardware device settings. A device management proxy service is digitally signed and granted access to device settings. Applications are then digitally provisioned by the proxy service and only validated signed requests from applications are permitted to change hardware device settings. Further granularity over hardware device settings is achieved through user accounts and groups established by the applications.

Abstract: Described examples include a system having a non-volatile memory including a binary section, a first page table and a second page table. The system also has a volatile memory and a processor coupled to the non-volatile memory and the volatile memory, the processor operable to use the first page table when the processor is initialized, the first page table including a first pointer to the binary section, the processor operable to cause copying of the binary section of the non-volatile memory to the volatile memory to create a copied binary section in the volatile memory, and the processor operable to use the second page table when the copying is complete, the second page table including a second pointer to the copied binary section.

Abstract: Systems and methods for embedding emulation support for a hardware feature into a virtual machine to enhance the security of the hypervisor and host system. An example method may comprise: receiving, by a processing device executing a hypervisor, a message indicating a hardware feature is unavailable; determining, by the hypervisor, whether a virtual machine is capable of emulating the hardware feature; and causing, by the hypervisor, the virtual machine to emulate the hardware feature in response to determining the virtual machine is capable of emulating the hardware feature.

Abstract: Systems and methods for managing access to storage devices in a distributed data storage environment. Embodiments operate to manage communications between a client computing device and storage target devices in a distributed storage system. The distributed storage system comprises one or more computing nodes and at least one storage target device. A client computing device interfaced with the distributed storage system uses an IP address to access a leader virtualized controller. Upon receipt of a storage access protocol message by the leader virtualized controller elected from a set of virtualized controllers, a redirect message comprising a second IP address that identifies a second virtualized controller is sent to the client computing device. The client computing device connects to the second virtualized controller. Messages are sent between the client computing device and the second virtualized controller, which in turn accesses the storage target device to carry out storage I/O protocol messaging.

Abstract: An information handling system includes first and second servers, and a storage controller. The storage controller to initialize a first virtual function for the first server, to initialize a second virtual function for the second server, to assign equal amounts of a first portion of a memory to the first and second virtual functions, to profile an input/output workload of the first and second virtual functions, to allocate amounts of a second portion of the memory to the first and second virtual functions based on a first input/output profile of each of the virtual functions, and to allocate a remaining portion of the memory as a global section of the memory for use by any of the virtual functions.

Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.

Abstract: Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.

Abstract: Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint.

Abstract: A hypervisor of a source host receives a request to migrate a group of virtual machines that provide network function virtualization support (NFV) from the source host to a destination host. The hypervisor of the source host determines that a first virtual machine of the group of virtual machines being migrated to the destination host shares a memory space on the source host with the group of virtual machines on the source host. Upon receiving a request from a second virtual machine of the group of virtual machines on the source host to access a first memory page of the shared memory space on the source host that has been migrated to the destination host, the hypervisor of the source host initiates migration of the second virtual machine to the destination host.

Abstract: An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages.

Abstract: The invention introduces an apparatus for accessing a memory card to at least include a host interface and a processing unit. The processing unit is arranged to operably inspect whether a logical block length utilized in a memory card inserted into a card reader can be supported by a host; and reply to the host with sense data that advises the host not to perform a subsequent write into the memory card through the host interface in response to a request sense command when the logical block length utilized in the memory card cannot be supported by the host.

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

Abstract: An administrator may set restrictions related to the operation of a virtual machine (VM), and virtualization software enforces such restrictions. There may be restrictions related to the general use of the VM, such as who may use the VM, when the VM may be used, and on what physical computers the VM may be used. There may be similar restrictions related to a general ability to modify a VM, such as who may modify the VM. There may also be restrictions related to what modifications may be made to a VM, such as whether the VM may be modified to enable access to various devices or other resources. There may also be restrictions related to how the VM may be used and what may be done with the VM. Information related to the VM and any restrictions placed on the operation of the VM may be encrypted to inhibit a user from circumventing the restrictions.

Abstract: A computer program product, system, and method are provided for upgrading a kernel or kernel module with a configured persistent. A persistent memory memory space is configured in the memory to store application data from applications in user mode. A kernel executing in the memory is prevented from accessing the persistent memory space. A service is called to load an updated kernel in the memory to replace the kernel, wherein the applications have access to the persistent memory space after the updated kernel is loaded. The service may comprise a kernel execution mechanism that directly loads the updated kernel into the memory without a full reboot of the computer system. An extended memory kernel service may be loaded during a boot operation to reserve the persistent memory space as an extended memory space for use by the applications and prevent the kernel from accessing the persistent memory space.

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

Abstract: An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.

Abstract: Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The solid-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.

Abstract: Systems and methods for clearing bank descriptors for reuse by gate banks without requiring a system reboot are described. In some embodiments, information regarding a bank descriptor of a memory system may be obtained. From the information, a determination may be made as to whether the bank descriptor describes a common bank. When the bank descriptor describes a common bank, the bank descriptor can be updated to no longer describe the common bank.

Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

Abstract: A data transmission system for transmitting a data file from a server to a client device includes a processor, a memory and a network interface device. The memory includes a user space and a kernel space. The data file is stored in the kernel space. The processor receives a transmission request from the client device for transmitting the data file. The processor maps a set of virtual addresses corresponding to the data file to the user space as a mapped data file, and stores a set of physical addresses corresponding to the set of virtual addresses in a set of meta-buffers of a socket created in the user space. The network interface device retrieves the data file from the kernel space based on the set of physical addresses from the set of meta-buffers, and transmits the data file to the client device.

Abstract: Apparatus and method for data integrity management in a data storage device. In accordance with some embodiments, a controller transfers user data blocks between a host device and a main memory. Each user data block has an associated logical address. A data integrity manager generates and stores a verification code for each user data block in a table structure in a local memory. The data integrity manager uses the verification code to independently verify a most current version of a selected user data block is being retrieved by the controller from the main memory during a host read request.

Abstract: A display controller is provided that includes a processing unit configured to process input data, a memory unit configured to store some of the processed input data before a transition signal is enabled, a memory management unit configured to map consecutive virtual addresses of an image displayed on a display panel to physical addresses of data stored in the memory unit, and a control unit configured to control the processing unit and the memory management unit in response to a control signal and configured to provide a range of virtual addresses designated by the transition signal in response to enablement of the transition signal such that the image is displayed on the display panel.

Abstract: A method of protecting digital data stored in a storage medium. The method comprises providing a first and a second addressable storage region in the storage medium, and selector means for selectively indicating one of the first and the second addressable storage regions as active; storing the digital data in the first addressable storage region of the storage medium, wherein the digital data stored in the first addressable storage region is stored encrypted with a first encryption key; and causing the selector means to indicate the first addressable storage region as being active; and, responsive to a trigger event, copying the digital data from the first to the second addressable storage region, wherein the digital data stored in the second addressable storage region is stored encrypted with a second encryption key; and causing the selector means to indicate the second addressable storage region as being active.

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract: The present disclosure provides a system and method for implementing extensible hardware configuration using memory. A memory containing an Info Block is provided. The Info Block contains a set of descriptors, which comprises an address part and a data part. The OTP Engine reads each valid descriptor stored in the Info Block, and writes the data in the data part into the memory location specified by the address part. The OTP Engine interacts with the Info Block by accessing the Info Block Controller registers via the central system bus.