Abstract: Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a tag value indicating a segment of a virtual volume to which the command block is directed. The tag value is used to select one of a plurality of mapping segment objects stored in a memory of the controller. Each mapping segment objects maps logical block addresses of a corresponding segment of a corresponding virtual volume to physical storage addresses on the physical storage devices that comprise the virtual volume. An I/O processing circuit of the controller then processes the SCSI command block in accordance with the mapping information in the selected mapping segment object. In one exemplary embodiment, each segment of a virtual volume comprises 2 terabytes of storage capacity of the virtual volume.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording valid/invalid page position information of at least one block; and moving valid data contained in at least a valid page of the block according to the valid/invalid page position information; where the block is an erasing unit. For example, the valid/invalid page position information may contain relative position information of the valid data in the block. More particularly, the valid/invalid page position information may contain a plurality of bits, the ranking of each bit may represent a page address offset of each page within the block, and each bit may respectively indicate whether each page in the block is valid or invalid.

Abstract: Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count.

Abstract: Systems, methodologies, media, and other embodiments associated with mitigating the effects of context switch cache and TLB misses are described. One exemplary system embodiment includes a processor configured to run a multiprocessing, virtual memory operating system. The processor may be operably connected to a memory and may include a cache and a translation lookaside buffer (TLB) configured to store TLB entries. The exemplary system may include a context control logic configured to selectively copy data from the TLB to the data store for a first process being swapped out of the processor and to selectively copy data from the data store to the TLB for a second process being swapped into to the processor.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A method and apparatus for detecting the configuration of a device in a processing system are described. In one embodiment, a page size parameter associated with a memory device is identified. Further, one or more configuration parameters associated with the memory device are also identified, the page size parameter and the configuration parameters enabling access to the memory device. Finally, a request to download application data from the memory device based on the page size parameter and the one or more configuration parameters is transmitted to the memory device.

Abstract: Disclosed is a method of detecting an access to de-allocated memory, comprising: creating a pool of fixed size memory blocks that are a non-zero integer multiple of a page size of a processor; receiving a request for an allocation of a block of memory; recording a set of allocation context information in a fixed size memory block; returning a pointer to an allocation of memory within said fixed size memory block; receiving a request to de-allocate said block of memory; recording a set of de-allocation context information in said fixed size memory block; and, setting an indicator in a page table entry associated with said fixed size memory block to a first value that indicates access to said fixed size memory block is not allowed.

Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.

Abstract: A data item interval identifier lookup method and system is proposed, which is designed for integration to an information processing system for finding which predefined interval the value of an input data item, such as an IP (Internet Protocol) address, belongs. The proposed method and system is characterized by the use of a multi-stage lookup-table data structure having a number of cascaded lookup tables constructed by partitioning the data format of the input data item into a number of segments, each being mapped to one stage of lookup table data structure whose key-value relationships are predefined based on a predefined interval-and-identifier definition table. In operation, the values of the partitioned segments are sequentially used as lookup keys to search through the multi-stage lookup-table data structure until the corresponding interval identifier is found. This feature allows the implementation to have low memory requirement and enhanced system performance.

Abstract: A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.

Abstract: A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system also includes a host engine coupled to the emulator and configured to perform instructions in the second format. The emulator is configured to determine whether a store command in the first format stores information to a memory page that includes instructions and to convert the store instruction to a special store instruction in the event that the target of the store instruction does not contain an instruction.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segments as segment assignment information. An address conversion circuit refers to segment assignment information to convert a logical address into a physical address. A segment queue stores a free segment and a buffer queue stores a free buffer. The state storage circuit includes a plurality of register groups each of which includes a plurality of segment registers. A register group is associated with one of the plurality of buffer spaces. A range number identifying a range of logical addresses in the associated buffer space is set up in a segment register.

Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A method of verifying programming of an integrated circuit card includes transferring program data to a page buffer of a non-volatile memory, copying the program data to a buffer memory, calculating a first checksum value with respect to program data in the buffer memory, updating the program data in the buffer memory by copying the program data of the page buffer to the buffer memory, calculating a second checksum value with respect to updated program data in the buffer memory, comparing the first checksum value and the second checksum value, and determining, based on the comparison result, whether the program data of the page buffer is tampered.

Abstract: A system and method for allocating data objects across multiple physical storage devices in a mass storage subsystem first determines a set of physical properties associated with the physical storage devices. The system assigns portions of the mass storage subsystem to a first division or a second division based on the physical properties, such that read operations directed to logically related data stored in the first division can be executed more efficiently than read operations directed to data stored in the second division. During operation, the system stores data objects with a low SLR in the second division, which may be allocated according to any well-known file system. If a write request is for a new data object with a high SLR, the system stores the new data object in a set of neighboring primary data chunks in the first division.

Abstract: A method manages memory paging operations. Responsive to a request to page out a memory page from a shared memory pool, the method identifies whether a physical space within one of a number of paging space devices has been allocated for the memory page. If physical space within the paging space device has not been allocated for the memory page, a page priority indicator for the memory page is identified. The memory page is then allocated to one of a number of memory pools within one of the number of paging space devices. The memory page is allocated one of the memory pools according to the page priority indicator of the memory page. The memory page is then written to the allocated memory pools.

Abstract: A method and apparatus for reducing a page replacement time in a system using a demand paging technique are provided. The apparatus includes a memory management unit which transmits a signal indicating that a page fault occurs, a device driver which reads a page having the page fault from a nonvolatile memory, and a page fault handler that searches and secures a space for storing the page having the page fault in a memory. The searching and securing of the space in the memory is performed within a limited time calculated beforehand and a part of data to be loaded to the memory of the system is stored in the nonvolatile memory.

Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.

Abstract: In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: One embodiment of the present invention provides a system and a method for performing a page-table lookup in a manner that supports adaptive page sizes. During operation, the system receives a virtual address. Next, the system looks up this virtual address in a page table. Since each entry in the page table maintains a page size, the lookup process involves using the page size to determine the number of bits that must be compared to find a matching page table entry. A page table entry matches the virtual address if the determined number of bits in the virtual address match the virtual address in the page table entry. If a matching page table entry is found, the system returns the physical page address from the matching page table entry.

Abstract: A method and apparatus for managing memory allocation using memory pages. A first physical memory page is compared with a second physical memory page, wherein the first physical memory page is associated with a first page table and the second physical memory page is associated with a second page table. If the second physical memory page matches the first physical memory page, the second physical memory page is deallocated, and the second page table is associated with the first physical memory page.

Abstract: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

Abstract: A system, method and computer program product for virtualizing a processor include a virtualization system running on a computer system and controlling memory paging through hardware support for maintaining real paging structures. A Virtual Machine (VM) is running guest code and has at least one set of guest paging structures that correspond to guest physical pages in guest virtualized linear address space. At least some of the guest paging structures are mapped to the real paging structures. For each guest physical page that is mapped to the real paging structures, paging means for handling a connection structure between the guest physical page and a real physical address of the guest physical page. A cache of connection structures represents cached paths to the real paging structures. Each path is described by guest paging structure descriptors and by tie descriptors. Each path includes a plurality of nodes connected by the tie descriptors.

Abstract: Methods, systems and apparatuses to dynamically balance execution loads on a partitioned system among processor cores or among partitions.

Abstract: Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table entry that specifies the physical address of the virtual page in linear physical address space. The page table entry also includes a data kind field that is used to guide and optimize the mapping process from the linear physical address space to the DRAM physical address space, which is used to directly access one or more DRAM. The DRAM physical address space includes a row, bank and column address. The data kind field is also used to optimize the starting partition number and partition interleave pattern that defines the organization of the selected physical page of memory within the DRAM memory system.

Abstract: An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.

Abstract: A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

Abstract: A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and system can be used to limit the number of items within the directory, direct content and content components to different directories, and provide an internally recognizable name for the filename. When searching the storage medium, time is not wasted searching what appears to be a seemingly endless list of filenames or subdirectory names within any single directory. A client computer can have requests for content fulfilled quicker, and the network site can reduce the load on hardware or software components. While the method and system can be used for nearly any storage media, the method and system are well suited for cache memories used with web servers.

Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

Abstract: A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application on a host computer system, executing a first virtual machine application within a first virtual machine, and executing a second virtual machine application within a second virtual machine. A plurality of TLB (translation look aside buffer) entries for the first virtual machine application and the second machine application are stored within a TLB of the host computer system. At least one of the plurality of TLB entries is a global TLB entry.

Abstract: A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.

Abstract: According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.

Abstract: A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

Abstract: The present invention is a four layer architecture that includes reusable components that can be used in varied operating environments and with varied network devices. The architecture includes an operating system dependent layer, an operating system independent layer, a media independent layer, and a media dependent layer. The operating system dependent layer can vary for differing operating system. In contrast, the operating system independent layer is identical or substantially similar for differing operating systems. Similarly, the media independent layer is identical or substantially similar for different network devices (e.g., a family or group of network devices). The media dependent layer can vary according to differing and varied network devices.

Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.

Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract: The present invention relates to a digital audio layer and an audio content file management method of a digital audio player. This method writes address of an recording area containing descriptive information such as title of a song and a singer's name for each stored audio file in a file management information area for a corresponding audio file. Then, descriptive information can be directly searched and displayed more quickly using the written address if an audio file is selected.