Abstract: A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.

Abstract: Provided are a method, system, and article of manufacture, wherein in certain embodiments, a plurality of logical memory blocks corresponding to a memory in a computational device are allocated. An attribute is associated with at least one logical memory block, wherein the attribute indicates whether the at least one logical memory block can be swapped from the memory, and wherein physical blocks corresponding to the at least one logical memory block are contiguous.

Abstract: Various embodiments of a system and method for optimizing storage library operations. In one embodiment a method may comprise storing a plurality of efficiency values indicative of relative efficiencies of storage targets in a storage library, and executing a storage library operation based on the plurality of efficiency values. Efficiency values may include, for example, information on a physical layout of the storage library. In one embodiment storage targets may include at least the following classes: a slot class, a portal class, a drive class, a picker class, and a media class. In one embodiment, executing a storage library operation based on the plurality of efficiency values may comprise selecting one or more storage targets to implement the storage library operation based on the plurality of efficiency values. For example, a drive closest to a given media unit may be selected to read the media unit.

Abstract: A method, and corresponding software and system, is described for paging memory used for one or more sequentially-accessed data structure. The method includes providing a data structure representing an order in which memory pages are to be reused; and maintaining the data structure according to a history of access to a memory page associated with one of the sequentially-accessed data structures. A position of the memory page in the order depends on a transition of sequential access off of the memory page.

Abstract: Pretranslating input/output buffers in environments with multiple page sizes that include determining a pretranslation page size for an input/output buffer under an operating system that supports more than one memory page size, identifying pretranslation page frame numbers for the buffer in dependence upon the pretranslation page size, pretranslating the pretranslation page frame numbers to physical page numbers, and storing the physical page numbers in association with the pretranslation page size. Typical embodiments also include accessing the buffer, including translating a virtual memory address in the buffer to a physical memory address in dependence upon the physical page numbers and the pretranslation page size and accessing the physical memory of the buffer at the physical memory address.

Abstract: A storage operating system is configured to assign volume block numbers (VBNs) to a volume. The system has a plurality of disks, and each disk of the plurality of disks is assigned disk block numbers (DBNs). A raidmap is configured to map the VBNs to the DBNs of the plurality of physical disks, the mapping for a particular disk stored in a disk label for the particular disk. The disk label for the particular disk is then written to the particular disk.

Abstract: A method and system for transmitting packets having a first address length on a core network supporting a second address length, where the second address length is larger than the first address length by determining a length of the first address and establishing an offset to the first address such that a combined length of the offset, length of a network prefix for the second address and length of the first address equals the length of the second address. The method and system of the present invention can be implemented as an enhancement to existing network protocols such as IPv4, IPv6 and the like.

Abstract: A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical processor and a target address space. In response to the instruction, first information is checked to determine whether the target logical processor is running. When it is determined that the target logical processor is not running, second information is checked by a host program to determine whether the target logical processor has access to the target address space.

Abstract: A method for processing using a shared file that includes creating a plurality of mmaps between a shared file and a plurality of address spaces, wherein each of the plurality of mmaps maps at least a portion of the shared file to one of the plurality of address spaces, and wherein each of the plurality of address spaces is associated with one of a plurality of processors, transferring, in parallel, data between the shared file and the address spaces using the plurality of mmaps associated with the plurality of address spaces, processing the data in parallel by the plurality of processors to obtain a result, wherein the plurality of processors access data from the plurality of address spaces, and storing the result in the shared memory.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: A circuit is provided for performing interleaving and deinterleaving functions in a digital communication system. The circuit includes a single-port memory that reads first data units from a first interleaved sequence of address locations to generate a first data stream and that writes second data units from a second data stream to the address locations. A first address generator module communicates with the single-port memory and generates a first interleaved sequence of addresses that correspond to the address locations and correspond to one of an interleaving function and deinterleaving function between the first data stream and the second data stream.

Abstract: A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame al song as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.

Abstract: A method and apparatus for digital forensics are provided. The apparatus for digital forensics includes a page file extractor for extracting a page file stored in a target storage medium, a stored-page feature extractor for extracting features of pages stored in the extracted page file, a page classifier for comparing the extracted features of the pages with at least one predetermined classification criterion and classifying the pages according to the comparison results, and a digital forensics unit for performing digital forensics according to the classified pages. According to the method and apparatus, it is possible to perform digital forensics using only information of a page file.

Abstract: A method and system for reading data from a non-volatile mass storage device is provided. The method includes, performing logical configuration for the non-volatile mass storage device, wherein file data is allocated addresses in a virtual logical address space; and data identified by virtual logical addresses is read by a host system. The system includes a file storage segment that reads and writes data on a file-by-file basis, allowing a host system to access data from the non-volatile mass storage device using a file interface format; and a logical interface segment that allows the host system to access data using logical addressing, wherein the host system is unaware of a storage format under which data is stored on a file-by-file basis.

Abstract: An emulation apparatus includes a translator, a first memory map, a second memory map, and a rewriting unit. The translator translates an instruction output from the target program to an instruction executable by the emulation apparatus. The first memory map is located in a memory region for use by the target program and is write-protected based on operation environment of the emulation apparatus. The second memory map is write-protected based on at least one of the execution environment of the target program and content of the instruction from the target program. The rewriting unit rewrites a first write instruction output from the translator to a second write instruction to the second memory map when the first write instruction causes a write protection violation to the first memory map.

Abstract: A demand paging apparatus and a method for an embedded system are provided. The demand paging apparatus includes a nonvolatile storage device, a physical memory, a demand paging window, and a demand paging manager. The nonvolatile storage device stores code and data which are handled by demand paging. The physical memory processes information about a requested page that is read from the nonvolatile storage device. The demand paging window generates a fault for the page and, thus, causes demand paging to occur. The demand paging window is part of an address space to which an application program stored in the nonvolatile storage device refers. The demand paging manager processes the page fault generated in the demand paging window.

Abstract: A method and a storage device may be provided. The storage device may include physical storage subdivided into a number of regions. The regions may start and end based on logical block addresses specified in a region table. At least one of the regions may be mapped to a logical drive letter. One or more others of the regions may be mapped to a subfolder with respect to the logical drive letter. The storage device may include an access control table. Each entry of the access control table may correspond to a respective region of the physical storage. Each of the entries of the access control table may indicate whether the respective region is protected and whether at least one entity is permitted protected access to the respective region after being successfully authenticated.

Abstract: Registering memory space for an application is performed. One or more open calls are received from an application to access one or more input/output (I/O) devices. Responsive to receiving the one or more open calls, one or more I/O map and pin calls are sent in order to register memory space for the one or more I/O devices within at least one storage area that will be accessed by the application. A verification is made as to whether the memory space to be registered is associated with the application. Responsive to the memory space being associated with the application, at least one virtual I/O bus address is received for each registered memory space of the one or more I/O devices. At least one I/O command is executed using the at least one virtual I/O bus address without intervention by an operating system or operating system image.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording unit, and can guarantee continuous reproduction of the divisionally recorded data. Of data divisionally recorded on a recording medium (5), data which corresponds to an end portion of that data and cannot be recorded as a recording area equal to or larger than a minimum recording unit specified in the recording medium (5) due to the presence of a recording area (6) of another data, that has already been recorded on the recording medium (5), is re-recorded on a recording area equal to or larger than the minimum recording unit. At this time, new data is generated by combining data less than the minimum recording unit, and data recorded in another recording area, and the new data is re-recorded on a new recording area.

Abstract: A move data facility is provided that enables optional specifications to be indicated to flexibly control the move operation. Data may be moved from any address space to any other address space without modifying the operating system to support such a move. A single instruction is used, for instance, to perform the move. Additional specifications may also be indicated to control the move.

Abstract: A machine-accessible medium may contain program instructions that, when executed by a processor, may cause the processor to perform at least one operation including searching a virtual hash page table (VHPT) using a region identifier and a virtual page number of a virtual address, and a default page size corresponding to the region identifier to locate a virtual address translation in the VHPT. The operation performed may further include searching the VHPT using the region identifier, the virtual page number, and at least one utilized page size to locate a virtual address translation in the VHPT if a virtual address translation is not located during the search of the VHPT using the region identifier, virtual page number, and default page size. The operation performed may also include inserting the located virtual address translation into a translation cache once a virtual address translation is located.

Abstract: A block management method for managing a mapping relationship between a plurality of logical blocks and a plurality of physical blocks of a flash memory is provided. The block management method includes: grouping the logical blocks into a plurality of logical zones; recording the mapping relationship between each logical block in each logical zone and all the data physical blocks among the physical blocks in a corresponding logical zone table in unit of the logical zones; and recording all the no-data physical blocks among the physical blocks with a single no-data physical block table. Thereby, the logical blocks can be mapped to all the physical blocks so that frequent access to specific physical blocks can be avoided when a user writes data into a specific logical zone frequently, and accordingly the lifespan of the flash memory can be prolonged.

Abstract: A method, computer program product, and distributed data processing system for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter is provided. A mechanism is provided for directly destroying the resources associated with one or more virtual adapters that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter.

Abstract: The storage system includes page area association information that associates a page area that partitions a storage area in a real volume into predetermined storage areas with a page area that partitions a storage area in a virtual volume into predetermined storage areas; a pair setting unit for pairing a primary virtual volume that stores data from a host computer and a secondary virtual volume to store a copy of the data stored in the primary virtual volume; and a page release unit for releasing association between a page area in the secondary virtual volume and a page area in the secondary real volume associated in advance with the page area in the secondary virtual volume.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory arrangement including a first memory, and a second memory operatively coupled to the first memory to serve as an external interface of the memory arrangement to one or more components external to the memory arrangement to access different portions of the first memory concurrently. Other embodiments may be described.

Abstract: A method for identifying relocatable kernel memory allocations in kernel non-relocatable memory is described. In this method, a physical address hardware mapping entry (PA HME) for each process accessing a physical page of memory by physical addresses. For each of the PA HMEs corresponding a process that does not permit page relocation, the pre-relocation handler and post-relocation handler references of each PA HME is set to null. Each PA HMEs is associated with a pmapping list for the physical page. Thus, A physical page is identified as non-relocatable when one of the PA HMEs referenced by the pmapping list has null pre-relocation and post-relocation handler references.

Abstract: A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that is associated with some range of virtual addresses and that can be used to translate any virtual address in its range to a physical address, where the sizes of the ranges mapped by different clusters may be different. Clusters are stored in an address translation table that is indexed by virtual address so that, starting from any valid virtual address, the appropriate cluster for translating that address can be retrieved from the translation table. Recently retrieved clusters are stored in an on-chip cache, and a cached cluster can be used to translate any virtual address in its range without accessing the address translation table again.

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed with a reduced number of signal lines.

Abstract: A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo logical volume and pseudo logical volume information associated with the pseudo logical volume, the pseudo logical volume being another of the logical volumes; and upon receipt of a command for canceling an assignment of one of the logical volumes to the corresponding recognition information, modifying the mapping information so that recognition information that has been indicative of said one of the logical volumes becomes indicative of the pseudo logical volume information associated with the pseudo logical volume.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: A system and methodology that can prevent errors during data commit on multicycle pass complete associated with a memory is provided. The system employs a transaction buffer component in the memory that receives and temporarily stores information associated with a transaction. A controller component programs subsets of data to respective memory locations once the entire transaction is completed based on the information stored in the transaction buffer component. Thus, if the transaction is interrupted during the transfer of the user data into the buffer, the data stored in the memory is not affected and can still contain the original data when power is regained. If the data transfer between the transaction buffer component and memory array is interrupted, the controller component can complete the transfer from the point of interruption on regaining power and can avoid partial storage of data.

Abstract: In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing a portion of the pipeline resource corresponding to an address space including the entry.

Abstract: In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

Abstract: A computer implemented method, data processing system, and computer usable code are provided for managing memory use for program segments in an executable program. The process copies a set of identified executable program segments associated with the executable program to a set of page segments in a memory space. The process unmaps the set of identified executable program segments and the set of page segments. The process then remaps the set of page segments to a source memory location associated with the set of identified executable program segments.

Abstract: Provided are an apparatus and a method of reducing memory access conflict. An apparatus for reducing memory access conflict when a plurality of data processing elements perform simultaneous access to a memory including a plurality of pages, each of which includes a plurality of subpages, the apparatus comprising: an access arbiter mapping a subpage division address corresponding to least significant bits of a memory access address received from each of the data processing elements to another address having a same number of bits as the subpage division address in order for data to be output from each of the subpages in a corresponding page at a time of the simultaneous access; and a selector, prepared for each of the pages, selecting to output one of the data output from the subpages using the mapped results.

Abstract: a data processing apparatus includes: an instruction execution section; an instruction protection information storage section that stores instruction protection information for specifying at least one partial address space in an instruction address space for storing instructions executed by the instruction execution section; a data protection information storage section that stores data protection information for specifying multiple partial address spaces in a data address space for storing operands for use in an operation of the instruction execution section; and a protection violation determination section that determines whether to permit access from the instruction execution section based on setting of the instruction and data protection information storage sections.

Abstract: A method for directly destroying one or more virtual resources that reside within a physical adapter and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional Peripheral Component Interconnect (PCI) I/O adapters, PCI-X I/O adapters, PCI-Express I/O adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for host to adapter communications.

Abstract: A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

Abstract: A method and apparatus of configuring the byte structure of a memory storage device, including a flash memory device, to enhance the security and error correction capability is described. In one embodiment, the method includes increasing the security of data stored in the storage device by encrypting data with a unique initialization vector and storing the initialization vector in the storage device. The method also includes using a unique initialization vector for encrypting data, to be stored in each datablock, each time data are encrypted. In one embodiment, the apparatus includes an AES controller that includes encryption and decryption modules to encrypt and decrypt data prior to writing data to or reading from the storage device. The apparatus also includes an encoder module and decoder circuits to encode and decode data prior to writing or reading from memory storage devices.

Abstract: A run level address mapping table and related method provides for storing address mapping data, which maps logical addresses to physical addresses in a flash memory using a flash translation layer. A first value is stored in the address mapping table, indicating an initial location for a run within a memory block, the run having at least two consecutive physical addresses. A second value is stored in the address mapping table, indicating a total size for the run.

Abstract: Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid addresses. Such a programming error is detected and an exception is thrown (that is, an addressing error is detected and indicated) responsive to an address reference to such a gap in valid addresses. Gaps are configured at complementary address ranges to facilitate detection of such aliasing errors.

Abstract: Methods and computer readable media for generating displays of user-defined blocks of networking addresses on a map of an associated address space are provided. Each block of networking addresses is described in a user-defined table with a start address and a map size. The display for each block of network addresses may be rendered on the map at a location based on the relative position of the start address within the associated address space and of a size based on the mask size in relation to the associated address space.

Abstract: When a static logical partition is set in a storage system, wasted resources are generated depending on the load state of the logical partition. Thus, after a logical partition is created, the storage system reconfigures the assignment of resources to the logical partition based on a predetermined configuration. The timing of a resource assignment reconfiguration is based on a job execution schedule, which is associated with a predetermined configuration, and which is executed by a computer utilizing the logical partition. There is also a constitution, wherein a computer sends a predetermined command to the storage system to instruct the storage system to reconfigure the resource assignment. There is also a constitution of a storage system, wherein a resource required for reconfiguring the resource assignment to the logical partition is reserved beforehand, and this reservation is canceled after the passage of a predetermined period of time.

Abstract: A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical addresses are mapped to storage units using a volume mapping table. Each volume mapping table is comprised of a plurality of segments. Each segment need not be contiguously allocated to another segment of the same table. Thus, each volume mapping table can be independently expanded or reduced without affecting other volume mapping tables. A hash function, a hash table, a segment table, and a redundancy group descriptor table may also be used to help manage the segments of the volume mapping tables.

Abstract: Provided are a method and apparatus capable of reducing a metadata processing time associated with address mapping performed to input/output burst data at a high speed in a virtual file system of a storage unit having a plurality of non-volatile data storage media. The method includes: determining a block group including a block included in each of a plurality of the non-volatile data storage media; determining an access unit including each page included in the determined block group; and mapping an address of input/output data to the determined block group and the access unit. Therefore, it is possible to significantly reduce an address mapping processing time in the virtual file system that may function as a bottleneck in high-speed input/output in a large-capacity storage unit.

Abstract: Where a computing device is provided with executable programs in relatively slow non-volatile memory, such as ROM, the device performance can be improved by shadowing, a process by which those programs are copied into relatively fast volatile memory, such as RAM. Shadowing is often inefficient because code is copied that is too infrequently used to benefit from the procedure, wasting processing time and memory. The present invention determines which parts of the slow memory are most frequently accessed, either by profiling or by intimate knowledge of the working of the device, and then shadows only those pages of executable programs whose frequent use warrants it. In a preferred embodiment the most frequently used code areas are clustered together onto certain pages of the non-volatile memory and the least frequently used code areas are clustered onto other pages of non-volatile memory.

Abstract: A proximity interconnect module includes a plurality of off-chip cache memories. Either disposed external to the proximity interconnect module or on the proximity interconnect module are a plurality of processors that are dependent on the plurality of off-chip cache memories for servicing requests for data. The plurality of off-chip cache memories are operatively connected to either one another or to one or more of the plurality of processors by proximity communication. Each of the plurality of off-chip cache memories may cache certain portions of the physical address space.