Abstract: A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

Abstract: Determining an effective address of a memory with a three-operand add operation in single execution cycle of a multithreaded processor that can access both segmented memory and non-segmented memory. During that cycle, the processor determines whether a memory segment base is zero. If the segment base is zero, the processor can access a memory location at the effective address without adding the segment base. If the segment base is not zero, such as when executing legacy code, the processor consumes another cycle to add the segment base to the effective address. Similarly, the processor consumes another cycle if the effective address or the linear address is misaligned. An integer execution unit that performs the three-operand add using a carry-save adder coupled to a carry look-ahead adder. If the segment base is not zero, the effective address is fed back through the integer execution unit to add the segment base.

Abstract: Reserve a plurality of blocks in a flash. Write a plurality of hot data into the plurality of blocks in a cyclic and sequential manner. After completing a cycle of writing data and hot data is to be written into the plurality of blocks, send a logic block address corresponding to hot data of a page to a cold/hot data identifying engine if the hot data of the page of a decay block are not updated. And the cold/hot data identifying engine decays a count of a counter corresponding to the logic block address according to the logic block address.

Abstract: A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance.

Abstract: The system includes first and second storage systems. The first storage system includes a first control unit managing a plurality of logical units (LUs) and a plurality of first storage devices being controlled to store data by the first control unit, the plurality of LUs including a first type LU and a second type LU, the first type LU corresponding to at least one of the plurality of first storage devices of the first storage system so that data to be stored to the first type LU is stored to the at least one of the plurality of first storage devices of the first storage system, the second type LU mapping to an LU which is managed by a second storage system so that data to be stored to the second type LU is transferred to the LU managed by the second storage system.

Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.

Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.

Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.

Abstract: Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.

Abstract: A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring logical units for mapping to the physical units of the data area and writing update data belonging to the logical pages of the logical units orderly into the physical pages of physical units gotten from the free area. The method further includes configuring root units for the logical pages, configuring an entry chain for each of the root units and building entries on the entry chains for recording update information of the updated logical pages, wherein each of the logical pages corresponds to a root unit. Accordingly, the table size for storing the update information is effectively reduced and the time for searching valid data is effectively shortened.

Abstract: A process for creates a virtual address for a software entity called a “daughter” belonging to the context of a software entity called the “mother.” This virtual address includes a series of fields allowing retrieval of the series of fields of the virtual address of the mother software entity and a field unique in the context of the mother software entity. Each series of fields is associated with a single software entity which it defines completely.

Abstract: A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory.

Abstract: A method of operation of a data storage system includes: enabling a system interface for receiving host commands; updating a mapping register for monitoring transaction records of a logical block address for the host commands including translating a host virtual block address to a physical address for storage devices; accessing by a storage processor, the mapping register for comparing the transaction records with a tiering policies register; and enabling a tiered storage engine for transferring host data blocks by the system interface and concurrently transferring between a tier zero, a tier one, or a tier two if the storage processor determines the transaction records exceed the tiering policies register.

Abstract: A method for preventing subversion of address space layout randomization (ASLR) in a computing device is described. An unverified module attempting to load into an address space of memory of the computing device is intercepted. Attributes associated with the unverified module are analyzed. A determination is made, based on the analyzed attributes, whether a probability exists that the unverified module will be loaded into a number of address spaces that exceeds a threshold. The unverified module is prevented from loading into the address space if the probability exists that the unverified module will be loaded into a number of address spaces that exceeds the threshold.

Abstract: A method includes indexing a translation table stored in memory with a first index of a virtual address corresponding to a first memory region size by querying the translation table at first locations associated with the first index. Indexing the translation table with a second index of the virtual address corresponding to a second memory region size by querying the translation table at second locations associated with the second index. The translation table includes translations for mapping address tags of the virtual address to physical addresses. The first index is different than the second index, and the first memory region size is different than the second memory region size.

Abstract: A storage device controller may segregate data units that are typically accessed together to a common storage unit. In one example, a storage device includes a control unit configured to receive a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks, and a non-volatile memory configured to store logical blocks in a plurality of storage units, wherein one of the plurality of storage units includes logical blocks corresponding to a second set of addresses. The control unit may determine an intersection of the first set of addresses with the second set of addresses and to store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit comprises one of the plurality of storage units.

Abstract: Methods are provided for efficiently storing data to a data storage device or subsystem. The data storage device may be a Solid-State Device (SSD), and may be implemented as part of a RAID (Redundant Array of Independent Disks) or other subsystem. When existing data is read and updated, and must be re-stored, the data is assembled and stored as if it were new data, and is written in a sequential manner, instead of being written to the same storage location. A newer generation number distinguishes it from the previous version. If the storage subsystem employs data striping, stripe size may be matched with the size of a logical collection of data (e.g., an extent), so that each such logical collection of data is wholly stored on just device in the storage subsystem. Concurrent device access may be supported by concurrently writing substripes of data to each device/extent.

Abstract: A method for rearranging a logical volume including arranging a logical volume rearranging program on a particular server and using the logical volume rearranging program to acquire server/storage mapping information from each server and performance information from each storage subsystem. Moreover, the logical volume rearranging program acquires request I/O (Input/Output) performance and a rearranging rule for each application set by a user. Furthermore, the logical volume rearranging program determines a destination by using the logical volume rearranging destination parity group specified by the user according to the aforementioned information, and rearranges the logical volume according to the storage subsystem performance and the request I/O performance of each application.

Abstract: A system, method and computer program product for virtualizing a processor and its memory, including a host operating system (OS); and virtualization software that maintains a virtualization environment for running a Virtual Machine (VM) without system level privileges and having a guest operating system running within the Virtual Machine. A plurality of processes are running within the host OS, each process having its own virtual memory, wherein the virtualization software is one of the processes. A host OS swap file is stored in persistent storage and maintained by the host operating system. The host OS swap file represents virtualized physical memory of the VM. A plurality of memory pages are aggregated into blocks, the blocks being stored in the host OS swap file and addressable in block form. The virtualization software manages the blocks so that blocks can be mapped to the virtualization software process virtual memory and released when the blocks are no longer necessary.

Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.

Abstract: Embodiments of the invention provide object-based tier management to improve the allocation of objects to different media of different speeds based on access characteristics such as access frequency. One embodiment is directed to a method of managing object-based data in an information system which includes an application server and a storage system. The method comprises receiving a write command including a first data to be written into a virtual volume; identifying an object to which the first data corresponds; checking if a second data corresponding to the object has been stored in the virtual volume; if the second data has been stored in a page of the virtual volume, checking if the page which stores the second data has a vacancy area; and if the page has a vacancy area, writing the first data in the page which stores the second data.

Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.

Abstract: One aspect of the present invention relates to techniques utilized within an operating system or a similar virtualization environment for reducing overhead of memory management data structures. Memory management data structures are used by operating systems to track the location of hardware pages in physical memory, consuming around 1% of a computer system's physical memory. However, these data structures may be classified as redundant when multiple data structures are used to track the same virtual memory pages stored within physical memory. One embodiment discloses an operation that identifies redundant data structures tracking frames of a single large page that are stored contiguously in the physical memory. Once identified, the redundant data structures may be removed from physical memory, freeing the physical memory for other uses. A further embodiment enables recreation of the removed data structures in physical memory if later accessed within the operating system.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: An underlying physical volume of a storage system is an aggregate having a plurality of storage devices. The aggregate has its own physical volume block number (pvbn) space. A file system layout apportions the underlying physical volume into a plurality of virtual volumes of the storage system each having a virtual volume identification (vvid). Each virtual volume has its own virtual volume block number (vvbn) space. The block allocation structures of a virtual volume are sized to the virtual volume, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the virtual volumes. Each storage block in a virtual volume is identified by the triplet: pvbn, vvid, and vvbn.

Abstract: A system, method, and program product are provided that identifies a cache set using Segment LookAside Buffer attributes. When an effective address is requested, an attempt is made to load the received effective address from an L2 cache. When this attempt results in a cache miss, the system identifies a segment within the Segment LookAside Buffer that includes the effective address. A class identifier is retrieved from the identified segment within the Segment LookAside Buffer. This class identifier identifies a cache set selected from the cache for replacement. Data is then reloaded into the cache set of the cache by using the retrieved class identifier that corresponds to the effective address.

Abstract: Bandwidth consumption between a data replication source and destination and storage consumption at the destination are reduced, when logical block mirroring is used with source deduplication, by eliminating repeated transmission of data blocks from source to destination. A reference is created for each data block at the source, the reference being unique within a storage aggregate of the source. During a mirror update, the source initially sends only the references of modified data blocks to the destination. The destination compares those references against a data structure to determine whether the destination already has any of those data blocks stored. If the destination determines that it already has a data block stored, it does not request or receive that data block again from the source. Only if the destination determines that it has not yet received the referenced data block does it request and receive that data block from the source.

Abstract: Management of a UNIX-style storage pools is enhanced by specially managing one or more memory management inodes associated with pinned and allocated pages of data storage by providing indirect access to the pinned and allocated pages by one or more user processes via a handle, while preventing direct access of the pinned and allocated pages by the user processes without use of the handles; scanning periodically hardware status bits in the inodes to determine which of the pinned and allocated pages have been recently accessed within a pre-determined period of time; requesting via a callback communication to each user process to determine which of the least-recently accessed pinned and allocated pages can be either deallocated or defragmented and compacted; and responsive to receiving one or more page indicators of pages unpinned by the user processes, compacting or deallocating one or more pages corresponding to the page indicators.

Abstract: A storage system is provided. The storage system comprises a storage media, a storage controller and a host. The storage controller is connected to the storage media. The host is connected to the storage controller, and performs a physical resource management algorithm for managing a physical resource of the storage media, so as to output at least a media operation command to the storage controller. The storage controller performs the media operation command to manage the storage media. A storage management method is also provided.

Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.

Abstract: An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller.

Abstract: Method and apparatus for ensuring a most recent version of data is retrieved from a memory, such as a non-volatile flash memory array. In accordance with various embodiments, a controller is adapted to sequentially store different versions of an addressable data block having a selected logical address in different locations within a memory. The controller assigns a revision indication value to each said version, with at least two of said stored versions concurrently sharing the same revision indication value. In some embodiments, the revision indication value constitutes a repeating cyclical sequence count that is appended to each block, or logically combined with a code value and stored with each block. The total number of counts in the sequence is less than the total number of versions resident in the memory.

Abstract: A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo logical volume and pseudo logical volume information associated with the pseudo logical volume, the pseudo logical volume being another of the logical volumes; and upon receipt of a command for canceling an assignment of one of the logical volumes to the corresponding recognition information, modifying the mapping information so that recognition information that has been indicative of said one of the logical volumes becomes indicative of the pseudo logical volume information associated with the pseudo logical volume.

Abstract: In order to prevent the degradation of performance of a storage apparatus caused by dynamic reallocation, the storage apparatus performs reassigning to a logical page the first physical page which is the physical page provided by the physical drive in Tier 1 which is the higher hierarchy than Tier 2 which is the hierarchy of the physical drive which provides the second physical page which is the physical page currently assigned to the logical page and, at the same time, by making the contents of the second physical page identical to the contents of the first physical page, performs the first migration for the logical page, associating and managing the second physical page and the first physical page and, when performing the second migration by reassigning the physical page provided by the physical drive in Tier 2 to the logical page to which the first physical page is assigned, and performs the second migration by reassigning the relevant second physical page to the logical page again when the second physical

Abstract: In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.

Abstract: A hypervisor prepares a guest region identifier (RID)-physical region identifier (RID) mapping table for dynamically registering and managing items and performs RID conversion using the guest RID-physical RID mapping table. When the mapping table is used, since it is unnecessary to provide a specific information area representing logical partitions (LPARs) corresponding to respective guests in an RID to be converted, there is no limitation concerning the number of LPARs and a problem in operation can be eliminated.

Abstract: A computer storage system is described. A range of volume block numbers (VBNs) is assigned to a volume. A range of storage device block numbers (DBNs) is assigned to each of a plurality of storage devices. A first mapping parameters are created to map a first range of VBN numbers to a first selected range of DBNs using a first portion of a new storage device. A second mapping parameters are created to map a second range of VBN numbers to a second range of DBNs on a second portion of the new storage device.

Abstract: What is provided is a load real address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction containing an opcode is obtained indicating that a load real address is to be performed. The instruction further identifies a first general register. Based on the contents of the machine instruction, a virtual address to be translated is obtained. Dynamic address translation is performed on the virtual address to obtain a segment-frame absolute address of a large block of data in memory. If an extended DAT facility and a format control field in the segment table entry are enabled, the address of the block of data is saved in the first general register. A page index portion and a byte index portion of the virtual address may also be saved in the first general register.

Abstract: A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host.

Abstract: A method for a storage controller to write a data block to one of a plurality of storage components is provided. The storage controller receives a write request from a host computer, and determines at least a portion of the data block includes a Logical Block Address (LBA) that is not currently mapped to a physical page of storage. The storage controller calculates availability for each storage component within the plurality of storage components, and selects the storage component with a highest calculated availability from the plurality of storage components. The storage controller next determines a next available physical page within the selected storage component. Finally, the storage controller writes the at least a portion of the data block including LBAs that are not currently mapped to a physical page of storage to the next available physical page.

Abstract: A management system detects a peak time period during which accesses are concentrated on a logical page included in a logical volume, and reallocates this logical page to an appropriate physical page. A management server detects an access variation of each logical volume, and selects a volume with a large access variation as a target volume. The management server measures the access status of each logical page in the target volume, and allocates a logical page to a more appropriate physical page.

Abstract: Systems and methods of monitoring logical block address (LBA) activity are disclosed. In an embodiment, a pattern of a data storage device may be monitored. An LBA may be detected that is accessed based on the pattern. The LBA may be added to a list of LBAs stored in a memory.

Abstract: A cache-aware Bloom filter system segments a bit vector of a cache-aware Bloom filter into fixed-size blocks. The system hashes an item to be inserted into the cache-aware Bloom filter to identify one of the fixed-size blocks as a selected block for receiving the item and hashes the item k times to generate k hashed values for encoding the item for insertion in the in the selected block. The system sets bits within the selected block with addresses corresponding to the k hashed values such that accessing the item in the cache-aware Bloom filter requires accessing only the selected block to check the k hashed values. The size of the fixed-size block corresponds to a cache-line size of an associated computer architecture on which the cache-aware Bloom filter is installed.

Abstract: A data storage device comprises virtual storage devices that are each assigned to a subset of data sectors in a non-volatile memory of the data storage device. The data storage device receives configuration metadata for configuring each of the virtual storage devices from a host operating system. The configuration metadata is received in a standard format that is file system independent. The configuration metadata comprises a range of logical block addresses and a virtual storage device number assigned to each of the virtual storage devices. Each of the virtual storage device numbers is a unique identifier used by the data storage device to differentiate between the virtual storage devices. The data storage device uses the virtual storage device numbers and logical block addresses to identify data sectors in the virtual storage devices that are accessible by virtual machine operating systems.

Abstract: An aspect of the invention relates to a method of managing data location of plural files in a storage system having a mixed volume which includes plural pages having a fixed page size, the pages belonging to different tiers. The method comprises mapping pages of different tiers to storage devices of different speeds in the storage system, the storage devices including at least a high speed storage device corresponding to a high tier page and a low speed storage device corresponding to a low tier page; and for each file that is a large file which is larger in size than the page size, performing sub-file tiered management on the large file to assign the large file among pages of different tiers according to access characteristics of different portions of the large file by matching the access characteristics of each portion of the large file with a corresponding tier of the assigned page of the mixed volume.

Abstract: Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.

Abstract: Power management functionality is described for implementing an application in an energy-efficient manner, without substantially degrading overall performance of the application. The functionality operates by identifying at least first data and second data associated with the application. The first data is considered to have a greater potential impact on performance of the application compared to the second data. The functionality then instructs a first set of hardware-level resources to handle the first data and a second set of hardware-level resources to handle the second data. The first set of hardware-level resources has a higher reliability compared to the second set of hardware-level resources. In one case, the first and second hardware-level resources comprise DRAM memory units. Here, the first set of hardware-level resources achieves greater reliability than the second set of hardware-level resources by being refreshed at a higher rate than the second set of hardware-level resources.

Abstract: Page tables in the last level of a hierarchical page table system are scanned for candidate page tables. Candidate page tables are converted to large pages, having a page table entry in a level before the last level of the hierarchical page table system adjusted to be associated with the newly created large page. Upon receiving a notification that a large page is to be converted into a page table, a new page table is created. Each entry in the new page table is associated with a small segment of memory in the large page and an entry in a page table one level before the last level in a hierarchical page table system is adjusted to be associated with the new page table.

Abstract: A computer system that generates a disposition instruction and an associated access command directed to a block of data at a logical address is described. The disposition instruction and the access command are communicated to a memory system in the computer system via a communication link. Note that the memory system includes different types of memory having different performance characteristics, and the disposition instruction is generated based on the different performance characteristics. In response to the access command, the memory system accesses the block of data at the logical address in a first type of memory in the different types of memory. Furthermore, based on the disposition instruction, the memory system moves the block of data to a second type of memory in the different types of memory to facilitate subsequent accesses to the block of data.