Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: Disclosed are a system, a method, and an article of manufacture to provide for configuring an automated data storage library having one or more storage frames that operate with different types of data storage media. The automated data storage library is configured to operate with sequential storage shelf addresses assigned to consecutive storage frames that use the same type of data storage media. The storage frames that operate with different types of data storage media may be physically assembled in any order. The automated data storage library may be expanded by attaching storage frames that operate with different types of data storage media in any order while maintaining sequential storage shelf addresses that span across multiple library frames.

Abstract: A global path identifier is assigned to each explicit route through a data communication network. The global path identifier is inserted into each packet as the packet enters a network and is used in selecting the next hop. When encountering a new selected path, an ingress router sends an explicit object to downstream nodes of the path to set up explicit routes by caching the next hop in an Explicit Forwarding Information Base (“EFIB”) table. Ingress routers maintain an Explicit Route Table (“ERT”) that tracks the global path identifier associated with each flow through the network. Multiple flows using the same path can be implemented by sharing the same global path identifier. In case of sudden network load changes, rerouting can be performed by changing the global path identifier associated with those flows that need to be rerouted and by then transmitting a new path object to downstream nodes.

Abstract: Exemplary systems and methods analyze cache data to detect a sequential workload to facilitate pre-fetching effectiveness. An exemplary address analysis module for sequential workload detection generates one or more addresses related to a host address. If the cache memory contains data corresponding to one or more of the related addresses, a sequential workload may be occurring, and a read pre-fetch operation may be triggered. An indexing module may be used to map host and related addresses to corresponding indices in cache memory.

Abstract: An apparatus and a method for controlling memory in a base station modem supporting multi-users including a memory divided into logical blocks for supporting the multi-users, and a controller for allocating the memory blocks dynamically in hardware. This allows non-continuous memory allocation and the size of memory can be increased or reduced during operation through the dynamic allocation structure of the memory.

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: A method and apparatus for compressing a reference pattern (RP) with repeated substrings by encoding produce compressed reference patterns (CRPs) with reduce storage requirements. Operation codes and a flag are stored with the CRPs. During comparison of reference elements of the CRP to input elements (IEs) of an input pattern (IP), the operation codes are read and the reference pattern is decoded allowing all reference elements including those of the repeated substrings to be compared to IEs in the IP to determine if the RP appears within the IP.

Abstract: A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Abstract: Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector gather and scatter operations. By contrast, one embodiment of the present invention implements gather and scatter operations using a plurality of deposit and extract instructions. As a result, gather and scatter operations may be efficiently performed within a general purpose processing environment and without the need for dedicated gather/scatter hardware.

Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.

Abstract: An SDRAM controller includes a service unit for receiving an SDRAM service request from at least one requester; a memory for storing instructions for performing a plurality of SDRAM transactions; and a lookup table of a sequence of addresses corresponding to at least a portion of the instructions stored in the memory, the portion of the instructions defining the SDRAM transaction. The service unit is configured to execute the SDRAM transaction based on the sequence of addresses in the lookup table. Also included is an arbiter for receiving service requests from multiple requestors to access the SDRAM, and another lookup table of identifiers corresponding to the multiple requestors, the identifiers stored in another sequence of addresses. The arbiter is configured to sequentially access each address in the other sequence of addresses, and grant service to a requestor based on an identifier stored in an address accessed.

Abstract: A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

Abstract: A processor may include a stack file and an execution core. The stack file may include an entry configured to store an addressing pattern and a tag. The addressing pattern identifies a memory location within the stack area of memory. The stack file may be configured to link a data value identified by the tag stored in the entry to the speculative result of a memory operation if the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.

Abstract: A hash table for a collection of data items includes a set of hash buckets, each hash bucket being associated with a subset of the collection of data items, and a set of properties entries in each of the hash buckets. Each properties entry includes a pointer to an associated data item in the subset associated with the bucket and a set of representative values identifying the associated data item. A hash table can also include bucket groups defining a second level hash table to permit resizing of the hash table.

Abstract: Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.

Abstract: An integrated memory contains an addressing unit for addressing memory cells for a memory access on the basis of received addressing signals. An addressing calculation logic unit is connected to the addressing unit. The latter can be activated by a test mode signal for a test operation of the memory. The addressing calculation logic unit receives command signals and address signals for the test operation, calculates therefrom the addressing signals for the memory access and feeds the latter into the addressing unit. After an initialization with the loading of initial parameters, the command signals and address signals for the test operation are applied to the addressing calculation logic unit and read/write operations are carried out by an access controller. An integrated memory with implemented BIST hardware, in the case of which a comparatively high functionality and flexibility during the memory test, are nevertheless made possible.

Abstract: An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0–CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0–CA2 being “don't care” bits assumed to be 000.

Abstract: A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.

Abstract: Each prefetch buffer has a tag register for storing a branch address and a data register for storing instruction data. Each of the prefetch buffers is assigned to either a first prefetch buffer rewritable during a normal operation period and a second prefetch buffer to be disabled for rewrite during the normal operation period. The second prefetch buffer can thus be prevented from being rewritten even if a central processor outputs branch addresses frequently. This realizes an improvement in the instruction fetch efficiency of the central processor and an improvement in the entire system performance. The fetch efficiency can be improved particularly in such systems that branch addresses occur frequently and some of them occur repeatedly.

Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

Abstract: A method of and system for memory access have address transformation circuitry for generating a single value of memory address from one or more corresponding values of an input quantity in which the number of values of the input quantity that correspond to a single value of the memory address varies across the range of values of the input quantity. The relationship between an input quantity and the corresponding memory address is a hyperbolic function.

Abstract: An array built-in, on-chip self test system for testing a memory array and a method of testing the memory array. The memory array has data input ports, data output ports, and address ports, and a data control subsystem, an address control subsystem, and a comparator. The data control subsystem generates and applies deterministic data patterns to the data input ports of the memory array. The address control subsystem generates addresses for application to the memory array in coordination with said data control subsystem, and includes a sequence counter, a count rate controller for the sequence controller, a count rate controller divider to control the number of cycles per address, an address controller to provide granular control of addresses, and an X-OR gate receiving an input from a sequence counter and from the address controller, the X-OR gate outputting an address bit to the memory array.

Abstract: A method for generating sequences of memory addresses for a memory buffer having N*M locations includes making a first address and a last address of every sequence respectively equal to 0 and to N*M?1, assigning a first sequence of addresses, and each address but a last address of another sequence of addresses is generated by multiplying a corresponding address of a previous sequence by N, and performing a modular reduction of this product with respect to N*M?1. The method further includes calculating a greatest bit length of every address, and calculating an auxiliary constant as the modular reduction with respect to N*M?1 of the power of two raised to twice the greatest bit length.

Abstract: A circuit for recording digital waveform data includes (a) a first counter which counts the number of data constituting a first data sequence including a plurality of data different from one another, (b) a second counter which counts the number by which the same data is repeated to constitute a second data sequence, (c) a memory which stores all of data constituting the first data sequence and one of data constituting the second data sequence in this order together with the number counted by the first counter and the number counted by the second counter, and (d) a controller which transmits an address signal to said memory, and controls operation of the first and second counters.

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Abstract: To provide a storage device capable of shortening a formatting time and a data recording time, and an information processing system, method and program. The storage device of the invention has at least one storage medium 40, storing means 32 for storing plural patterns of format data for each pattern, receiving means 34 for receiving a sector address specifying a sector of the storage medium 40 to be written and a pattern identifier specifying a pattern of the format data to be written, and writing means 36 for reading the format data having the pattern corresponding to the pattern identifier from the storing means 32 and writing the read format data into the sector of the storage medium 40 corresponding to the received sector address.

Abstract: Systems and methods for backup of data in redundant data storage systems. In this regard, one embodiment can be broadly summarized by a representative system that copies a block of data from a primary storage unit to a primary backup storage unit using a primary addressing sequence that begins with a first start address; and substantially concurrently copies a second block of data from a secondary storage unit to a secondary backup storage unit using a secondary addressing sequence that begins with a second start address. Another embodiment can be described as a method wherein the first start address is the same as the second finish address; the primary addressing sequence uses an incrementing count, and the secondary addressing sequence uses a decrementing count. Other systems and methods are also provided.

Abstract: A system may include a memory file and an execution core. The memory file may include an entry configured to store an addressing pattern and a tag. If an addressing pattern of a memory operation matches the addressing pattern stored in the entry, the memory file may be configured to link a data value identified by the tag to a speculative result of the memory operation. The addressing pattern of the memory operation includes an identifier of a logical register, and the memory file may be configured to predict whether the logical register is being specified as a general purpose register or a stack frame pointer register in order to determine whether the addressing pattern of the memory operation matches the addressing pattern stored in the entry. The execution core may be configured to access the speculative result when executing another operation that is dependent on the memory operation.

Abstract: Briefly, embodiments of the invention provide an architecture including two or more stack memories defined on separate memory banks. An apparatus in accordance with embodiments of the invention may include, for example, a processor associated with two stack memories defined on separate single-access memory banks. Embodiments of the invention further provide a method of compilation including, for example, allocating a first variable to a first memory bank and allocating a second variable to a stack memory defined on a second memory bank.

Abstract: A signal processor including a processor having a cache memory and a process execution unit executing a process by use of information temporarily stored in the cache memory and an external memory provided external to the processor. In the signal processor, the process execution unit automatically returns to a start point of a loop-type data at an end of the loop-type data and sequentially reads out the loop-type data from the external memory to the cache memory.

Abstract: A method of creating a discontiguous address plan for an enterprise is provided which includes determining a hierarchy of routing optimization for an enterprise, determining a number of route advertisement aggregation points at each level of the hierarchy, determining a number of network security policy areas for the enterprise, and determining a number of addresses for each of the network security policy areas. The number of addresses is rounded up to a power of the address scheme base number to produce a plurality of rounded addresses. The method further includes allocating an address range for each of the plurality of rounded addresses so that a starting address of the address range begins on a power of the base number and determining a size of the plurality of address ranges. The size of the plurality of address ranges is rounded up to a power of the base number to produce the size of a repeating policy pattern.

Abstract: An apparatus and method are provided for updating one or more pluralities of pointers (i.e. one or more vector pointers) which are used for accessing one or more pluralities of data elements (i.e. one or more vector data elements) in a multi-ported memory. A first register file holds the vector pointers, a second register file holds stride data, and a plurality of functional units combine data from the second register file with data from the first register file. The results of combining the data are transferred to the first register file and represent updated vector pointers. Furthermore, a third register file is provided for holding modulus selector data to specify the size of a circular buffer for circular addressing.

Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

Abstract: An apparatus and method of line coding to mitigate collision induced errors in Wavelength Division Multiplexing (WDM) optical communications systems is disclosed. The apparatus and method prevents Soliton-Soliton-Collision induced errors by reducing a variance in a number of possible collisions between solitons in multiple channels in a WDM fiber optic communication system using a sliding window criterion. The sliding window criterion defines a set of parametric values based on physical properties of the transmission network, a transmission frequency and a defined data block size. N-bit codes are iteratively selected and sequentially assigned to segments of a mapping table indexed by all possible unique combinations of “1”s and “0”s in a block of data. Input data blocks are mapped to corresponding code words having a reduced number of transitions for transmission on the fiber optic network. Received code words are converted back to a data stream corresponding to the input data stream.

Abstract: A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.

Abstract: A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.

Abstract: In one embodiment of the present invention, there is disclosed, a method of handling data which is being written to and stored in flash memory, wherein input data, comprising information data and overhead data, undergoes a reversible transformation before being written to flash memory whereupon each bit stored in flash memory, as flash data, is a function of both information data and header data.

Abstract: The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A system for the detection and support of data streams is disclosed. The system determines whether new commands comprise a data stream. If a new data stream is detected, the system next determines whether adequate resources are available to launch the new data stream. If the system determines that the data stream can be launched, system resources, particularly cache memory space, are assigned to the data stream to provide the data stream with the necessary amount of data throughput needed to support the data stream efficiently. The data stream's throughput is the amount of data that the stream requires per unit time. The system monitors all supported data streams to determine when a particular data stream has terminated, at which time resources dedicated to the data stream are released and become available to support other data streams. The cache for each supported data stream is maintained at as full a level as possible, with the cache for the “least full” data stream given priority for refresh.

Abstract: Methods and apparatus for accessing memory locations in a memory device in different orders. In one implementation, a memory device includes: a memory array, including a plurality of memory locations divided into memory pages, where each memory location has a row address and a column address; a row decoder connected to the memory array for selecting a row address in the memory array; a column decoder connected to the memory array for selecting a column address in the memory array; and a multi-sequence address generator for generating addresses, where the multi-sequence address generator has a burst mode and in burst mode generates one of two or more burst sequences of addresses according to received burst parameters, and where each sequence has an index indicating the separation between two addresses in the sequence.

Abstract: Counter control section 101 increments a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers as the read address values, bit inversion apparatus 102 performs bit inversion using the read address values as inputs, column conversion section 103 outputs the address values corresponding to the bit inversion output values and the column numbers from counter control section 101 as the column conversion values, shift register 104 bit-shifts the output values of bit inversion apparatus 102 and outputs as the address offset values, adder 106 adds up the address offset values and column conversion values and size comparison section 106 compares the addition value with the interleave size and outputs data which is not greater than the interleave size as address values.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAM 300 when a request is made to access the SDRAM 300, without deactivating the accessed row, until a detection signal that detects the last column is asserted. The SDRAM access control section deactivates the accessed row when the detection signal is asserted.

Abstract: To provide a method of using a memory that can contribute to an efficient SIMD operation. The method of using the memory includes the steps of: supposing a predefined two dimensional memory space consisting of predefined virtual minimum two dimensional memory spaces 1 arranged in longitudinal and transverse directions; and preassigning each address of the virtual minimum two dimensional memory space 1 to an address in each of n physical memories determined in relation with the virtual minimum two dimensional memory space.

Abstract: In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.

Abstract: There is disclosed a method and apparatus for mapping between logical and physical addresses in a solid state data storage device, particularly but not exclusively a magnetic random access solid state data storage device, in which a list of mappings between ranges of logical addresses and ranges of physical addresses are stored in a data table, the mappings being operated on to look up a physical address from a logical address and vice versa, and being operated on by a data processor, to amend the data mappings by introduction of new ranges of logical and physical addresses, upon ranges of individual physical memory elements becoming defective.

Abstract: A method comprising reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device and ignoring said certain address bits before inputting at least one n-bit word into said memory array. The method may additionally comprise examining at least two of the least significant bits of a column address and wherein said reordering is responsive to said examining step. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0-CA2 identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0-CA2 being “don't care” bits assumed to be 000.

Abstract: A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on the memory banks being operable independently. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth in one of the banks. After all data have been written into or read from the specified memory cells, corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.