Abstract: A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing.

Abstract: In some applications, such as video motion compression processing for example, a request pattern or “stream” of requests for accesses to memory (e.g., DRAM) may have, over a large number of requests, a relatively small number of requests to the same page. Due to the small number of requests to the same page, conventionally sorting to aggregate page hits may not be very effective. Reordering the stream can be used to “bury” or “hide” much of the necessary precharge/activate time, which can have a highly positive impact on overall throughput. For example, separating accesses to different rows of the same bank by at least a predetermined number of clocks can effectively hide the overhead involved in precharging/activating the rows.

Abstract: When a concentration of access requests on a specific bank occurs, the delay time is caused due to the competition among the accesses, thereby lowering the processing speed of an information processing apparatus as a whole. A data transfer arbitration unit 172 sequentially transfers data to be recorded to a memory controller 160 that records data in memory having a plurality of banks. A selector 174 selects any DMAC 170 from among a plurality of DMACs, irrespective of priority sequence of transfer service for the DMAC. A transmitter 176 transmits, to a control-side transfer unit 114, data requested to be transferred by the selected DMAC 170. The selector 174 selects consecutively the DMAC 170 so that the transfer service for the same DMAC is consecutively executed, and determines the number of consecutive selections so that a transfer across the banks of the DMAC 170 occurs by a plurality of the transfer services.

Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

Abstract: Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.

Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

Abstract: Method and systems are disclosed for increasing the number of ranks supported in a memory system. In one embodiment, a plurality of predefined subsets of memory chips on a memory module is selected. A chip select signal uniquely identifying the selected subset of memory chips is generated. The chip select signal is encoded as a multi-bit word having a bit width that is less than the number of predefined subsets of memory chips. Each bit of the encoded chip select signal is transmitted along a separate chip select line. The transmitted chip select signal is decoded to determine the identity of the selected subset of memory chips. The selected subset of memory chips identified by the decoded chip select signal are read or written.

Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.

Abstract: A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements.

Abstract: A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group.

Abstract: A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.

Abstract: A memory module including a plurality of memory channel connectors for communicating with a memory controller via a plurality of high-speed channels. The memory module also includes a plurality of memory devices arranged in one or more ranks, and a plurality of independently operable hub devices. Each hub device includes an interface for receiving signals from and driving signals to the memory controller on one of the high-speed channels via one or more of the memory channel connectors. Each hub device also includes a plurality of independently operable ports to communicate with all or a subset of the ranks of memory devices.

Abstract: A system, memory hub device, method and design structure for providing an enhanced cascade interconnected memory system are provided. The system includes a memory controller, a memory channel, a memory hub device coupled to the memory channel to communicate with the memory controller via one of a direct connection and a cascade interconnection through another memory hub device, and multiple memory devices in communication with the memory controller via one or more cascade interconnected memory hub devices. The memory channel includes unidirectional downstream link segments coupled to the memory controller and operable for transferring configurable data frames. The memory channel further includes unidirectional upstream link segments coupled to the memory controller and operable for transferring data frames.

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract: A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses.

Abstract: A method and apparatus for exchanging information between components coupled with an a I2C bus via separate banks. In one embodiment, the apparatus is for use in a wireless communication system for communicating with a wireless network and comprises a host processor having an I2C interface, a transceiver having an I2C interface, a physical interface coupling the host processor and the transceiver, the physical interface having an I2C bus coupled to the I2C interface of both the host processor and the transceiver and multiple separate banks of memory accessible by the host processor and the transceiver to exchange information between the host processor and the transceiver, where the host processor and the transceiver access the plurality of banks of memory via their respective I2C interfaces.

Abstract: In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.

Abstract: A semiconductor memory device, including a memory banks and associated local data buses, and a bus connection circuit connected to the local data buses associated with two or more of the memory banks to perform a selective data transfer between a global data bus and those local data buses.

Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.

Abstract: A storage controller includes a CPU for controlling each component in the storage controller; a ROM for storing programs executed by the CPU and data required for this execution; a RAM employed as a work area when the CPU executes the programs; a first ASIC (USB system) for controlling data transfers based on the USB standard; slots in which can be inserted various external memory units; a second ASIC (external memory system) for controlling data accesses to the external memory units to read data therefrom or write data thereto; and an address bus and a data bus connecting these components to one another.

Abstract: Systems and methods for providing memory modules with multiple hub devices. Exemplary systems include a cascade-interconnect memory system with a memory bus, a memory controller and a memory module. The memory controller is in communication with the memory bus for generating, receiving and responding to memory access requests. The memory module includes a first hub device with three or more ports and a second hub device with three or more ports. A first port on the first hub device is in communication with the memory controller via the memory bus, a second port on the first hub device is in communication with a first set of memory devices, and a third port on the first hub device is cascade connected to a first port on the second hub device. A second port on the second hub device is in communication with a second set of memory devices and a third port on the second hub device supports a cascaded connection to a subsequent hub device in the memory system.

Abstract: A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device.

Abstract: A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mapping logic (140) within the memory device. The configuration of the mapping logic, also known as a mapping scheme, is defined by data stored in mapping specifying data storage (150), which may be altered by operating system software or application software (160) running on the system. Altering this configuration may be as a result of signals received from a monitoring unit (135) which monitors the efficiency with which the current mapping scheme is accessing data stored in the memory device. More than one mapping scheme may be used within a single memory device.

Abstract: A semiconductor device employs a SESO memory or a phase change memory which has a smaller memory cell area than SRAM. The semiconductor device has a plurality of memory banks each composed of the SESO or phase change memories, and a cache memory which has a number of ways equal to the ratio of a write speed (m) to a read speed (n). The semiconductor device controls the cache memory such that a write back operation is not repeated on the same memory bank.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Abstract: A memory flush is processed in accordance with a state machine that keeps track of the flush states of a memory target. A memory target is not flushed if it has not been written to, or if a memory flush has already been completed for that memory target. A memory target is flushed if the memory partition is in a flush needed state or a flush pending state. Each memory target has an associated state machine, but only one state machine is maintained per memory target.

Abstract: A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Abstract: A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.

Abstract: A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: Described is a high speed nonvolatile memory device and technology that includes a controller coupled via interfaces to sets of nonvolatile storage, such as separate flash memory chips or separate regions of a single chip. The controller includes logic that processes write requests of arbitrary size, by interleaving writes among the interfaces, including by parallel writing among the interfaces. For example, the data may be received via direct memory access (DMA) transfers. The controller maintains information to allow the interleaved data to be reassembled into its correct relative locations when read back, such as by DMA. The high speed nonvolatile memory device thus provides a hardware device and software solution that allows a personal computer to rapidly boot or resume from a reduced power state such as hibernation. The high speed nonvolatile memory device also may be used for other data storage purposes, such as caching and file storage.

Abstract: An electronic tag system, an electronic tag, and a controlling method thereof according to the present invention include an electronic tag that includes a memory having a divided band and a bank status that stores a status of data stored in the divided bank, a controlling circuit that reads and writes the data from and to the bank and changes the status and a controlling device that allows the controlling circuit connected through the electronic tag and an electronic tag reader/writer to transmit and receive the read and written data from and to the bank and issue an instruction to change the status.

Abstract: A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh logic performs a refresh to a portion of the memory array specified, at least partially, by the portion specifying signal. Data transfer interfaces receive data transfer commands and transfer memory to and from the apparatus. Another apparatus includes refresh control logic to output a refresh signal and a portion specifying signal via a refresh command interface.

Abstract: A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.

Abstract: A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.

Abstract: In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

Abstract: The present invention relates to a method for scheduling and controlling access to a multibank memory having at least two banks, and to an apparatus for reading from and/or writing to recording media using such method. According to the invention, the method comprises the steps of: writing an input stream to the first bank; switching the writing of the input stream to the second bank when a read command for the first bank is received; and switching the writing of the input stream back to the first bank when a read command for the second bank is received.

Abstract: Various embodiments of the invention may use one or more programmable non-volatile registers in each memory device to provide a separate device address for that device. These registers may be programmed at various points in the manufacturing and distribution cycle, such as but not limited to the memory chip factory, an original equipment manufacturer (OEM), or in the field. In some embodiments, other types of information (e.g., configuration information for the memory device) may also be programmed in this manner.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: A method, a system, an apparatus, and a computer program product are presented for a fragment caching methodology. Within the request path from a client to a server, a first computing device may attach to a request message a message header that indicates that the first computing device supports fragment processing; a second computing device within the request path processes this request message. When the second computing device receives a response message corresponding to the request message, it can check for a message header directive that indicates that it should cache the response message's fragment only if the response path does not have at least one computing device that supports the processing of fragments; if so, then it forwards the response message without caching its contained fragment.

Abstract: Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.

Abstract: A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller receives and responds to memory access requests including memory update requests from a processor. The memory controller also generates a memory update command in response to receiving a memory update request. The memory hub device includes a first port, a second port and a control unit. The first port is in communication with the memory controller via one or more of the memory busses for transferring data and control information between the memory hub device and the memory controller. The second port is in communication with one or more of the memory devices.

Abstract: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.

Abstract: A method of recovering the state of a system, which system comprises at least one counter, which counter represents an instantaneous state of an entity in a system. The counter will increase in value in response to an increment request and decrease in value in response to a decrement request, wherein each increment request is paired with a decrement request.

Abstract: A memory system includes a plurality of memory devices arranged in sets on at least one memory module, each set including at least one memory device. In some embodiments, the system further includes respective dedicated serial data and control busses configured to couple respective ones of the memory device sets to a memory controller external to the at least one memory module. The dedicated serial data and control busses may be configured to provide unbuffered access to the individual memory devices from the memory controller. In other embodiments, dedicated data busses are provided to an external control buffer and dedicated control busses are provided to a control buffer in the module.