Abstract: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: The invention provides a code memory capable of code provision for a plurality of physical channels. In one embodiment, the code memory comprises a selecting multiplexer, a core memory module, and a code buffer. The selecting multiplexer repeatedly latches on to a plurality of addresses generated by the physical channels according to a sequence of the physical channels to generate a code memory address signal. The core memory module stores code data, and retrieves the code data according to the code memory address signal to generate a code memory data signal. The code buffer respectively retrieves a plurality of code segments requested by the physical channels from the code memory data signal according to the sequence of the physical channels, and stores the code segments.

Abstract: A process and system for virtually managing enclosures. A process determines whether a system includes an enclosure processor, a virtual enclosure processor, or both an enclosure processor and a virtual enclosure processor. The process receives a command by a virtual enclosure processor if it is determined that the system includes the virtual enclosure processor. The virtual enclosure processor manages a peripheral in an enclosure. Additionally, a process activates a virtual enclosure processor in a system including a real enclosure processor. The virtual enclosure processor receives a command. The virtual enclosure processor controls a peripheral.

Abstract: A system and a method for data storage means includes a set of data storage sub-assemblies and connectable to storage control means adapted to retrieve, for a plurality of simultaneous user applications, data stored in the data storage means. The method divides a data composition into a plurality of payload data subsets, and stores the payload data subsets in the data storage sub-assemblies. The storage control means is adapted to retrieve, for a user application, the payload data subsets in a predetermined retrieving sequence, wherein a sequence of a number of payload data subsets, which number corresponds to the number of data storage sub-assemblies in the set of data storage sub-assemblies, and which payload data subsets follow sequentially one immediately upon the other in the retrieving sequence, are stored in separate ones of the data storage sub-assemblies in the set of data storage sub-assemblies.

Abstract: Fixed-length data (560) contained in a database (560) are segmented into a number of pieces of data that are searchable at a time and searching is performed at high speed. As means for it, a pointer table (500), a secondary pointer table, a local table, and a fixed-length-data table are provided, and when more segmentation is required, a table having a numeric-value comparing function is further provided. As means for performing efficient configuration/management of the tables and for performing management that does not interfere with a search operation, an empty-house table (700), an empty-room table (720), a room-management table (740), and a structure-management table (760) may be provided.

Abstract: A method and apparatus to facilitate low-power consumption through a configurable suspend mode of operation of a PLD, the PLD comprising an application logic block coupled to receive configuration data bits and adapted to implement a logic application in response to the configuration data bits, a suspend pin coupled to receive a suspend signal, a write protect block coupled to the application logic block and adapted to prohibit the application logic block from changing logic states in response to a suspend mode initiated by the suspend signal; and an awake pin adapted to provide an awake signal that is indicative of a status of the suspend mode.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: A system and method is disclosed for improving data integrity and the efficiency of data storage in separate memories of a computing device. In particular, the present invention introduces a combination of two types of memory, namely, an NVRAM and a Flash memory, as persistent memory for storing file data. By constantly caching a last data portion of a data file in an NVRAM, it avoids any sector erasing for individual bits in a Flash memory. Such an approach increases the data storage efficiency and life expectancy of a Flash memory. The present invention has very broad application in almost all computing devices, including any PC (desktop or laptop) and server computers. It demonstrates particularly advantageous performance in portable electronic devices implementing Windows™ CE operating systems.

Abstract: A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware.

Abstract: A memory interface allows access SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n(n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract: Methods and apparatus of the present invention include new data and parity mapping for a two-level or hierarchical secondary RAID architecture. The hierarchical secondary RAID architecture achieves a reduced mean time to data loss compared with a single-level RAID architecture. The new data and parity mapping technique provides load-balancing between the disks in the hierarchical secondary RAID architecture and facilitates sequential access.

Abstract: A data storage system comprises a first data storage medium and a second data storage medium. The first and the second data storage media are different types of data storage media. The data storage system assigns a first range of logical block addresses to physical addresses in the first data storage medium. The data storage system is configured to dynamically reassign the first range of logical block addresses to physical addresses in the second data storage medium. Alternatively, the data storage system can assign a first range of logical block addresses to physical addresses in the first data storage medium and to physical addresses in the second data storage medium. The data storage system stores data associated with the first range of logical block addresses in both of the first and the second data storage media. One of the data storage media can be NAND Flash memory.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A system and method for enabling a programmable device to execute instructions without interruption. An instruction space for storing instructions from a host application is bifurcated to define a program segment and a hold segment. At startup, instructions are loaded into the hold segment, and the programmable device begins executing those instructions. While the hold segment instructions are executed, the program segment is loaded with instructions. Once the program segment is filled, control is shifted to it and instructions from this segment are executed by the programmable device. When the program segment has been executed, control is shifted back to the hold segment, and instructions are taken from it while the program segment is reloaded with a fresh set of instructions from the host application. Once the program segment is reloaded, control is redirected and execution of instructions from the program segment is continued.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A method for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I/O transaction is provided. The present invention also provides a method, computer program product, and distributed data processing system for directly creating and initializing one or more virtual resources that reside within a physical adapter, such as a PCI, PCI-X, or PCI-E adapter, and that are associated with a virtual host. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O adapters, PCI-Express I/O adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for host to adapter communications.

Abstract: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract: A system for a distributed database implementing a dynamic mastership strategy. The system includes a multiple data centers, each having a storage unit to store a set of records. Each data center stores its own replica of the set of records and each record includes a field that indicates which data center is assigned to be the master for that record. Since each of the data centers can he geographically distributed, one record may be more efficiently edited with the master being one geographic region while another record, possibly belonging to a different user, may be more efficiently edited with the master being located in another geographic region.

Abstract: A DRAM command scheduling algorithm is presented that is designed to alleviate various constraints imposed upon high performance, high datarate, short channel DDRx SDRAM memory systems. The algorithm amortizes the overhead costs of rank-switching time and schedules around the tFAW bank activation constraint. A multi-rank DDRx memory system is also presented having at least two ranks of memory each having a number of banks and at least one memory controller configured for performing the hardware-implemented step of DRAM command scheduling for row access commands and column access commands. The step of command scheduling includes decoupling the row access commands from the column access commands; alternatively scheduling the decoupled row access commands to different ranks of memory; and group scheduling the decoupled column access commands to each bank of the number of banks of a given rank of the different ranks of memory.

Abstract: A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to positional information of memory chips of the memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Abstract: A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another.

Abstract: A controller, in particular an Ethernet controller has a control unit operable to receive commands and data through an I/O interface; a plurality of registers arranged in a register block which is divided into a plurality of register banks, wherein at least one register controls a function of the controller; a register address unit having logic for accessing one of the plurality of registers by a plurality of addressing schemes, wherein the addressing schemes at least has a direct address provided by received data, a combined address provided by a partial address from a received command and a bank address stored in a bank register, and an address selected form a plurality of predetermined addresses through a received command.

Abstract: A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller increases the number of cycles for issuing command/address signals, and if it is determined that the load level is low, the memory controller reduces the number of issuing cycles.

Abstract: A memory access control device enabling freer access from a plurality of ports to a plurality of memories and a processing system having the same are provided. From among addresses generated at a read address generation unit and addresses input from an external bus, the address which is supplied to a local memory (LM) is selected in accordance with configuration information supplied by a configuration information storage unit. Addresses correspond to ports. Lower bits thereof instruct the storage region inside the LM, and upper bits instruct the LM to be accessed. The read data to be output to a port is selected from among the read data of a plurality of LMs in accordance with the upper bits of this address.

Abstract: A memory system comprising memory modules including memory chips including integrated switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a switching circuit within a memory chip detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: An enhanced mechanism for the allocation, organization and utilization of high performance block storage metadata provides a stream of data (e.g., in a server system, storage system, DASD, etc.) that includes a sequence of fixed-size blocks which together define a page. Each of the fixed-size blocks includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. Each footer in the confluence of footers has space available for application metadata, which are provided as one or more information units. At least one of the footers includes a Checksum field containing a checksum that covers at least the confluence of footers. This approach is advantageous in that it provides data integrity protection, protects against stale data, and significantly increases the amount of metadata space available for application use.

Abstract: One embodiment is directed to a method and apparatus for modifying a configuration of a computer system including a host computer and at least one computer system resource accessible to at least one application program executing on the host computer. The computer system is dynamically reconfigured, without reinitializing the host computer or the application program, to alter a manner in which the at least one application program accesses the at least one computer system resource. Another embodiment is directed to a method and apparatus for responding to changes in a configuration of the computer system impacting a manner in which the at least one computer system resource is accessed by the host computer. Information relating to a first configuration of the computer system at a first point in time is stored, the first configuration relating to a first manner of accessing the at least one computer system resource by the host computer.

Abstract: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

Abstract: A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

Abstract: A method for managing a memory device, a memory device so managed and a system that includes such a memory device. A value of a longevity parameter of the device is monitored after a data operation on the device in which the monitoring is performed by the device. A grade of the device is derived from the value. Preferred longevity parameters include a ratio of successfully-processed data to unsuccessfully-processed data and a deviation in a power consumption of the device. The grade serves as a forecast of a life expectancy of the memory. Preferred grades include: a comparison grade, a maximum grade, and an average grade.

Abstract: From among identical modules stored on a module storage 112 and a module storage 212, an authenticated printing management module 130 selects the module with higher level information. For example, an ID authentication module 132 is stored in both the module storage 112 of an MFP 10 and the module storage 212 of a network interface card 11. The authenticated printing management module 130 selects the ID authentication module of the network interface card 11, in accordance with level information that represents an ID authentication module selection hierarchy. By so doing, where modules necessary for executing authenticated printing are included on both the MFP 10 and the network interface card 11, modules present on either the MFP 10 or the network interface card 11 are able to be selected appropriately for use.

Abstract: A precharge signal generation circuit outputs a precharge signal including a pulse every access cycle with respect to a data register in a first mode, and generates a precharge signal by masking the signal including the pulse every access cycle with respect to the data register when access to a memory cell other than a predetermined memory cell in the data register is designated in a second mode. A first precharge circuit precharges a bit line pair in response to activation of the precharge signal.

Abstract: The present invention provides a high-performance storage access environment to a user who moves around a wide area, while increasing the fault resistance of the system. A plurality of network storages (volumes) is assigned to the user. Then, at the occasion of logging in to a volume by the user, the volume that can be accessed with high performance from a position he made access is located. Addresses at a computer with which user makes access are associated with addresses of the volumes provided by a storage device in advance in an assigned volume management table so as to increase access performance. Then, a management server performs control so that the address of the volume associated with the user access position is returned as a response, at the time of logging in.

Abstract: A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a portion of the data for a memory transaction. If a memory unit is determined to be defective, one portion of the memory bus may be inactivated for hot swapping of memory, and the system can continue to operate using an active portion of the memory bus.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A method and system are provided for providing a consistent reintegration of a failed primary instance as a new secondary instance with implementation of truncation of log records. Upon failure of a primary instance, a secondary instance may be reassigned as the new primary instance. Prior to reintegration, any portion of the database log of the failed primary that is after the log position of the new primary instance may be truncated, followed by a comparison of the log positions of both the new primary instance and the new secondary instance. In limited circumstances, the truncation of the log data generated by the failed primary instance after the point of failure is possible, and supports reintegration of the failed primary as a new secondary instance with limited overhead.

Abstract: A DRAM controller may be configured to re-order read/write requests to maximize the number of page hits and minimize the number of page conflicts and page misses. A three-level prediction algorithm may be performed to obtain auto-precharge prediction for each read/write request, without having to track every individual page. Instead, the DRAM controller may track the history of page activity for each bank of DRAM, and make a prediction to first order based history that is not bank based. The memory requests may be stored in a queue, a specified number at a time, and used to determine whether a page should be closed or left open following access to that page. If no future requests in the queue are to the given bank containing the page, recent bank history for that bank may be used to obtain a prediction whether the page should be closed or left open.