Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A data structure design system for prolonging the life of an FRAM (Ferroelectric Random Access Memory) includes a CPU (Central Processing Unit) (1), an FRAM (2), an SDRAM (Synchronous Dynamic Random Access Memory) (3), and a clock (4). The FRAM is divided into a plurality of fixed-size blocks, and is for storing data. The SDRAM is for storing data that need to be written to the FRAM, and includes three data structures: queue one, queue two, and hash table. The CPU is for reading data from external storages, storing the data in the SDRAM, reading data from the SDRAM, and writing the data to the FRAM via the three data structures. The clock is for recording a predetermined time used to determine the blocks in the FRAM in which data have not been read up to the predetermined time. A related data structure design method is also provided.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Abstract: Briefly, in accordance with an embodiment of the invention, a method to store information is provided, wherein the method includes generating a storage parameter to store information, wherein the storage parameter indicates use of the information by a software process and transferring the information to one of at least two memory devices based at least in part on the storage parameter and on a characteristic of the two memory devices.

Abstract: Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.

Abstract: An instruction memory shared by a number of processing units has a plurality of individually accessible sections. A software program in the instruction memory is distributed among the memory sections. Sequential parts of the software program are in sequential sections. The software program may have a common portion which is repeated in each of the memory sections. Arbiter logic may control which of the processing units accesses which of the memory sections in each memory access cycle.

Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data bits and output a pair of data bits onto the internal bus each half clock cycle.

Abstract: A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device.

Abstract: In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each decoder of a given memory controller may be independently configurable to match on a respective value of a subset of address bits such as the low-order cache line address bits, for example, received in a memory request. In one specific implementation, the number of decoders included on a given memory controller may correspond to the number of ways in which the memory is interleaved.

Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

Abstract: A random number generator, for generating random numbers, includes: a first processing module for generating at least one candidate number array comprising a plurality of candidate numbers respectively corresponding to a plurality of candidate addresses; an address generating module for generating at least one specific address according to at least one generator polynomial, where each specific address is a candidate address within the plurality of candidate addresses; and a second processing module, coupled to the first processing module and the address generating module, within the candidate number array sent from the first processing module, the second processing module selecting the candidate number(s) corresponding to the specific address as random number(s).

Abstract: The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a read-register specification and a read-register scan direction; a read control circuit for executing control to rearrange a plurality of pieces of read data, which is read out from the memory banks in accordance with the read addresses, on the basis of the read-register specification and a read-register displacement; and a processing unit for carrying out a plurality of operations on the rearranged pieces of read data output by the read control circuit.

Abstract: Methods and computer readable media are provided for implementing state machines in parallel. A control vector is generated from current state and input bits. This vector is then used to determine the next state and any output bits for each of a plurality of state machines in parallel. In some implementations, the Altivec vperm instruction is used to perform a parallel table look-up.

Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Abstract: There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In the multi-port memory device having a data transmission/reception block (bank, port, global data bus connection block, etc.) which exchanges data with the global data bus in a current sensing type data transmission/reception structure, an initialization switch is used to discharge each global data bus line and an initialization signal generator controls the initialization switch. A first high data fail at the initial operation is caused by a high precharge level of the global data bus. According to the present invention, it is possible to lower a high precharge level without causing a problem in data transmission.

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract: A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 0 to N?1 and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2m×J; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2m(K mod J)+BROm(K/J), where K (0?K?(N?1)) denotes a reading sequence, BROm(y) is the bit-reversed m-bit value of y and / is a function in which a quotient of K divided by d is obtained, the quotient being an integer.

Abstract: A user-friendly data processing system apparatus which ensures the expandability of memory capacity and high speed processing with low cost is provided. The data processing system is composed of a data processing unit, a volatile memory and a nonvolatile memory. The data processing unit, the volatile memory and the nonvolatile memory are connected in series and by reducing the number of connection signals fast processing is realized while maintaining the memory capacity expandability. Upon transferring a data of the nonvolatile memory to the volatile memory, an error correction is executed, therefore, the reliability is improved. The data processing system composed of the plurality of memory chips is formed as a data processing system module in which the each chips are stacked and arranged, and wiring is formed by ball grid array (BGA) and bonding between the chips.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

Abstract: A write-bank selecting unit selects different memory banks in response to N+1 consecutive write requests, respectively. In each memory cycle, a data writing unit inputs N or less write commands to a data access unit. On the other hand, a primary read-bank selecting unit selects readable memory banks in each memory cycle. A secondary read-bank selecting unit selects memory banks corresponding to read requests for which data blocks could not be read out in the preceding memory cycle. A data reading unit generates read commands for those read banks and inputs the generated read commands to a data access unit. With this configuration, a packet buffer capable of satisfying both of short processing cycles and high memory use efficiency can be provided by using memory devices at a relatively low price.

Abstract: In order to manage the various types of attribute information within the storage system, the storage system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage system receives an access request to a file, the utilization of these databases allows the storage system to make the access to the access-target file.

Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: A moving picture processing apparatus in which a buffer residual amount of a buffer module which buffers a plurality of image data which are inputted from the outside is monitored by a storing media control module and a decimation is performed at a decimation ratio which differs every image data, in accordance with the buffer residual amount of the buffer module and in accordance with the frame rate of each of the plurality of image data, so that it can be prevented the inconvenience that a period of time during which the image data is not recorded and cannot be reproduced occurs for a long time.

Abstract: A memory architecture design and strategy is provided using memory devices that would normally be considered disadvantageous, but by accommodating the data input, output, and other peripheral controller services, overall performance in this mode is optimized. The surprising result is that even though the choice of memory is inappropriate for the task based on the precepts of the prior art, the overall memory system is effective. Bank switching in DDR-SDRAM can be utilized to achieve technological feasibility without resorting to, for example, SRAM.

Abstract: In a wireless access control system, a method and system for providing indications of the state of a Wireless Access Point Module (WAPM) to an observer using at least one indicator mounted on the WAPM. The WAPM preferably provides indications of the version number of the software installed on the WAPM. Additionally, the WAPM may communicate with a WPIM. The WAPM may indicate that it is attempting to establish communication with said WPIM, is engaged in an error test with said WPIM, or has lost communication with said WPIM, for example.

Abstract: A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, and a controlling integrated circuit which is provided in the memory system in the package, and when an instruction of data transfer within the memory system is received from exterior of the package, controls an execution of the data transfer to be executed within the memory system such that data of memory cells at addresses of a first memory integrated circuit are read out, and the readout data are written into memory cells at addresses of a second memory integrated circuit.

Abstract: An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A storage control device of bank structure is provided which comprises a CPU 1 and a storage 2 connected to CPU 1. Storage 2 detects and temporarily holds one of the bank addresses 0DF00h-7DF07h of the bank memories 9 to be read out next by CPU 1 when one of the bank memories 9 is read out by CPU 1 so that storage 2 supplies the held bank address 0DF00h-7DF07h to a memory control device 3 which thereby is switched to a next bank memory when CPU 1 produces a next retrieval signal. Accordingly, CPU 1 of small capacity reads information from storage of larger capacity to operate a controlled system connected to CPU 1 of the storage control device.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address.

Abstract: Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

Abstract: Methods and apparatus for migrating a data set. In one embodiment, a migration is paused. In another embodiment, for a migration of data between multiple source/target groups, the migration is initiated by beginning transfer for some groups and queuing others for later processing. In a further embodiment, different transfer vehicles are used for different source/target groups. In a still further embodiment, a transfer vehicle is automatically selected for at least one source/target group.

Abstract: A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data written to a group of columns during a burst write operation. The burst columns are generated using an internal counter and an externally provided start address. Repeating sequences of commands and data packets are provided to the memory device. An externally provided data mask signal is used to write one of the data packets to the memory on each of the sequences.

Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

Abstract: A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to store a preferred memory device voltage configuration corresponding to a preferred operating voltage of the memory device. The preferred memory device voltage configuration is readable by a host and the circuit is responsive to a command to modify the voltage to the memory device in accordance with the preferred memory device configuration. The voltage to the memory device is modified for improved performance and compatibility of the memory device with a host system.

Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

Abstract: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Abstract: A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.

Abstract: One processing section 131 executes a process of generating image data K representing a black image on the basis of the image data Y, M, and C, and sequentially executes a process of removing elements of the black image contained in the image data Y, from the image data Y, a process of removing the elements of the black image contained in the image data M, from the image data M, and a process of removing the elements of the black image contained in the image data C, from the image data C.

Abstract: Disclosed is a multiprocessor system using a plurality of multi-chip packages mounted with at least one processor and at least one memory, wherein: the number of memory access to the memory by the processor is recorded, and if the number of memory access across different multi-chip packages exceeds the number of memory access within the same multi-chip package, the memory contents are swapped. A memory access load distributing method in a multiprocessor system is also disclosed.

Abstract: A method for migrating from a source storage system to a target storage system includes defining a volume defined on a device to be migrated in the source storage system as an external volume to the target storage system; causing the host to access the volume on the drive to be migrated through an input/output port of the drive to be migrated as the external volume of the target storage system; blocking the other input/output port of the drive to be migrated while maintaining the access to the external volume of the target storage system; reconnecting the blocked input/output port with an interface in the target storage system; blocking the input/output port through which the external volume is being accessed, and connecting it with the interface in the target storage system; and implementing the drive to be migrated in the target storage system.

Abstract: A method and a system is provided for persistently storing and restoring objects of an object oriented environment established on a computer system having a volatile memory and a persistent storage. Pieces of memory, referred to as segments are allocated in the volatile memory. Then, a first list is created that contains first references to said segments. The segments are further divided into blocks. The blocks are indicated by second references. The second references are stored in a second list. In order to store an object present in the volatile memory, a block is allocated. Then an object description is created by saving the object's values of its variables. After saving the object description in the allocated block, a new element is added to the second list containing the particular reference to said created object description. Then, the references of the object descriptions of all other objects referenced in the present object are determined.

Abstract: A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.

Abstract: A method for storing data received from a host processor at a primary storage subsystem in a data storage system includes writing the data to a first volatile cache memory in the primary storage subsystem and copying the data from the primary storage subsystem to a secondary storage subsystem. The second subsystem writes the copied data to a second volatile cache memory and returns an acknowledgment to the primary storage subsystem responsively to writing the copied data to the second volatile cache memory and prior to saving the data in the second non-volatile storage media. The primary storage subsystem signals the host processor that the data have been stored in the data storage system responsively to the acknowledgment from the secondary storage subsystem.

Abstract: A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address. The current address corresponds to a current location in the memory. In addition, the method includes performing a data swap on data stored at the current location with data stored at the new location.

Abstract: A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during initialization. The memory hub controller and the memory hubs each transmit an initialization complete signal downstream when at least one receiver in the controller or hub is initialized and, in the case of the memory hubs, when a downstream initialization signal has also been received. Similarly, the memory hubs transmit an initialization signal upstream to another memory hub or the controller when both of its receivers are initialized and an upstream initialization signal has also been received. Receipt of an upstream initialization signal by the memory hub controller signifies that all of the receivers have been initialized.