Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization circuitry. In smaller systems, the CAM device determines the highest priority CAM device having a match. In larger systems, an external logic device determines the highest priority CAM device having a match and then provides that information to each CAM device in the system. In both smaller and larger systems the CAM device determines if it is the highest priority CAM device having a match. In accordance with an exemplary embodiment of the invention, the CAM device needs only minimal programming to be configured to be utilized in either a larger or smaller system.

Abstract: A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Abstract: Reference number 21 indicates a CPU, reference number 22 indicates a memory controller, and reference number 23 indicates a parameter set register group that has access parameters shared and used by banks. In the parameter set register group 23, parameter sets S0 to Sn having elements P0 to Pn exist. Reference number 24 indicates an external memory group to be finally accessed. A parameter set selection register 27 selects a parameter set among the parameter sets S0 to Sn of the parameter set register group 23 so as to be corresponded to each bank. The parameter set selection register 27 stores a unique identifier for each of banks B0 to Bm, which select the parameter sets S0 to Sn.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: A memory module includes a memory module controller to be coupled to a system memory controller by a system memory bus and a plurality of memory devices coupled to the memory module controller, where signaling between the memory module controller and one or more of the memory devices is independent of signal loading or operating voltage of the system memory bus.

Abstract: A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least tw

Abstract: A semiconductor device for outputting data read from a read only storage device, includes a plurality of read only storage devices, each including memory cells, a plurality of selecting signal lines for transmitting selecting signals to the read only storage devices for indicating a read only storage device storing data to be read, an address signal line for transmitting an address signal to the read only storage devices for indicating an address of memory cells storing data to be read and a switching device. The switching device has an address storage circuit for storing address information of a defective memory cell and detecting whether or not selected memory cells include a defective memory cell, a data storage circuit for storing replacement data for memory cells including a defective memory cell, and a switching circuit.

Abstract: A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.

Abstract: A deinterleaver module in an OFDM wireless transceiver includes partitioned memory banks for storage of code word fragments from an interleaved data stream, each code word fragment associated with a prescribed subcarrier frequency. Each code word fragment includes a prescribed number of code word bits based on a prescribed modulation of the interleaved data stream, and the code word bits for each code word fragment are written into respective selected locations of the corresponding memory bank based on the prescribed modulation and the corresponding prescribed subcarrier frequency. Write enable signals, bit selection signals, and address signals for each of the code word bits are generated based on applying logical operands to a cascaded sequence of successively delayed signals synchronous with a local clock signal. The deinterleaver module outputs deinterleaved data from the memory banks based on parallel output of the respective stored code word bits from a selected address of the memory banks.

Abstract: A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.

Abstract: An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and registers) works for variable P,D,m. This is achieved by decomposing the (P,D,m) interleaver into a concatenation of a multiplexed interleaver (implemented with A+1 memory locations), followed by a block interleaver (implemented with 2P memory locations). In many applications, these 2P memory locations can be treated as part of the memory for controlling the data flow of the system.

Abstract: A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

Abstract: A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Abstract: A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during initialization. The memory hub controller and the memory hubs each transmit an initialization complete signal downstream when at least one receiver in the controller or hub is initialized and, in the case of the memory hubs, when a downstream initialization signal has also been received. Similarly, the memory hubs transmit an initialization signal upstream to another memory hub or the controller when both of its receivers are initialized and an upstream initialization signal has also been received. Receipt of an upstream initialization signal by the memory hub controller signifies that all of the receivers have been initialized.

Abstract: A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction field is associated with each memory access operation. Memory access operations are selected for dispatch so that they are predicted to be non-conflicting. Preferably, the processor automatically maintains a bank predict value based on previous bank accesses, and a confirmation value indicating a degree of confidence in the bank prediction. The confirmation value is preferably an up-or-down counter which is incremented with each correct prediction and decremented with each incorrect prediction.

Abstract: A hardware circuit implemented on a DRAM foundry is provided for finding the longest prefix key match. The hardware circuit includes the use of prefix search engines to store prefix keys. Each prefix search engine may advantageously include an n-dimension memory for fast efficient access. Each prefix search engine is preassigned to store prefix keys having a specific length. Based on the preassignment and the n-dimensional memory, the hardware circuit matches the longest prefix key stored in the prefix search engines by comparing all prefix search engines in parallel.

Abstract: A method of accessing matrix data of a semiconductor memory having memory banks. The memory banks each having memory cells arranged in X and Y directions, a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on the memory banks being operable independently. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth in one of the banks. After all data have been written into or read from the specified memory cells, corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.

Abstract: The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory module groups are connected to the N system data buses and respectively have N memory modules. In each of the first through P-th memory module groups, a different one of the N system data buses is connected to each of the N memory modules, and each of the N system data buses has a data bus width of M/N bits. The first through P-th memory module groups are operated in response to first through P-th corresponding chip select signals. M is the bit-width of an entire system data bus of the semiconductor memory system. The N system data buses are wired such that data transmission times are the same from each N memory modules that operate in response to the same chip select signal to the memory controller.

Abstract: A memory device comprises a plurality of banks of storage locations accessible in response to access requests. Data refresh means are provided for refreshing data stored in the storage locations within prescribed times, whereby the memory device autonomously perform a refresh. A cache memory is embedded in the memory device. The cache memory has a plurality of cache storage locations for storing data contained in recently accessed storage locations. Access control means control the access to the storage locations and to the cache storage locations in response to the access requests: an access request is diverted to the cache memory whenever access to anyone of the recently accessed storage locations is requested. Any cache storage location is freely associable to any storage location in any bank, the association between any cache storage location and a storage location in the plurality of banks being established by a storage location association table in the access control means.

Abstract: Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Abstract: A CPU determines whether the intended use of the image data to be stored in a plurality of HDDs has a first-type purpose, which requires storing temporarily stored image data for carrying out output processing of the image data, or a second-type purpose, which requires long-term preservation of the image data. If the first-type intended use is determined, a first-type mode for saving is selected, wherein the image data to be stored are divided and each divided set of image data is stored into one HDD. If the second-type intended use is determined, a second-type mode for saving is selected, wherein the same image data part is saved in a plurality of storage means.

Abstract: Secondary or augmented control of a storage array in a cost effective manner is accomplished by connecting a host to the storage array via a storage adapter independent of a RAID controller. The RAID controller provides primary control for services standard to the RAID controller. Augmented or enhanced services as well as backup control are provided by a control module executing on the host, communicating to one or more selected storage devices within the storage array via the storage adapter. In one embodiment, the control module detects faults or failures in the RAID controller, selectably directs storage commands to the RAID controller, emulates a storage controller including a RAID controller, and provides enhanced or augmented services such as conducting diagnostic, firmware update, or disaster recovery operations.

Abstract: The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module and a memory device and is configured to receive initialization control commands and associated configuration information from the configuration module, and to send memory initialization commands to the memory device based on received initialization control commands and associated configuration information.

Abstract: The disclosed embodiments provide for a system and method for storing data in a flash memory device that has a code bank and a data bank. The method includes writing data to the data bank under control of a flash driver in the code bank when sufficient space is expected to exist in the data bank. Otherwise, the method includes writing data to the code bank under control of a flash driver in a storage device that is external to the flash memory device.

Abstract: This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with the new architecture. A method for handling errors is included in another embodiment with the new architecture.

Abstract: A virtualization switch virtualizes a data storage area provided by a server device and provides it to a server device. This virtualization switch processes a priority control and a bandwidth control also on the output side to packets which make an access to a virtual volume and which have different demands for a QoS but identical IP headers according to a discrimination result of a TCP connection. Here, the TCP connection is discrimination by managing a TCP source port on the side of the virtualization switch.

Abstract: Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.

Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used to some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus, increasing performance and decreasing program memory usage.

Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.

Abstract: A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.

Abstract: In one embodiment of the present invention, a method includes sensing a first burst length of data equal to half of a sense width of a plurality of sense amplifiers of a memory, and sensing a second burst length of data equal to the half of the sense width during a latency while sensing the first burst length of data.

Abstract: A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2 cache, the old data at that location is passed through the crossbar switch to a second bank of the L2 cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i.e., stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.

Abstract: Methods and apparatus for allow different mapping implementations, including a many-to-one logical to physical block mapping, to be used within a memory system are disclosed. According to one aspect of the present invention, a method for mapping a plurality of logical blocks to a physical block includes identifying a first logical block meets at least one criterion. The method also includes identifying a second logical block which is substantially complementary to the first logical block, and providing contents associated with the first logical block and contents associated with the second logical block to the physical block.

Abstract: The present invention provides a data processing apparatus and method for accessing memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled via a device bus with the memory, the device being operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data. In accordance with the invention, the memory access request as issued by the device includes a domain signal identifying whether the memory access request pertains to either the secure domain or the non-secure domain.

Abstract: The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register is used in the present invention to store the status values. When operating, the CPU accesses one port in accordance with the application program. The status values of the other ports are mapped to the global register. Therefore, the CPU also can understand the other ports status through the global register when accessing one port.

Abstract: The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.

Abstract: A specialized memory chip which includes an embedded application specific signal processing unit ASSPU. The ASSPU handles one or more predetermined tasks instead of a main processing unit. The ASSPU and the main processing unit can access memory on the memory chip simultaneously.

Abstract: Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are operated alternately to obtain an apparent operating speed equivalent to that of a CPU. Read clock generating circuits are placed in close proximity to clock input pins of respective ones of the flash ROMs and supply the flash ROMs with read clocks obtained by dividing down the frequency of a system clock. Delay ascribable to wiring is eliminated from the read clocks as a result.

Abstract: A computer body outputting a predetermined number of address signals A0 to A11 and a plurality of select signals CSO and CSI, generates a memory select signal CS and an additional address signal A12 added to the signals A0 to A11 according to the inputted signals CSO and CSI, and provides the signal CS, signal A12, and signals A0 to AI1 to a 256-megabit SDRAM (memory), so that the computer body can access the corresponding data. The computer body can access the data corresponding to the generated additional address signal A12 and predetermined number of the address signals A0 to A11.

Abstract: An apparatus, and method and computer program thereof, comprises a plurality of ports each adapted to receive packets of data; a memory controller core adapted to generate one or more memory transactions for each of the packets of the data, wherein each memory transaction comprises a payload having a size of m bytes, and wherein the payloads contain the data; a memory comprising a plurality of memory banks adapted to store the data, wherein the memory can receive no more than n bytes of data in a single memory transaction; and a memory interface adapted to transmit the memory transactions to the memory; wherein m=kn and k is an integer.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract: A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.

Abstract: Methods and apparatus are provided for closely coupling a dedicated memory port to a processor core while allowing external components access to the dedicated memory. A processor core such as a processor core on a programmable chip is provided with dedicated read access to a dual ported memory. Write access is arbitrated between processor core write access and read/write access by external components. A dedicated memory port is particularly beneficial in digital signal processing applications.

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.