Abstract: In one embodiment, a multi-tenant computing system includes at least one processor including a plurality of cores on which a plurality of agents of a plurality of tenants of the multi-tenant computing system are to execute, a configuration storage, and a memory execution circuit. The configuration storage includes a first configuration register to store configuration information associated with the memory execution circuit. The first configuration register is to store a mode identifier to identify a mode of operation of the memory execution circuit. The memory execution circuit, in a first mode of operation, is to receive encrypted data of a first tenant of the plurality of tenants, the encrypted data encrypted by the first tenant, generate an integrity value for the encrypted data, and send the encrypted data and the integrity value to a memory, wherein the integrity value is not visible to the software of the multi-tenant computing system.

Abstract: A storage device includes: a memory device including a plurality of memory blocks; a buffer memory device including first and second buffers which temporarily store write data; and a memory controller for controlling the memory device and the buffer memory device to perform a write operation of storing the write data in the memory device. The memory controller allocates a command to a mapping table including mapping information corresponding to a physical address according to a reception order of the command, when the memory controller receives the command from a host, and controls the buffer memory device such that write data is temporarily stored in a corresponding one of the first and second buffers. When write data temporarily stored in the first or second buffer is flushed to the memory device, the memory controller updates the mapping table, using mapping information corresponding to the flushed write data.

Abstract: Methods, systems, and devices for multiple flash translation layers (FTLs) at a memory device are described to support two or more FTLs within a memory device. A first FTL may be configured to support data mapping using a defined granularity and a second FTL may be configured to support data mapping using a smaller granularity than the defined granularity or data that does not match the defined granularity, based on one or more characteristics of the data. A memory device may select between the FTLs to map data based on the one or more characteristics of the data and may write the data to the memory device. The memory device may store logical-to-physical mapping associated with the data, among other information, using the selected FTL.

Abstract: A counter system includes a counter management subsystem, a storage subsystem having storage elements, and a non-volatile memory system storing a first counter including a first value field/first bitmap field combination for each storage element, and a second counter including a second value field/second bitmap field combination for each storage element. The counter management subsystem resets the first counter and, following each storage operation on a storage element, updates a bit in the first bitmap field for that storage element. When one of the first bitmap fields is filled, the counter management subsystem converts each first value field/first bitmap field combination to a respective first value, resets the second counter, updates the second value field for each storage element with the respective first value for each storage element and, following each storage operation on a storage element, updates a bit in the second bitmap field for that storage element.

Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.

Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).

Abstract: Technologies for memory management with memory protection extension include a computing device having a processor with one or more protection extensions. The processor may load a logical address including a segment base, effective limit, and effective address and generate a linear address as a function of the logical address with the effective limit as a mask. The processor may switch to a new task described by a task state segment extension. The task state extension may specify a low-latency segmentation mode. The processor may prohibit access to a descriptor in a local descriptor table with a descriptor privilege level lower than the current privilege level of the processor. The computing device may load a secure enclave using secure enclave support of the processor. The secure enclave may load an unsandbox and a sandboxed application in a user privilege level of the processor. Other embodiments are described and claimed.

Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

Abstract: A system and method for reordering data blocks received from a zone of a memory device. An example method includes sending, by a host system to a memory sub-system comprising a memory device, a plurality of write commands; receiving, by the host system from the memory sub-system, block allocation metadata, wherein the block allocation metadata references one or more locations in the memory device corresponding to a zone; generating, by the host system, a reorder map based on the block allocation metadata; reading a plurality of data blocks associated with the zone; and reordering, by the host system, the plurality of data blocks based on the reorder map.

Abstract: A method, system and computer-usable medium for identifying probability distributions. The identifying probability distributions includes receiving a stream of events, the stream of events comprising a plurality of events; extracting features from the plurality of events, at least some extracted features corresponding to interrelated events; identifying items of interest based upon the interrelated events; and, generating a distribution value based upon the items of interest.

Abstract: A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

Abstract: A data storage device including, in one implementation, a non-volatile memory device having a memory block including a number of memory dies, and a controller coupled to the non-volatile memory device. An activity level of the data storage device is monitored to determine whether the data storage device is in an idle condition based on the monitored activity level. Background operations are performed in response to the data storage device being determined to be in an idle condition Relocation operations are then performed in response to determining that the data storage device remains in the idle condition, wherein the relocation operations are executed in an order based on a priority level associated with each of the relocation operations.

Abstract: A basic storage unit management circuit includes a receiving circuit, a transmitting circuit, a first buffer, and an idle basic storage unit controller. The first buffer is arranged to store a bit map, wherein the bit map includes a plurality of first bits that correspond to a plurality of basic storage units, respectively, and each of the plurality of first bits is arranged to label whether a corresponding basic storage unit is an idle basic storage unit. The idle basic storage unit controller is coupled to the receiving circuit, the transmitting circuit, and the first buffer, and is arranged to manage the bit map stored by the first buffer, and process at least one basic storage unit of at least one packet that is received by the receiving circuit or is transmitted by the transmitting circuit.

Abstract: A method for dynamically managing host read operation and read refresh operation in a storage device, a storage device and a storage medium thereof are provided. The method includes: controlling, by a controller of the storage device, a ratio of the number of host read operation to the number of read refresh operation in the storage device to be in line with a first value and obtaining a total read request count which accumulates in the storage device; when a criterion for updating the ratio is satisfied, determining, by the controller, a second value for the ratio of the number of host read operation to the number of read refresh operation according to the total read request count and information of blocks to be refreshed in the storage device; and controlling, by the controller, the number of host read operation and the number of read refresh operation so that a ratio of the number of host read operation to the number of read refresh operation is in line with the second value.

Abstract: The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings.

Abstract: A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.

Abstract: A plurality of codewords are programmed to one or more memory pages of a memory sub-system. Each memory page of the memory sub-system is associated with a logical unit of a plurality of logical units of the memory sub-system and at least one of a plane of a plurality of planes of the memory sub-system or a block of a plurality of blocks of the memory sub-system. Each codeword of the plurality of codewords comprises host data and base parity bits. A plurality of additional parity bits are programmed to the one or more memory pages of the memory sub-system, wherein each additional parity bit of the plurality of additional parity bits is associated with a codeword of the plurality of standard codewords. A first set of redundancy metadata is generated corresponding to each of the additional parity bits. The first set of redundancy metadata is programmed to a memory page separate from any memory page storing the additional parity bits.

Abstract: A storage device includes a first physical space including first nonvolatile memory devices, a second physical space including second nonvolatile memory devices physically isolated from the first nonvolatile memory devices, and a storage controller that fetches a command from an external device and performs an operation corresponding to the command in any one of the first and second physical spaces, based on information included in the fetched command.

Abstract: A processing device of a memory sub-system is configured to determine, for a memory unit of the memory device, a plurality of write disturb counts associated with the memory unit, wherein each of the plurality of write disturb (WD) count is associated with a corresponding write disturb direction; compute, for the memory unit, a weighted WD count reflecting the plurality of write disturb counts; determine whether the weighted WD count meets a criterion; and responsive to determining that the weighted WD count meets the criterion, perform a refresh operation on the memory unit.

Abstract: A system for file system data access can include memory devices including a non-volatile memory device, as well as a processing device, operatively coupled with the memory devices to perform operations including receiving a file system (FS) write command and determining whether a write count of a physical super management unit (PSMU) of the non-volatile memory device satisfies a threshold criterion. The operations can include, recording a change of a super management unit (SMU) mapping for FS data of an FS mapping table, where the FS mapping table is a portion of a logical-to-physical (L2P) mapping table and performing a move of SMU data corresponding to the change of the SMU mapping. They can also include creating a backup copy of the FS mapping table on the non-volatile memory device, and restoring the FS mapping table from the backup copy of the FS mapping table.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: A memory controller includes: a map cache area for storing a map cache lines including mapping information between a logical address and a physical address; a victim map cache line selector for selecting a victim map cache line among the map cache lines, using a victim map cache line selection model trained by using a storage state information as training data, when a physical address corresponding to a logical address of an operation request is absent in the map cache area; and a map data controller for removing the selected victim map cache line from the map cache area, providing the removed victim map cache line to a memory device, receiving a target map cache line including the physical address corresponding to the logical address of the operation request from the memory device, and storing the target map cache line in the map cache area.

Abstract: A programmable data storage device includes: a non-volatile memory; a storage controller configured to control the non-volatile memory; a network interface; and a field programmable gate array configured to: implement a blockchain algorithm; and store at least one block of a blockchain corresponding to the blockchain algorithm in the non-volatile memory via the storage controller; and a processor having memory coupled thereto, the memory having instructions stored thereon that, when executed by the processor, cause the processor to: send and receive one or more blocks of the blockchain via the network interface; and control the field programmable gate array to execute the blockchain algorithm on the one or more blocks of the blockchain.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.

Abstract: A technique of performing data reduction includes, upon detecting a match between similarity hashes of a candidate dataset and a target dataset, evaluating an adjacent candidate dataset and an adjacent target dataset for similarity with each other and, in response to confirming such similarity, performing data reduction of the adjacent candidate dataset with reference to the adjacent target dataset.

Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

Abstract: Optimizing multiple backup operations for multiple sources by discovering shared data routes between sources and targets for backup operations performed in a certain time period. Backups using shared routes use a Best Time Algorithm that determines a size of a dataset to be saved an available bandwidth in each transfer window of the time period, and then determines an order of the backup operations based on first ordering the backups based on decreasing dataset size and second ordering the transfer windows in order of decreasing bandwidth, and matching the backups to the transfer windows in accordance with the first ordering and second ordering. The optimum time represents a time to initiate each backup of the multiple backups that results in a shortest data transfer time over the entire time period.

Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.

Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates with the storage device in accordance with a non-volatile memory host controller interface specification. The host provides a customized module containing instructions for performing the operations of a customized command. The host sends an idle time command to the storage device for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device executes the idle time command, during which the module may be used by the controller of the storage device.

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Abstract: Systems and methods for managing write stream workload of video surveillance systems through playback workload triggered dynamic capture are described. A video camera may include a video image sensor for receiving video data. The video data may be written to a storage device. A request for access to the video data may then be received. An impact on a standard data write stream may be determined based on the time window determined for the access to the video data. At least one mitigation option may be initiated at the video image sensor as a result.

Abstract: A storage device comprises a controller and a plurality of nonvolatile memory devices. Maintenance conditions of the nonvolatile memory devices are monitored internally by the storage device. Upon determining that a maintenance condition is satisfied, the storage device notifies an external host. The controller may perform the maintenance operations on the plurality of nonvolatile memory devices with little disruption to the host and assure data is reliably maintained by the nonvolatile memory devices.

Abstract: A storage device can be designed to reduce latency in a read operation. Such a storage device can include: a memory device including a plurality of pages that include a first page and a second page different from the first page, each page including a plurality of memory cells that are configured to store data; and a memory controller in communication with the memory device and for sequentially storing result values of a function with respect to a plurality of input values in the plurality of memory cells, and controlling the memory device to store a result value in a last area of the first page and a start area of the second page.

Abstract: Each of a plurality of memory blocks of a nonvolatile memory device is divided into two or more wordline groups having different characteristics. A write command for at least two memory blocks among the plurality of memory blocks is received. During a first partial time interval included in an entire write time interval for two or more memory blocks, a data write operation is performed on a wordline group included in one memory block among the two or more memory blocks in response to a reception of an address for the one memory block. During a second other partial time interval included in the entire write time interval, a data write operation is performed on wordline groups included in the two or more memory blocks in response to a reception of an address for the two or more memory blocks.

Abstract: Systems and methods are provided for reading data from non-volatile storage devices and decoding the read data. A method may include obtaining a unique identifier for a storage location to be read, retrieving from a memory an adjustment to read reference voltage (Vref) associated with the unique identifier, performing a read operation on the storage location using a read reference voltage adjusted by the adjustment to Vref, decoding data read from the storage location in a decoding process and updating the adjustment to Vref with decoding information generated during the decoding process.

Abstract: A central processing unit of a host system is used to manage at least a portion of a data placement of a storage device including by bypassing a storage controller processing unit of the storage device to store data in a random-access memory of the storage device while allowing media endurance management of the storage device to be managed by the storage controller processing unit of the storage device. The central processing unit of the host system to the storage device provides a command that causes the storage controller processing unit of the storage device to utilize the data stored by the central processing unit of the host system in the random-access memory of the storage device.

Abstract: Disclosed herein is a device equipped with flash memory, which includes memory in which at least one program is recorded and a processor for executing the program. The memory includes flash memory including a data area and a backup area, and the program divides data into two or more segments depending on whether the data can be stored in a single page and stores the same in the data area. The first segment is stored in a page along with a segment number, indicating the sequential position of the divided data, a segment offset, indicating the number of pages between the pages in which the current segment and the next segment are stored, the size of a data file name, the size of the data, and the file name. At least one additional segment may be stored in another page along with the segment number and segment offset thereof.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

Abstract: A system and method for notifying a process about a creation or removal event of a named data element (NDE) in a coordination namespace distributed memory system. A controller runs methods to: generate a tuple corresponding to data generated by a requesting process, the tuple having a tuple name and data value; and generate a notification indicator in a pending notification list to indicate to one or more processes a notification of the creation or removal event associated with the corresponding tuple. Upon detecting the event performed on the tuple by a second process, the method further searches for NDEs in the distributed memory system having the same tuple name, and in response to determining an existence of an associated pending notification record in a pending notification list of records, notify each corresponding process of the one or more processes indicated in the list of the creation or removal event.

Abstract: Methods, systems, and devices for access of a memory system based on fragmentation are described. The memory system may receive a first message indicating a set of data that the memory system is to store using a fragmentation-based write procedure. The memory system may, based on the first message, determine blocks of a memory device that satisfy a fragmentation threshold. After determining the blocks, the memory system may transmit to the host system a second message that indicates the memory system is ready to receive the set of data indicated in the first message. The memory system may then store the set of data in the determined blocks based on transmitting the second message.

Abstract: A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.

Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.

Abstract: Methods, systems, and devices for multi-stage memory device performance notification are described. A memory system may include a first set of memory cells of a first type associated with a first performance level and a second set of memory cells of a second type associated with a second performance level. The memory system may have an interface and a control circuit coupled with the first and second sets of memory cells. The control circuit may be configured to determine a first parameter associated with a transition between the first performance level and the second performance level. The control circuit may also be configured to store the first parameter in a first register based at least in part on determining the first parameter.

Abstract: Various methods, apparatuses/systems, and media for PaaS cloud ready random access report generation are disclosed. A processor receives an initial intermediate file having intermediate contents to be utilized for PaaS cloud ready random access report generation; determines whether the intermediate contents exceed a predetermined memory threshold value; implements a first mode of report generation algorithm to create a final intermediate file when it is determined that a memory requirement for the intermediate contents is equal to or below the predetermined memory threshold value or implement a second mode of report generation algorithm to create the final intermediate file when it determined that the memory requirement for the intermediate contents exceed the predetermined memory threshold value; transmits the final intermediate file to a rendering engine; and generates a report based on the final intermediate file.

Abstract: A memory system, a memory controller and an operating method are disclosed. A first area, a second area included in the first area, and a third area are set. An area to which target data is to be written is determined to the first area or the third area. When the target data is written to the first area, the target data is preferentially written to the second area. The number of data bits stored per memory cell in the first area is less than the number of data bits stored per memory cell in the third area. As a consequence, it is possible to secure storage capacity of the memory system to at least a set reference while securing data write performance of the memory system recognized by a host to at least a set reference.

Abstract: Systems, methods and apparatus of recordation of vehicle data associated with errant vehicle behavior. For example, a vehicle includes: sensors configured to generate sensor data; control elements configured to generate control signals to be applied to the vehicle in response to user interactions with the control elements; electronic control units configured to provide status data in operations of the electronic control units; and a data storage device. The data storage device is configured to receive input data including the sensor data, the control signals and the status data, store the input data in a cyclic way in an input partition over time, generate a classification of errant behavior based on the input data and using an artificial neural network, and preserve a portion of the input data associated with the classification of errant behavior.

Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.

Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.