Abstract: A system controller includes an output unit which transfers an access request from an access source coupled to the system controller to an other system controller; a local snoop control unit that determines whether a destination of the access request from the access source is a local memory unit coupled to the system controller, and locks the destination when the destination is the local memory unit; a receiving unit which receives the access request from the output unit and an access request from an other system controller; a global snoop control unit which sends a response indicating whether the access request is executable or not, and controls locking of the destination of the access request when the destination is the local memory unit; and an access processing unit which unlocks the locking and accesses the memory unit when the access request from the access source becomes executable.

Abstract: Systems, methods, and devices for reducing snoop traffic in a central processing unit are provided. In accordance with one embodiment, an electronic device includes a central processing unit having a plurality of cores. A cache memory management system may be associated with each core that includes a cache memory device configured to store a plurality of cache lines, a page status table configured to track pages of memory stored in the cache memory device and to indicate a status of each of the tracked pages of memory, and a cache controller configured to determine, upon a cache miss, whether to broadcast a snoop request based at least in part on the status of one of the tracked pages in the page status table.

Abstract: Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.

Abstract: In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.

Abstract: A data processing system has a cache which receives both non-debug snoop requests and debug snoop requests for processing. The non-debug snoop requests are generated in response to transactions snooped from a system interconnect. Debug control circuitry that is coupled to the cache provides the debug snoop requests to the cache for processing. The debug snoop requests are generated in response to debug snoop commands from a debugger and without the use of the system interconnect. In one form snoop circuitry has a snoop request queue having a plurality of entries, each entry for storing a snoop request. A debug indicator corresponding to each snoop request indicates whether the snoop request is a debug snoop request or a non-debug snoop request.

Abstract: Embodiments of the invention provide a method, system, and computer program product for cache-line based notification. An embodiment of the method comprises injecting a cache-line including notification information into a cache of a processing unit, marking the cache-line as having the notification information, and using the notification information to notify a processing thread of the presence of the cache-line in the cache. In an embodiment, the cache-line identifies a thread affiliation. In an embodiment, a multitude of threads operate in the processing unit, and the using includes notifying a plurality of these threads of the presence of the cache-line in the cache, and analyzing the cache-line to identify this plurality of threads. The cache may include a plurality of cache-lines, each of which includes a notification, and the processing unit thread uses these notifications to form a linked list of at least some of the cache-lines.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.

Abstract: A computer-implemented method, data processing system, and computer usable program code are provided for reducing memory access latency. A memory controller receives a memory access request and determines if an address associated with the memory access request falls within an address range of a plurality of paired memory address range registers. The memory controller determines if an enable bit associated with the address range is set to 1 in response to the address falling within one of the address ranges. The memory controller flags the memory access request as a high-priority request in response to the enable bit being set to 1 and places the high-priority request on a request queue. A dispatcher receives an indication that a memory bank is idle. The dispatcher determines if high-priority requests are present in the request queue and, if so, sends the earliest high-priority request to the idle memory bank.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.

Abstract: A data processing system including a plurality of processors 4, 6, 8 each having a local cache memory 10, 12, 14 is provided. A cache coherency controller 16 serves to maintain cache coherency between the local cache memories 10, 12, 14. When one of the processors 4, 6, 8 is placed into a low power state its associated local cache memory 10, 12, 14 is maintained in a state in which the data it is holding is accessible to the cache coherency controller 16 until a predetermined condition has been met whereupon the local cache memory 10, 12, 14 concerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.

Abstract: A lease system is described herein that allows clients to request a lease to a remote file, wherein the lease permits access to the file across multiple applications using multiple handles without extra round trips to a server. When multiple applications on the same client (or multiple components of the same application) request access to the same file, the client specifies the same lease identifier to the server for each open request or may handle the request from the cache based on the existing lease. Because the server identifies the client's cache at the client level rather than the individual file request level, the client receives fewer break notifications and is able to cache remote files in more circumstances. Thus, by providing the ability to cache data in more circumstances common with modern applications, the lease system reduces bandwidth, improves server scalability, and provides faster access to data.

Abstract: A data processing apparatus and method are provided for handling memory access requests to shared memory. The data processing apparatus has a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state. The processing units share a memory, and at least one local storage unit is configured to store a local copy of a data item stored in the memory for access by an associated processing unit. A snoop control unit is configured to monitor memory access requests issued by the processing units and to store in the snoop control unit indications of local copies of data items stored in each local storage unit.

Abstract: In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.

Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.

Abstract: A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data.

Abstract: Deadlocks are avoided by marking read requests issued by a parallel processor to system memory as “special.” Read completions associated with read requests marked as special are routed on virtual channel 1 of the PCIe bus. Data returning on virtual channel 1 cannot become stalled by write requests in virtual channel 0, thus avoiding a potential deadlock.

Abstract: A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor.

Abstract: A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.

Abstract: A data processing system is described that reduces read latency of requested memory data, thereby resulting in improved system performance. An exemplary system includes a bus, a processor, and a controller associated with the processor. The controller is configured to send a request for data to a memory storage unit, receive, from the memory storage unit, an early response indicating that the controller will later receive the requested data, and upon receipt of the early response indicator, start a timer to wait a period of time. The controller is further configured to, after expiration of the timer but prior to receipt of the requested data, send an arbitration request to initiate a transaction on the bus to communicate the requested data from the controller to the processor when the requested data is later received by the controller.

Abstract: In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.

Abstract: A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.

Abstract: A technique for performing cache injection includes monitoring, at a cache, addresses on a bus. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache. A replacement policy position of the data block is then modified (to increase a probability that the data block is consumed prior to ejection from the cache).

Abstract: A technique for performing cache injection includes monitoring addresses on a bus in response to a cache injection instruction. Ownership of input/output data on the bus is acquired by a cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block associated with the cache injection instruction.

Abstract: The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least two of the processing units having a cache associated therewith for storing a subset of the data for access by that processing unit. A snoop-based cache coherency protocol is employed to ensure data accessed by each processing unit is up-to-date, and when an access request is issued the cache coherency protocol is referenced in order to determine whether a snoop process is required. Snoop control storage is provided which defines a plurality of snoop schemes, each snoop scheme defining a series of snoop phases to be performed to implement the snoop process, and each snoop phase requiring a snoop operation to be performed on either a single cache or multiple caches.

Abstract: In a data processing system each bus master of a plurality of bus masters communicates information via a system interconnect. A cache is associated with a predetermined bus master of the plurality of bus masters for storing information used by the predetermined bus master. A snoop queue is associated with the predetermined bus master for storing a plurality of snoop requests and selectively storing for each snoop request an indicator of a synchronization request that indicates a synchronization operation is to be performed by completing any previously issued snoop requests prior to or concurrently with completion of the synchronization operation. In one form the indicator is a synchronization request indicator flag for each entry in the snoop queue that indicates whether each entry participates in the synchronization operation associated with the synchronization request.

Abstract: A method for directing cache injection based on actual system load may include providing a snooping-based fabric having two or more bus-coupled units. At least one of the bus-coupled units may be configured as an injection unit for directing cache injection. A snoop request may be transmitted from the injection unit to one or more destination units of the other bus-coupled unit. The snoop request may include an identification value having a function identifier. The function identifier may identify a destination function for the cache injection, where the destination function is configured to run on the destination unit. A snoop response may be transmitted from the destination unit to the injection unit in response to the snoop request. The snoop response may include a function response value indicating whether the function identifier matches a function indication of a snoop register for the destination unit.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to apply global ordering to the requests. A bus interface having request, snoop, and response logic is provided for each agent. A bus interface having request, snoop and response logic is provided for the global arbiter, and a bus interface is provided to couple the global arbiter to each type of fabric it is responsible for. Global ordering and arbitration logic tags incoming requests from the multiple agents and insures that snoops are responded to according to the global order, without regard to latency differences in the fabrics.

Abstract: The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations.

Abstract: In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.

Abstract: A method includes detecting a bus transaction on a system interconnect of a data processing system having at least two masters; determining whether the bus transaction is one of a first type of bus transaction or a second type of bus transaction, where the determining is based upon a burst attribute of the bus transaction; performing a cache coherency operation for the bus transaction in response to the determining that the bus transaction is of the first type, where the performing the cache coherency operation includes searching at least one cache of the data processing system to determine whether the at least one cache contains data associated with a memory address the bus transaction; and not performing cache coherency operations for the bus transaction in response to the determining that the bus transaction is of the second type.

Abstract: A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Abstract: A method of data processing in a processing unit supported by a memory hierarchy includes the processing unit performing a plurality of memory accesses to the memory hierarchy. The plurality of memory accesses includes one or more memory accesses targeting a full cache line of data. The processing unit monitors utilization of data accessed by the plurality of memory accesses, and based upon the utilization of the data, dynamically alters a memory access mode of operation so that a subsequent storage-modifying memory access targets less than a full cache line of data.

Abstract: According to at least one embodiment, a method of data processing in a multiprocessor data processing system includes a requesting processing unit initiating an interconnect operation including a memory access request that indicates an acceptability of a variable amount of data to service the interconnect request for data. In response to snooping the memory access request on an interconnect, a snooper selects an amount of data to supply to the requesting processing unit and transmits the selected amount of data to the requesting processing unit. The requesting processing unit receives the selected amount of data and utilizes at least some of the selected amount of data to service a processor request.

Abstract: An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect.

Abstract: Presented herein are system(s) and method(s) for a multiple miss cache. In one embodiment, there is presented a cache system for storing data. The cache comprises a plurality of data words, a plurality of first bits, and a plurality of second bits. The plurality of data words store data. The plurality of first bits correspond to particular ones of the plurality of data words, each of the plurality of bits indicating whether the data word corresponding thereto stores valid data. The plurality of second bits correspond to particular ones of the plurality of data words, each of the plurality of bits for indicating whether a cache miss has occurred with the data word corresponding thereto.

Abstract: A multi processor system 1 comprises a plurality of processors 21 to 25, a system bus 30 and a main system memory 40. Each processor 21 to 25 is connected to a respective cache memory 41 to 45, with each cache memory 41 to 45 in turn being connected to the system bus 30. The cache memories 41 to 45 store copies of data or instructions that are used frequently by the respective processors 21 to 25, thereby eliminating the need for the processors 21 to 25 to access the main system memory 40 during each read or write operation. Processor 25 is connected to a local memory 50 having a plurality of data blocks (not shown). According to the invention, the local memory 50 has a first port 51 for connection to its respective processor 25. In addition, the local memory 50 has a second port 52 connected to the system bus 30, thereby allowing one or more of the other processors 21 to 24 to access the local memory 50.

Abstract: A data processing apparatus 2 includes a programmable general purpose processor 10 coupled to a hardware accelerator 12. A memory system 14, 6, 8 is shared by the processor 10 and the hardware accelerator 12. Memory system monitoring circuitry 16 is responsive to one or more predetermined operations performed by the processor 10 upon the memory system 14, 6, 8 to generate a trigger to the hardware accelerator 12 for it to halt its processing operations and clean any data values held as temporary variables within registers 20 of the hardware accelerator back to the memory system 14, 6, 8.

Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.

Abstract: In a network-based cache-coherent multiprocessor system, when a node receives a cache request, the node can perform an intra-node cache snoop operation and forward the cache request to a subsequent node in the network. A snoop-and-forward prediction mechanism can be used to predict whether lazy forwarding or eager forwarding is used in processing the incoming cache request. With lazy forwarding, the node cannot forward the cache request to the subsequent node until the corresponding intra-node cache snoop operation is completed. With eager forwarding, the node can forward the cache request to the subsequent node immediately, before the corresponding intra-node cache snoop operation is completed. Furthermore, the snoop-and-forward prediction mechanism can be enhanced seamlessly with an appropriate snoop filter to avoid unnecessary intra-node cache snoop operations.

Abstract: A memory access controlling apparatus, for monitoring an access of a memory to generate a target watch signal, includes: at least one monitoring circuit, a setting unit and an output circuit. The monitoring circuit corresponds to an address of the memory and holds an access setting value. The monitoring circuit monitors the access of the memory according to the access setting value to generate an initial watch signal. The setting unit holds a setting value for triggering an exception, which is related to a condition for triggering the exception while the memory is accessed. The output circuit is coupled to the monitoring circuit and the setting unit, and is used for generating the target watch signal according to the initial watch signal and the setting value.

Abstract: A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

Abstract: A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

Abstract: A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

Abstract: A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.

Abstract: A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes.

Abstract: A snoop request cache maintains records of previously issued snoop requests. Upon writing shared data, a snooping entity performs a lookup in the cache. If the lookup hits (and, in some embodiments, includes an identification of a target processor) the snooping entity suppresses the snoop request. If the lookup misses (or hits but the hitting entry lacks an identification of the target processor) the snooping entity allocates an entry in the cache (or sets an identification of the target processor) and directs a snoop request such to the target processor, to change the state of a corresponding line in the processor's L1 cache. When the processor reads shared data, it performs a snoop cache request lookup, and invalidates a hitting entry in the event of a hit (or clears it processor identification from the hitting entry), so that other snooping entities will not suppress snoop requests to it.

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, read rate, number of read requests, write rate, number of write requests, rate or percentage of memory bus utilization, local hub request rate or number, and/or remote hub request rate or number.