Abstract: A system for optimization of variables is provided. The system includes a buyer finance system for receiving asset data and buyer finance data. A seller variable system receives the asset data and the buyer finance data and applies a seller variable distribution to generate seller transaction state data. A finance variable system receives the asset data and the buyer finance data and applies a finance variable distribution to generate finance transaction state data. A variable optimization system receives the seller transaction state data and the finance transaction state data and generates transaction approval data.

Abstract: A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.

Abstract: Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of a data block is stored in the phase change memory and a second portion of the data block is stored in the FLASH memory. The first portion of the data block is accessed prior to the second portion of the data block during a read operation.

Abstract: An emulation processing method causing a computer including a first and a second processor to execute emulation processing, the emulation processing method includes: calculate a next instruction address next to a received instruction address, and transmit, to the second processor, the calculated instruction address and instruction information read out on the basis of the calculated instruction address, transmit, to the first processor, a first instruction address that is an instruction address included in an execution result of executed processing, and execute processing based on the instruction information received from the first processor, when a second instruction address that is the instruction address received from the first processor is identical to the first instruction address, and read out instruction information on the basis of the first instruction address and execute processing based on the instruction information read out, when the second instruction address is not identical to the first instruct

Abstract: A graphics processing unit core 26 includes a plurality of processing pipelines 38, 40, 42, 44. A program instruction of a thread of program instructions being executed by a processing pipeline includes a next-instruction-type field 36 indicating an instruction type of a next program instruction following the current program instruction within the processing thread concerned. This next-instruction-type field is used to control selection of to which processing pipeline the next instruction is issued before that next instruction has been fetched and decoded. The next-instruction-type field may be passed along the processing pipeline as the least significant four bits within a program counter value associated with a current program instruction 32. The next-instruction-type field may also be used to control the forwarding of thread state variables between processing pipelines when a thread migrates between processing pipelines prior to the next program instruction being fetched or decoded.

Abstract: A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.

Abstract: A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly.

Abstract: The different advantageous embodiments provide an apparatus comprising a central processing unit, a microcode store, and a number of functional units. The central processing unit utilizes transport triggered architecture and is configured to execute microcoded instructions that allow a single instruction to be executed as multiple instructions. The microcode store includes a number of microcoded instruction implementations. The number of functional units includes a number of useful entry points into the microcode store.

Abstract: A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Abstract: The present invention provides a method and apparatus for handling lane-crossing instructions in an execution pipeline. One embodiment of the method includes conveying bits of an instruction from a register to an execution stage in a pipeline along a first data path that includes a lane crossing stage configured to change a first mapping of the register to the execution stage to a second mapping. The method also includes concurrently conveying the bits along a second data path from the register to the execution stage that bypasses the lane crossing stage. The method further includes selecting the first or second data path to provide the bits to the execution stage.

Abstract: A more efficient technique is provided in an information processing apparatus which executes processing using pipelines. An information processing apparatus according to this invention includes a first pipeline, second pipeline, processing unit, and reorder unit. The first pipeline has a plurality of first nodes, and shifts first data held in a first node to a first node. The second pipeline has a plurality of second nodes respectively corresponding to the first nodes of the first pipeline, and shifts second data held in a second node to a second node. The processing unit executes data processing using the first data and the second data. The reorder unit holds one of the output second data based on attribute information of the second data output from the second pipeline, and outputs the held second data to the second pipeline.

Abstract: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Abstract: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

Abstract: Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.

Abstract: Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

Abstract: A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

Abstract: A database of codesets for a remote control device includes codeset information blocks for derivative codesets and codeset information blocks for nonderivative codesets. A codeset information block for a derivative codeset includes: a bit indicating that the block is for a derivative codeset, a plurality of bits each of which corresponds to a respective one of a plurality of fields in a referenced codeset information block, and a pointer that points to the referenced codeset information block. The digital value of a bit determines whether information from the corresponding field in the referenced block will be used as part of the derivative codeset or whether such information is contained in the derivative codeset information block itself. The sizes of the fields in the referenced block are predetermined or are determinable, so a field in the referenced block can be located if its bit is set in the referencing block.

Abstract: A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to receive the branch direction signal and a peripheral device status notification signal indicating whether an operation performed in the peripheral device is being executed. The branch wait operation section outputs an instruction issue stop signal directing waiting of the branch operation to the program execution section if the branch direction signal is input during a period when the peripheral device status notification signal is active indicating that the operation in the peripheral device is being executed.

Abstract: A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprises first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.

Abstract: A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is analyzed. An instruction type associated with the at least one instruction is identified. At least one of a base field, an index field, one or more operands, and a mask field of the instruction are analyzed. At least one of the following is then performed: the at least one instruction is organized into a set of unit of operation; and the at least one instruction is shortened. The set of unit of operations is then executed.

Abstract: An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register.

Abstract: Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are included in the loop instruction. When a processor executes a loop instruction, it decodes the instruction, identifies the modifier register, and accesses the register value to determine if the processor will jump back based on the memory address information. The loop execution can incur no clock cycle penalties.

Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.

Abstract: Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction is valid; and a branch instruction execution unit which executes the branch instruction when the branch instruction is valid. The method includes: verifying whether the branch instruction is valid; and not executing the branch instruction when the branch instruction is invalid.

Abstract: A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative branch prediction efficiency may be represented by the average number of clocks per instruction (CPI), whereby an increase in the average CPI indicates that the processor is becoming less efficient due to incorrectly predicted speculative branch predictions and, conversely, a decrease indicates that the processor has a higher ratio of properly predicted speculative branch predictions.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a channel detector circuit. The channel detector circuit includes a branch metric calculator circuit that is operable to receive a number of violated checks from a preceding stage, and to scale an intrinsic branch metric using a scalar selected based at least in part on the number of violated checks to yield a scaled intrinsic branch metric.

Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.

Abstract: A system, processor and method are provided for digital signal processing A processor may initiate processing a sequence of instructions followed by an interrupt Each instruction may be processed in respective sequential pipeline slots A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program.

Abstract: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

Abstract: A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer and the circular instruction buffer. The instruction buffer stores a plurality of instructions, and the circular instruction buffer stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit decodes and pairs the instructions and the recovery instructions. When the branch mis-prediction occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit which is externally connected to the decoding and pairing circuit.

Abstract: Methods and systems for efficiently interpreting operating system service requests on the same register or vector of a processor or CPU where the operating system service requests are initiated from native and non-native applications are provided. More particularly, a switching layer can enable processing of the operating system service requests by routing control of a particular request to an appropriate kernel subsystem or module based on the type of operating system service being requested and the type of application initiating the request. Additionally, the performance impact of the switching layer for native applications is overcome by dynamically reprogramming the processor or CPU on every change of active process so that only foreign applications are subject to the processing requirements of the switching layer.

Abstract: Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.

Abstract: An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus.

Abstract: A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.

Abstract: A new computing machine and new methods of executing and solving heretofore unknown computational problems are presented here. The computing system demonstrated here can be implemented with a program composed of instructions such that instructions may be added or removed while the instructions are being executed. The computing machine is called a Dynamic Register Machine. The methods demonstrated apply to new hardware and software technology. The new machine and methods enable advances in machine learning, new and more powerful programming languages, and more powerful and flexible compilers and interpreters.

Abstract: A computer program product, apparatus, and method for processing a transport control channel program with chain linked branching in an I/O processing system are provided. The method includes receiving a command message at a control unit from an I/O subsystem to perform an I/O operation. The method further includes reading a chain linked flag in the command message indicating that a subsequent command message for the I/O operation follows the command message. The method also includes reading a serialization flag in the command message requesting that device status be returned to the I/O subsystem in order to select the subsequent command message. The method additionally includes executing one or more commands in the command message, and transmitting the device status to the I/O subsystem in response to executing the one or more commands in combination with the serialization flag.

Abstract: Method and apparatus for servicing commands such as the type issued by a host device to load an operating system from an associated data storage device. A controller is adapted to, upon receipt of a selected command sequence comprising a first command followed by a second command, determine an elapsed time interval between the first and second commands. The controller further uses the elapsed time interval to subsequently service the first and second commands during a subsequent receipt of the selected command sequence. Preferably, a command history table is generated to list the commands in the command sequence and the associated time intervals, and to use the time intervals to predict when the next command will occur. Readback data are pre-fetched to a buffer to expedite servicing of the commands, and the controller selectively enters one or more reduced power modes between successive commands to reduce power consumption levels.

Abstract: A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logic (113) outputs a prediction indicating in which one of the plurality of memories a target data is stored. The target memory prediction logic (113) outputs the prediction in the same processing cycle as the output of the target memory address by the address generation logic (109). An associated method is also provided.

Abstract: Herein described are at least a system and a method of reducing or decreasing the rate of interrupts transmitted by a device to a microprocessor. In a representative embodiment, the device comprises a universal asynchronous receiver/transmitter. In a representative embodiment, the rate of interrupts is reduced by receiving and using a first signal as an input to a first counter. The first counter outputs a first count, and compares the first count to a value provided by a memory. Subsequently, a second signal is generated to initiate an interrupt when the first count equals the value. In a representative embodiment, a system for delaying transmission of an interrupt from a universal asynchronous receiver/transmitter (UART) to a microprocessor comprises a counter capable of generating a count, a memory capable of storing a value, and a comparator used for comparing the count to the value.

Abstract: A technique for handling floating-point special values, e.g., Infinity, NaN, ?Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.

Abstract: In a method of linking to information in a deduplication data sequence, a branching point is identified. The branching point is a place where a branch data sequence diverges from a parent data sequence that has been previously stored in a data deduplication process. A signature value associated with a subsequence of the information represented in the branch data sequence is determined. A branch location where the information of the branch data sequence begins is identified. Link information is stored in association with the branching point. The link information is stored in a computer memory. The link information comprises a link to the branch location and also comprises a portion of the signature value.

Abstract: One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.

Abstract: The present invention comprises: a converting step for converting a source program into a machine language program; an inserting step for inserting notifying instructions for notifying that the source program has been executed in the machine language program; and a program generating step for generating the executable program from the machine language program in which the notifying instructions are inserted. Further, in the inserting step, the notifying instructions are placed at the entry points of each basic block that constitutes the machine language program and the notifying instructions to which the same conditions as those of the conditional instruction groups are granted are placed at the entry points of conditional instruction groups provided in the machine language program. In the program generating step, identification information for identifying the notifying instructions is granted to each of the notifying instructions.

Abstract: A frequency-based prediction of indirect jumps executing in a computing environment is provided. Illustratively, a computing environment comprises a prediction engine that processes data representative of indirect jumps performed by the exemplary computing environment according to a selected frequency-based prediction paradigm. Operatively, the exemplary prediction engine can keep track of targets, in a table, taken for each indirect jump and program context (e.g., branch history and/or path information) of an exemplary computing program. Further, the prediction engine can also store a frequency counter associated with each target in the exemplary table. Illustratively, the frequency counter can record the number of times a target was taken in the recent past executions of an observed one or more indirect jump. The prediction engine can supply the target address of an indirect jump based on the values of the frequency counters of each stored target address.

Abstract: The present invention provides a system and method for prioritizing branch instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: (1) receive an issue group of instructions; (2) determine if at least one branch instruction is in the issue group, if so scheduling the least one branch instruction in a one of the plurality of execution pipelines based upon a first prioritization scheme; (3) determine if there is an issue conflict for one of the plurality of execution pipelines and resolving the issue conflict by scheduling the at least one branch instruction in a different execution pipeline; (4) schedule execution of the issue group of instructions in the cascaded delayed execution pipeline unit.

Abstract: A database of codesets for a remote control device includes codeset information blocks for derivative codesets and codeset information blocks for nonderivative codesets. A codeset information block for a derivative codeset includes: a bit indicating that the block is for a derivative codeset, a plurality of bits each of which corresponds to a respective one of a plurality of fields in a referenced codeset information block, and a pointer that points to the referenced codeset information block. The digital value of a bit determines whether information from the corresponding field in the referenced block will be used as part of the derivative codeset or whether such information is contained in the derivative codeset information block itself. The sizes of the fields in the referenced block are predetermined or are determinable, so a field in the referenced block can be located if its bit is set in the referencing block.